Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 4 | * redistributing this file, you may do so under either license. |
| 5 | * |
| 6 | * GPL LICENSE SUMMARY |
| 7 | * |
| 8 | * Copyright(c) 2015 Intel Corporation. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of version 2 of the GNU General Public License as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, but |
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 17 | * General Public License for more details. |
| 18 | * |
| 19 | * BSD LICENSE |
| 20 | * |
| 21 | * Copyright(c) 2015 Intel Corporation. |
| 22 | * |
| 23 | * Redistribution and use in source and binary forms, with or without |
| 24 | * modification, are permitted provided that the following conditions |
| 25 | * are met: |
| 26 | * |
| 27 | * - Redistributions of source code must retain the above copyright |
| 28 | * notice, this list of conditions and the following disclaimer. |
| 29 | * - Redistributions in binary form must reproduce the above copyright |
| 30 | * notice, this list of conditions and the following disclaimer in |
| 31 | * the documentation and/or other materials provided with the |
| 32 | * distribution. |
| 33 | * - Neither the name of Intel Corporation nor the names of its |
| 34 | * contributors may be used to endorse or promote products derived |
| 35 | * from this software without specific prior written permission. |
| 36 | * |
| 37 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 38 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 39 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 40 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 41 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 42 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 43 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 44 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 45 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 46 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 47 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 48 | * |
| 49 | */ |
| 50 | |
| 51 | #ifndef _COMMON_H |
| 52 | #define _COMMON_H |
| 53 | |
| 54 | #include <rdma/hfi/hfi1_user.h> |
| 55 | |
| 56 | /* |
| 57 | * This file contains defines, structures, etc. that are used |
| 58 | * to communicate between kernel and user code. |
| 59 | */ |
| 60 | |
| 61 | /* version of protocol header (known to chip also). In the long run, |
| 62 | * we should be able to generate and accept a range of version numbers; |
| 63 | * for now we only accept one, and it's compiled in. |
| 64 | */ |
| 65 | #define IPS_PROTO_VERSION 2 |
| 66 | |
| 67 | /* |
| 68 | * These are compile time constants that you may want to enable or disable |
| 69 | * if you are trying to debug problems with code or performance. |
| 70 | * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in |
| 71 | * fast path code |
| 72 | * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be |
| 73 | * traced in fast path code |
| 74 | * _HFI1_TRACING define as 0 if you want to remove all tracing in a |
| 75 | * compilation unit |
| 76 | */ |
| 77 | |
| 78 | /* |
| 79 | * If a packet's QP[23:16] bits match this value, then it is |
| 80 | * a PSM packet and the hardware will expect a KDETH header |
| 81 | * following the BTH. |
| 82 | */ |
| 83 | #define DEFAULT_KDETH_QP 0x80 |
| 84 | |
| 85 | /* driver/hw feature set bitmask */ |
| 86 | #define HFI1_CAP_USER_SHIFT 24 |
| 87 | #define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1) |
| 88 | /* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */ |
| 89 | #define HFI1_CAP_LOCKED_SHIFT 63 |
| 90 | #define HFI1_CAP_LOCKED_MASK 0x1ULL |
| 91 | #define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT) |
| 92 | /* extra bits used between kernel and user processes */ |
| 93 | #define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2) |
| 94 | #define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \ |
| 95 | HFI1_CAP_MISC_SHIFT)) - 1) |
| 96 | |
| 97 | #define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; }) |
| 98 | #define HFI1_CAP_KCLEAR(cap) \ |
| 99 | ({ \ |
| 100 | hfi1_cap_mask &= ~HFI1_CAP_##cap; \ |
| 101 | hfi1_cap_mask; \ |
| 102 | }) |
| 103 | #define HFI1_CAP_USET(cap) \ |
| 104 | ({ \ |
| 105 | hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \ |
| 106 | hfi1_cap_mask; \ |
| 107 | }) |
| 108 | #define HFI1_CAP_UCLEAR(cap) \ |
| 109 | ({ \ |
| 110 | hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \ |
| 111 | hfi1_cap_mask; \ |
| 112 | }) |
| 113 | #define HFI1_CAP_SET(cap) \ |
| 114 | ({ \ |
| 115 | hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap << \ |
| 116 | HFI1_CAP_USER_SHIFT)); \ |
| 117 | hfi1_cap_mask; \ |
| 118 | }) |
| 119 | #define HFI1_CAP_CLEAR(cap) \ |
| 120 | ({ \ |
| 121 | hfi1_cap_mask &= ~(HFI1_CAP_##cap | \ |
| 122 | (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \ |
| 123 | hfi1_cap_mask; \ |
| 124 | }) |
| 125 | #define HFI1_CAP_LOCK() \ |
| 126 | ({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; }) |
| 127 | #define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK)) |
| 128 | /* |
| 129 | * The set of capability bits that can be changed after initial load |
| 130 | * This set is the same for kernel and user contexts. However, for |
| 131 | * user contexts, the set can be further filtered by using the |
| 132 | * HFI1_CAP_RESERVED_MASK bits. |
| 133 | */ |
| 134 | #define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \ |
Mitko Haralanov | 3bd4dce | 2015-10-30 18:58:41 -0400 | [diff] [blame] | 135 | HFI1_CAP_HDRSUPP | \ |
| 136 | HFI1_CAP_MULTI_PKT_EGR | \ |
| 137 | HFI1_CAP_NODROP_RHQ_FULL | \ |
| 138 | HFI1_CAP_NODROP_EGR_FULL | \ |
| 139 | HFI1_CAP_ALLOW_PERM_JKEY | \ |
| 140 | HFI1_CAP_STATIC_RATE_CTRL | \ |
| 141 | HFI1_CAP_PRINT_UNIMPL | \ |
| 142 | HFI1_CAP_TID_UNMAP) |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 143 | /* |
| 144 | * A set of capability bits that are "global" and are not allowed to be |
| 145 | * set in the user bitmask. |
| 146 | */ |
| 147 | #define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA | \ |
| 148 | HFI1_CAP_USE_SDMA_HEAD | \ |
| 149 | HFI1_CAP_EXTENDED_PSN | \ |
| 150 | HFI1_CAP_PRINT_UNIMPL | \ |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 151 | HFI1_CAP_NO_INTEGRITY | \ |
| 152 | HFI1_CAP_PKEY_CHECK) << \ |
| 153 | HFI1_CAP_USER_SHIFT) |
| 154 | /* |
| 155 | * Set of capabilities that need to be enabled for kernel context in |
| 156 | * order to be allowed for user contexts, as well. |
| 157 | */ |
| 158 | #define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL) |
| 159 | /* Default enabled capabilities (both kernel and user) */ |
| 160 | #define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP | \ |
| 161 | HFI1_CAP_NODROP_RHQ_FULL | \ |
| 162 | HFI1_CAP_NODROP_EGR_FULL | \ |
| 163 | HFI1_CAP_SDMA | \ |
| 164 | HFI1_CAP_PRINT_UNIMPL | \ |
| 165 | HFI1_CAP_STATIC_RATE_CTRL | \ |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 166 | HFI1_CAP_PKEY_CHECK | \ |
| 167 | HFI1_CAP_MULTI_PKT_EGR | \ |
| 168 | HFI1_CAP_EXTENDED_PSN | \ |
| 169 | ((HFI1_CAP_HDRSUPP | \ |
| 170 | HFI1_CAP_MULTI_PKT_EGR | \ |
| 171 | HFI1_CAP_STATIC_RATE_CTRL | \ |
| 172 | HFI1_CAP_PKEY_CHECK | \ |
| 173 | HFI1_CAP_EARLY_CREDIT_RETURN) << \ |
| 174 | HFI1_CAP_USER_SHIFT)) |
| 175 | /* |
| 176 | * A bitmask of kernel/global capabilities that should be communicated |
| 177 | * to user level processes. |
| 178 | */ |
| 179 | #define HFI1_CAP_K2U (HFI1_CAP_SDMA | \ |
| 180 | HFI1_CAP_EXTENDED_PSN | \ |
| 181 | HFI1_CAP_PKEY_CHECK | \ |
| 182 | HFI1_CAP_NO_INTEGRITY) |
| 183 | |
| 184 | #define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << 16) | HFI1_USER_SWMINOR) |
| 185 | |
| 186 | #ifndef HFI1_KERN_TYPE |
| 187 | #define HFI1_KERN_TYPE 0 |
| 188 | #endif |
| 189 | |
| 190 | /* |
| 191 | * Similarly, this is the kernel version going back to the user. It's |
| 192 | * slightly different, in that we want to tell if the driver was built as |
| 193 | * part of a Intel release, or from the driver from openfabrics.org, |
| 194 | * kernel.org, or a standard distribution, for support reasons. |
| 195 | * The high bit is 0 for non-Intel and 1 for Intel-built/supplied. |
| 196 | * |
| 197 | * It's returned by the driver to the user code during initialization in the |
| 198 | * spi_sw_version field of hfi1_base_info, so the user code can in turn |
| 199 | * check for compatibility with the kernel. |
| 200 | */ |
| 201 | #define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION) |
| 202 | |
| 203 | /* |
| 204 | * Define the driver version number. This is something that refers only |
| 205 | * to the driver itself, not the software interfaces it supports. |
| 206 | */ |
| 207 | #ifndef HFI1_DRIVER_VERSION_BASE |
Jubin John | d4802974 | 2015-10-26 10:28:49 -0400 | [diff] [blame] | 208 | #define HFI1_DRIVER_VERSION_BASE "0.9-294" |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 209 | #endif |
| 210 | |
| 211 | /* create the final driver version string */ |
| 212 | #ifdef HFI1_IDSTR |
| 213 | #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR |
| 214 | #else |
| 215 | #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE |
| 216 | #endif |
| 217 | |
| 218 | /* |
| 219 | * Diagnostics can send a packet by writing the following |
| 220 | * struct to the diag packet special file. |
| 221 | * |
| 222 | * This allows a custom PBC qword, so that special modes and deliberate |
| 223 | * changes to CRCs can be used. |
| 224 | */ |
| 225 | #define _DIAG_PKT_VERS 1 |
| 226 | struct diag_pkt { |
| 227 | __u16 version; /* structure version */ |
| 228 | __u16 unit; /* which device */ |
| 229 | __u16 sw_index; /* send sw index to use */ |
| 230 | __u16 len; /* data length, in bytes */ |
| 231 | __u16 port; /* port number */ |
| 232 | __u16 unused; |
| 233 | __u32 flags; /* call flags */ |
| 234 | __u64 data; /* user data pointer */ |
| 235 | __u64 pbc; /* PBC for the packet */ |
| 236 | }; |
| 237 | |
| 238 | /* diag_pkt flags */ |
| 239 | #define F_DIAGPKT_WAIT 0x1 /* wait until packet is sent */ |
| 240 | |
| 241 | /* |
| 242 | * The next set of defines are for packet headers, and chip register |
| 243 | * and memory bits that are visible to and/or used by user-mode software. |
| 244 | */ |
| 245 | |
| 246 | /* |
| 247 | * Receive Header Flags |
| 248 | */ |
| 249 | #define RHF_PKT_LEN_SHIFT 0 |
| 250 | #define RHF_PKT_LEN_MASK 0xfffull |
| 251 | #define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT) |
| 252 | |
| 253 | #define RHF_RCV_TYPE_SHIFT 12 |
| 254 | #define RHF_RCV_TYPE_MASK 0x7ull |
| 255 | #define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT) |
| 256 | |
| 257 | #define RHF_USE_EGR_BFR_SHIFT 15 |
| 258 | #define RHF_USE_EGR_BFR_MASK 0x1ull |
| 259 | #define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT) |
| 260 | |
| 261 | #define RHF_EGR_INDEX_SHIFT 16 |
| 262 | #define RHF_EGR_INDEX_MASK 0x7ffull |
| 263 | #define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT) |
| 264 | |
| 265 | #define RHF_DC_INFO_SHIFT 27 |
| 266 | #define RHF_DC_INFO_MASK 0x1ull |
| 267 | #define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT) |
| 268 | |
| 269 | #define RHF_RCV_SEQ_SHIFT 28 |
| 270 | #define RHF_RCV_SEQ_MASK 0xfull |
| 271 | #define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT) |
| 272 | |
| 273 | #define RHF_EGR_OFFSET_SHIFT 32 |
| 274 | #define RHF_EGR_OFFSET_MASK 0xfffull |
| 275 | #define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT) |
| 276 | #define RHF_HDRQ_OFFSET_SHIFT 44 |
| 277 | #define RHF_HDRQ_OFFSET_MASK 0x1ffull |
| 278 | #define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT) |
| 279 | #define RHF_K_HDR_LEN_ERR (0x1ull << 53) |
| 280 | #define RHF_DC_UNC_ERR (0x1ull << 54) |
| 281 | #define RHF_DC_ERR (0x1ull << 55) |
| 282 | #define RHF_RCV_TYPE_ERR_SHIFT 56 |
| 283 | #define RHF_RCV_TYPE_ERR_MASK 0x7ul |
| 284 | #define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT) |
| 285 | #define RHF_TID_ERR (0x1ull << 59) |
| 286 | #define RHF_LEN_ERR (0x1ull << 60) |
| 287 | #define RHF_ECC_ERR (0x1ull << 61) |
| 288 | #define RHF_VCRC_ERR (0x1ull << 62) |
| 289 | #define RHF_ICRC_ERR (0x1ull << 63) |
| 290 | |
| 291 | #define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */ |
| 292 | |
| 293 | /* RHF receive types */ |
| 294 | #define RHF_RCV_TYPE_EXPECTED 0 |
| 295 | #define RHF_RCV_TYPE_EAGER 1 |
| 296 | #define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */ |
| 297 | #define RHF_RCV_TYPE_ERROR 3 |
| 298 | #define RHF_RCV_TYPE_BYPASS 4 |
| 299 | #define RHF_RCV_TYPE_INVALID5 5 |
| 300 | #define RHF_RCV_TYPE_INVALID6 6 |
| 301 | #define RHF_RCV_TYPE_INVALID7 7 |
| 302 | |
| 303 | /* RHF receive type error - expected packet errors */ |
| 304 | #define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2 |
| 305 | #define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4 |
| 306 | |
| 307 | /* RHF receive type error - eager packet errors */ |
| 308 | #define RHF_RTE_EAGER_NO_ERR 0x0 |
| 309 | |
| 310 | /* RHF receive type error - IB packet errors */ |
| 311 | #define RHF_RTE_IB_NO_ERR 0x0 |
| 312 | |
| 313 | /* RHF receive type error - error packet errors */ |
| 314 | #define RHF_RTE_ERROR_NO_ERR 0x0 |
| 315 | #define RHF_RTE_ERROR_OP_CODE_ERR 0x1 |
| 316 | #define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2 |
| 317 | #define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3 |
| 318 | #define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4 |
| 319 | #define RHF_RTE_ERROR_CONTEXT_ERR 0x5 |
| 320 | #define RHF_RTE_ERROR_KHDR_TID_ERR 0x6 |
| 321 | |
| 322 | /* RHF receive type error - bypass packet errors */ |
| 323 | #define RHF_RTE_BYPASS_NO_ERR 0x0 |
| 324 | |
| 325 | /* |
| 326 | * This structure contains the first field common to all protocols |
| 327 | * that employ this chip. |
| 328 | */ |
| 329 | struct hfi1_message_header { |
| 330 | __be16 lrh[4]; |
| 331 | }; |
| 332 | |
| 333 | /* IB - LRH header constants */ |
| 334 | #define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */ |
| 335 | #define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */ |
| 336 | |
| 337 | /* misc. */ |
| 338 | #define SIZE_OF_CRC 1 |
| 339 | |
| 340 | #define LIM_MGMT_P_KEY 0x7FFF |
| 341 | #define FULL_MGMT_P_KEY 0xFFFF |
| 342 | |
| 343 | #define DEFAULT_P_KEY LIM_MGMT_P_KEY |
| 344 | #define HFI1_PERMISSIVE_LID 0xFFFF |
| 345 | #define HFI1_AETH_CREDIT_SHIFT 24 |
| 346 | #define HFI1_AETH_CREDIT_MASK 0x1F |
| 347 | #define HFI1_AETH_CREDIT_INVAL 0x1F |
| 348 | #define HFI1_MSN_MASK 0xFFFFFF |
| 349 | #define HFI1_QPN_MASK 0xFFFFFF |
| 350 | #define HFI1_FECN_SHIFT 31 |
| 351 | #define HFI1_FECN_MASK 1 |
jubin.john@intel.com | 349ac71 | 2016-01-11 18:30:52 -0500 | [diff] [blame] | 352 | #define HFI1_FECN_SMASK BIT(HFI1_FECN_SHIFT) |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 353 | #define HFI1_BECN_SHIFT 30 |
| 354 | #define HFI1_BECN_MASK 1 |
jubin.john@intel.com | 349ac71 | 2016-01-11 18:30:52 -0500 | [diff] [blame] | 355 | #define HFI1_BECN_SMASK BIT(HFI1_BECN_SHIFT) |
Mike Marciniszyn | 7724105 | 2015-07-30 15:17:43 -0400 | [diff] [blame] | 356 | #define HFI1_MULTICAST_LID_BASE 0xC000 |
| 357 | |
| 358 | static inline __u64 rhf_to_cpu(const __le32 *rbuf) |
| 359 | { |
| 360 | return __le64_to_cpu(*((__le64 *)rbuf)); |
| 361 | } |
| 362 | |
| 363 | static inline u64 rhf_err_flags(u64 rhf) |
| 364 | { |
| 365 | return rhf & RHF_ERROR_SMASK; |
| 366 | } |
| 367 | |
| 368 | static inline u32 rhf_rcv_type(u64 rhf) |
| 369 | { |
| 370 | return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK; |
| 371 | } |
| 372 | |
| 373 | static inline u32 rhf_rcv_type_err(u64 rhf) |
| 374 | { |
| 375 | return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK; |
| 376 | } |
| 377 | |
| 378 | /* return size is in bytes, not DWORDs */ |
| 379 | static inline u32 rhf_pkt_len(u64 rhf) |
| 380 | { |
| 381 | return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2; |
| 382 | } |
| 383 | |
| 384 | static inline u32 rhf_egr_index(u64 rhf) |
| 385 | { |
| 386 | return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK; |
| 387 | } |
| 388 | |
| 389 | static inline u32 rhf_rcv_seq(u64 rhf) |
| 390 | { |
| 391 | return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK; |
| 392 | } |
| 393 | |
| 394 | /* returned offset is in DWORDS */ |
| 395 | static inline u32 rhf_hdrq_offset(u64 rhf) |
| 396 | { |
| 397 | return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK; |
| 398 | } |
| 399 | |
| 400 | static inline u64 rhf_use_egr_bfr(u64 rhf) |
| 401 | { |
| 402 | return rhf & RHF_USE_EGR_BFR_SMASK; |
| 403 | } |
| 404 | |
| 405 | static inline u64 rhf_dc_info(u64 rhf) |
| 406 | { |
| 407 | return rhf & RHF_DC_INFO_SMASK; |
| 408 | } |
| 409 | |
| 410 | static inline u32 rhf_egr_buf_offset(u64 rhf) |
| 411 | { |
| 412 | return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK; |
| 413 | } |
| 414 | #endif /* _COMMON_H */ |