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Anatolij Gustschin230f7ed2010-09-28 20:55:21 +02001/* Copyright (C) 2005-2010 Freescale Semiconductor, Inc.
Randy Vinson80cb9ae2006-01-20 13:53:38 -08002 * Copyright (c) 2005 MontaVista Software
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18#ifndef _EHCI_FSL_H
19#define _EHCI_FSL_H
20
21/* offsets for the non-ehci registers in the FSL SOC USB controller */
Anatolij Gustschin761bbcb2012-01-24 22:17:38 +010022#define FSL_SOC_USB_SBUSCFG 0x90
23#define SBUSCFG_INCR8 0x02 /* INCR8, specified */
Randy Vinson80cb9ae2006-01-20 13:53:38 -080024#define FSL_SOC_USB_ULPIVP 0x170
25#define FSL_SOC_USB_PORTSC1 0x184
26#define PORT_PTS_MSK (3<<30)
27#define PORT_PTS_UTMI (0<<30)
28#define PORT_PTS_ULPI (2<<30)
29#define PORT_PTS_SERIAL (3<<30)
30#define PORT_PTS_PTW (1<<28)
31#define FSL_SOC_USB_PORTSC2 0x188
Anatolij Gustschin13b7ee2a2011-04-18 22:01:55 +020032#define FSL_SOC_USB_USBMODE 0x1a8
33#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
34#define USBMODE_CM_HOST (3 << 0) /* controller mode: host */
35#define USBMODE_ES (1 << 2) /* (Big) Endian Select */
Anatolij Gustschin230f7ed2010-09-28 20:55:21 +020036
37#define FSL_SOC_USB_USBGENCTRL 0x200
38#define USBGENCTRL_PPP (1 << 3)
39#define USBGENCTRL_PFP (1 << 2)
40#define FSL_SOC_USB_ISIPHYCTRL 0x204
41#define ISIPHYCTRL_PXE (1)
42#define ISIPHYCTRL_PHYE (1 << 4)
43
Randy Vinson80cb9ae2006-01-20 13:53:38 -080044#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
45#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
46#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
Christian Engelmayer7378c572007-03-12 09:08:36 +010047#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
48#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
Randy Vinson80cb9ae2006-01-20 13:53:38 -080049#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
Shengzhou Liu28c56ea2012-02-16 18:02:20 +080050#define CTRL_UTMI_PHY_EN (1<<9)
Shengzhou Liu529febe2012-02-02 11:23:14 +080051#define CTRL_PHY_CLK_VALID (1 << 17)
Li Yang40acc092007-05-23 13:58:17 -070052#define SNOOP_SIZE_2GB 0x1e
Randy Vinson80cb9ae2006-01-20 13:53:38 -080053#endif /* _EHCI_FSL_H */