Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ahci.c - AHCI SATA support |
| 3 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 8 | * Copyright 2004-2005 Red Hat, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; see the file COPYING. If not, write to |
| 23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | * |
| 25 | * |
| 26 | * libata documentation is available via 'make {ps|pdf}docs', |
| 27 | * as Documentation/DocBook/libata.* |
| 28 | * |
| 29 | * AHCI hardware documentation: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/blkdev.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/interrupt.h> |
domen@coderock.org | 87507cf | 2005-04-08 09:53:06 +0200 | [diff] [blame] | 42 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 43 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 45 | #include <scsi/scsi_cmnd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #include <linux/libata.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | |
| 48 | #define DRV_NAME "ahci" |
Jeff Garzik | 8bc3fc4 | 2007-05-21 20:26:38 -0400 | [diff] [blame] | 49 | #define DRV_VERSION "2.2" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | |
| 51 | |
| 52 | enum { |
| 53 | AHCI_PCI_BAR = 5, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 54 | AHCI_MAX_PORTS = 32, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
| 56 | AHCI_DMA_BOUNDARY = 0xffffffff, |
Jens Axboe | be5d821 | 2007-05-22 09:45:39 +0200 | [diff] [blame] | 57 | AHCI_USE_CLUSTERING = 1, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 58 | AHCI_MAX_CMDS = 32, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 59 | AHCI_CMD_SZ = 32, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 60 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | AHCI_RX_FIS_SZ = 256, |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 62 | AHCI_CMD_TBL_CDB = 0x40, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 63 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
| 64 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
| 65 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
| 66 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | AHCI_RX_FIS_SZ, |
| 68 | AHCI_IRQ_ON_SG = (1 << 31), |
| 69 | AHCI_CMD_ATAPI = (1 << 5), |
| 70 | AHCI_CMD_WRITE = (1 << 6), |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 71 | AHCI_CMD_PREFETCH = (1 << 7), |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 72 | AHCI_CMD_RESET = (1 << 8), |
| 73 | AHCI_CMD_CLR_BUSY = (1 << 10), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
| 75 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 76 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | |
| 79 | board_ahci = 0, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 80 | board_ahci_pi = 1, |
| 81 | board_ahci_vt8251 = 2, |
| 82 | board_ahci_ign_iferr = 3, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 83 | board_ahci_sb600 = 4, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 84 | |
| 85 | /* global controller registers */ |
| 86 | HOST_CAP = 0x00, /* host capabilities */ |
| 87 | HOST_CTL = 0x04, /* global host control */ |
| 88 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
| 89 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
| 90 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
| 91 | |
| 92 | /* HOST_CTL bits */ |
| 93 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
| 94 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
| 95 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
| 96 | |
| 97 | /* HOST_CAP bits */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 98 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 99 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 100 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
Tejun Heo | 979db80 | 2006-05-15 21:03:52 +0900 | [diff] [blame] | 101 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 102 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
| 104 | /* registers for each SATA port */ |
| 105 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
| 106 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
| 107 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
| 108 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
| 109 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
| 110 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
| 111 | PORT_CMD = 0x18, /* port command */ |
| 112 | PORT_TFDATA = 0x20, /* taskfile data */ |
| 113 | PORT_SIG = 0x24, /* device TF signature */ |
| 114 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
| 115 | PORT_SCR = 0x28, /* SATA phy register block */ |
| 116 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
| 117 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
| 118 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
| 119 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
| 120 | |
| 121 | /* PORT_IRQ_{STAT,MASK} bits */ |
| 122 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
| 123 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
| 124 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
| 125 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
| 126 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
| 127 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
| 128 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
| 129 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
| 130 | |
| 131 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
| 132 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
| 133 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
| 134 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
| 135 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
| 136 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
| 137 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
| 138 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
| 139 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
| 140 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 141 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
| 142 | PORT_IRQ_IF_ERR | |
| 143 | PORT_IRQ_CONNECT | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 144 | PORT_IRQ_PHYRDY | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 145 | PORT_IRQ_UNK_FIS, |
| 146 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
| 147 | PORT_IRQ_TF_ERR | |
| 148 | PORT_IRQ_HBUS_DATA_ERR, |
| 149 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
| 150 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
| 151 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | |
| 153 | /* PORT_CMD bits */ |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 154 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
| 156 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
| 157 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 158 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
| 160 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
| 161 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
| 162 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 163 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
| 165 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
| 166 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 167 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 168 | /* ap->flags bits */ |
Tejun Heo | 4aeb0e3 | 2006-11-01 17:58:33 +0900 | [diff] [blame] | 169 | AHCI_FLAG_NO_NCQ = (1 << 24), |
| 170 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 171 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 172 | AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */ |
Tejun Heo | c7a4215 | 2007-05-18 16:23:19 +0200 | [diff] [blame] | 173 | AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */ |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 174 | |
| 175 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 176 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
Tejun Heo | 3cadbcc | 2007-05-15 03:28:15 +0900 | [diff] [blame] | 177 | ATA_FLAG_SKIP_D2H_BSY | |
| 178 | ATA_FLAG_ACPI_SATA, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | }; |
| 180 | |
| 181 | struct ahci_cmd_hdr { |
| 182 | u32 opts; |
| 183 | u32 status; |
| 184 | u32 tbl_addr; |
| 185 | u32 tbl_addr_hi; |
| 186 | u32 reserved[4]; |
| 187 | }; |
| 188 | |
| 189 | struct ahci_sg { |
| 190 | u32 addr; |
| 191 | u32 addr_hi; |
| 192 | u32 reserved; |
| 193 | u32 flags_size; |
| 194 | }; |
| 195 | |
| 196 | struct ahci_host_priv { |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 197 | u32 cap; /* cap to use */ |
| 198 | u32 port_map; /* port map to use */ |
| 199 | u32 saved_cap; /* saved initial cap */ |
| 200 | u32 saved_port_map; /* saved initial port_map */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 201 | }; |
| 202 | |
| 203 | struct ahci_port_priv { |
| 204 | struct ahci_cmd_hdr *cmd_slot; |
| 205 | dma_addr_t cmd_slot_dma; |
| 206 | void *cmd_tbl; |
| 207 | dma_addr_t cmd_tbl_dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | void *rx_fis; |
| 209 | dma_addr_t rx_fis_dma; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 210 | /* for NCQ spurious interrupt analysis */ |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 211 | unsigned int ncq_saw_d2h:1; |
| 212 | unsigned int ncq_saw_dmas:1; |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 213 | unsigned int ncq_saw_sdb:1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | }; |
| 215 | |
| 216 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); |
| 217 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); |
| 218 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 219 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | static void ahci_irq_clear(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | static int ahci_port_start(struct ata_port *ap); |
| 222 | static void ahci_port_stop(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
| 224 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
| 225 | static u8 ahci_check_status(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 226 | static void ahci_freeze(struct ata_port *ap); |
| 227 | static void ahci_thaw(struct ata_port *ap); |
| 228 | static void ahci_error_handler(struct ata_port *ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 229 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 230 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 231 | static int ahci_port_resume(struct ata_port *ap); |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 232 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl); |
| 233 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 234 | u32 opts); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 235 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 236 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 237 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
| 238 | static int ahci_pci_device_resume(struct pci_dev *pdev); |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 239 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 241 | static struct scsi_host_template ahci_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | .module = THIS_MODULE, |
| 243 | .name = DRV_NAME, |
| 244 | .ioctl = ata_scsi_ioctl, |
| 245 | .queuecommand = ata_scsi_queuecmd, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 246 | .change_queue_depth = ata_scsi_change_queue_depth, |
| 247 | .can_queue = AHCI_MAX_CMDS - 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | .this_id = ATA_SHT_THIS_ID, |
| 249 | .sg_tablesize = AHCI_MAX_SG, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 251 | .emulated = ATA_SHT_EMULATED, |
| 252 | .use_clustering = AHCI_USE_CLUSTERING, |
| 253 | .proc_name = DRV_NAME, |
| 254 | .dma_boundary = AHCI_DMA_BOUNDARY, |
| 255 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 256 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | .bios_param = ata_std_bios_param, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | }; |
| 259 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 260 | static const struct ata_port_operations ahci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | .port_disable = ata_port_disable, |
| 262 | |
| 263 | .check_status = ahci_check_status, |
| 264 | .check_altstatus = ahci_check_status, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | .dev_select = ata_noop_dev_select, |
| 266 | |
| 267 | .tf_read = ahci_tf_read, |
| 268 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 269 | .qc_prep = ahci_qc_prep, |
| 270 | .qc_issue = ahci_qc_issue, |
| 271 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | .irq_clear = ahci_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 273 | .irq_on = ata_dummy_irq_on, |
| 274 | .irq_ack = ata_dummy_irq_ack, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 275 | |
| 276 | .scr_read = ahci_scr_read, |
| 277 | .scr_write = ahci_scr_write, |
| 278 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 279 | .freeze = ahci_freeze, |
| 280 | .thaw = ahci_thaw, |
| 281 | |
| 282 | .error_handler = ahci_error_handler, |
| 283 | .post_internal_cmd = ahci_post_internal_cmd, |
| 284 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 285 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 286 | .port_suspend = ahci_port_suspend, |
| 287 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 288 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 289 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | .port_start = ahci_port_start, |
| 291 | .port_stop = ahci_port_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 292 | }; |
| 293 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 294 | static const struct ata_port_operations ahci_vt8251_ops = { |
| 295 | .port_disable = ata_port_disable, |
| 296 | |
| 297 | .check_status = ahci_check_status, |
| 298 | .check_altstatus = ahci_check_status, |
| 299 | .dev_select = ata_noop_dev_select, |
| 300 | |
| 301 | .tf_read = ahci_tf_read, |
| 302 | |
| 303 | .qc_prep = ahci_qc_prep, |
| 304 | .qc_issue = ahci_qc_issue, |
| 305 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 306 | .irq_clear = ahci_irq_clear, |
Akira Iguchi | 246ce3b | 2007-01-26 16:27:58 +0900 | [diff] [blame] | 307 | .irq_on = ata_dummy_irq_on, |
| 308 | .irq_ack = ata_dummy_irq_ack, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 309 | |
| 310 | .scr_read = ahci_scr_read, |
| 311 | .scr_write = ahci_scr_write, |
| 312 | |
| 313 | .freeze = ahci_freeze, |
| 314 | .thaw = ahci_thaw, |
| 315 | |
| 316 | .error_handler = ahci_vt8251_error_handler, |
| 317 | .post_internal_cmd = ahci_post_internal_cmd, |
| 318 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 319 | #ifdef CONFIG_PM |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 320 | .port_suspend = ahci_port_suspend, |
| 321 | .port_resume = ahci_port_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 322 | #endif |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 323 | |
| 324 | .port_start = ahci_port_start, |
| 325 | .port_stop = ahci_port_stop, |
| 326 | }; |
| 327 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 328 | static const struct ata_port_info ahci_port_info[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 329 | /* board_ahci */ |
| 330 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 331 | .flags = AHCI_FLAG_COMMON, |
Brett Russ | 7da7931 | 2005-09-01 21:53:34 -0400 | [diff] [blame] | 332 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame^] | 333 | .udma_mask = ATA_UDMA6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | .port_ops = &ahci_ops, |
| 335 | }, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 336 | /* board_ahci_pi */ |
| 337 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 338 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 339 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame^] | 340 | .udma_mask = ATA_UDMA6, |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 341 | .port_ops = &ahci_ops, |
| 342 | }, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 343 | /* board_ahci_vt8251 */ |
| 344 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 345 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME | |
| 346 | AHCI_FLAG_NO_NCQ, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 347 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame^] | 348 | .udma_mask = ATA_UDMA6, |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 349 | .port_ops = &ahci_vt8251_ops, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 350 | }, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 351 | /* board_ahci_ign_iferr */ |
| 352 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 353 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 354 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame^] | 355 | .udma_mask = ATA_UDMA6, |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 356 | .port_ops = &ahci_ops, |
| 357 | }, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 358 | /* board_ahci_sb600 */ |
| 359 | { |
Tejun Heo | 1188c0d | 2007-04-23 02:41:05 +0900 | [diff] [blame] | 360 | .flags = AHCI_FLAG_COMMON | |
Tejun Heo | c7a4215 | 2007-05-18 16:23:19 +0200 | [diff] [blame] | 361 | AHCI_FLAG_IGN_SERR_INTERNAL | |
| 362 | AHCI_FLAG_32BIT_ONLY, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 363 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 469248a | 2007-07-08 01:13:16 -0400 | [diff] [blame^] | 364 | .udma_mask = ATA_UDMA6, |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 365 | .port_ops = &ahci_ops, |
| 366 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | }; |
| 368 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 369 | static const struct pci_device_id ahci_pci_tbl[] = { |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 370 | /* Intel */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 371 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
| 372 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ |
| 373 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ |
| 374 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ |
| 375 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ |
Tejun Heo | 82490c0 | 2007-01-23 15:13:39 +0900 | [diff] [blame] | 376 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 377 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
| 378 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ |
| 379 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ |
| 380 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 381 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */ |
| 382 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */ |
| 383 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */ |
| 384 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */ |
| 385 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */ |
| 386 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */ |
| 387 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */ |
| 388 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */ |
| 389 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */ |
| 390 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */ |
| 391 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */ |
| 392 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */ |
| 393 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */ |
Jason Gaston | 8af12cd | 2007-03-02 17:39:46 -0800 | [diff] [blame] | 394 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */ |
Tejun Heo | 648a88b | 2006-11-09 15:08:40 +0900 | [diff] [blame] | 395 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */ |
| 396 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */ |
| 397 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 398 | |
Tejun Heo | e34bb37 | 2007-02-26 20:24:03 +0900 | [diff] [blame] | 399 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
| 400 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 401 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 402 | |
| 403 | /* ATI */ |
Conke Hu | c65ec1c | 2007-04-11 18:23:14 +0800 | [diff] [blame] | 404 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
Henry Su | 2bcfdde | 2007-05-10 22:48:51 -0700 | [diff] [blame] | 405 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 406 | |
| 407 | /* VIA */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 408 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
Tejun Heo | bf33554 | 2007-04-11 17:27:14 +0900 | [diff] [blame] | 409 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 410 | |
| 411 | /* NVIDIA */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 412 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
| 413 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ |
| 414 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ |
| 415 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ |
Peer Chen | 6fbf5ba | 2006-12-20 14:18:00 -0500 | [diff] [blame] | 416 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
| 417 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ |
| 418 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ |
| 419 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ |
| 420 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ |
| 421 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ |
| 422 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ |
| 423 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ |
Peer Chen | 895663c | 2006-11-02 17:59:46 -0500 | [diff] [blame] | 424 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
| 425 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ |
| 426 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ |
| 427 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ |
| 428 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ |
| 429 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ |
| 430 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ |
| 431 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ |
Peer Chen | 0522b28 | 2007-06-07 18:05:12 +0800 | [diff] [blame] | 432 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */ |
| 433 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */ |
| 434 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */ |
| 435 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */ |
| 436 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */ |
| 437 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */ |
| 438 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */ |
| 439 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */ |
| 440 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */ |
| 441 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */ |
| 442 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */ |
| 443 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */ |
| 444 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */ |
| 445 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */ |
| 446 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */ |
| 447 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */ |
| 448 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */ |
| 449 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */ |
| 450 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */ |
| 451 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */ |
| 452 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */ |
| 453 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */ |
| 454 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */ |
| 455 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 456 | |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 457 | /* SiS */ |
Jeff Garzik | 54bb3a94 | 2006-09-27 22:20:11 -0400 | [diff] [blame] | 458 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
| 459 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ |
| 460 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ |
Jeff Garzik | 95916ed | 2006-07-29 04:10:14 -0400 | [diff] [blame] | 461 | |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 462 | /* Generic, PCI class code for AHCI */ |
| 463 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 464 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
Jeff Garzik | 415ae2b | 2006-11-01 05:10:42 -0500 | [diff] [blame] | 465 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | { } /* terminate list */ |
| 467 | }; |
| 468 | |
| 469 | |
| 470 | static struct pci_driver ahci_pci_driver = { |
| 471 | .name = DRV_NAME, |
| 472 | .id_table = ahci_pci_tbl, |
| 473 | .probe = ahci_init_one, |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 474 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 475 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 476 | .suspend = ahci_pci_device_suspend, |
| 477 | .resume = ahci_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 478 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | }; |
| 480 | |
| 481 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 482 | static inline int ahci_nr_ports(u32 cap) |
| 483 | { |
| 484 | return (cap & 0x1f) + 1; |
| 485 | } |
| 486 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 487 | static inline void __iomem *__ahci_port_base(struct ata_host *host, |
| 488 | unsigned int port_no) |
| 489 | { |
| 490 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 491 | |
| 492 | return mmio + 0x100 + (port_no * 0x80); |
| 493 | } |
| 494 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 495 | static inline void __iomem *ahci_port_base(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 496 | { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 497 | return __ahci_port_base(ap->host, ap->port_no); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 498 | } |
| 499 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 500 | /** |
| 501 | * ahci_save_initial_config - Save and fixup initial config values |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 502 | * @pdev: target PCI device |
| 503 | * @pi: associated ATA port info |
| 504 | * @hpriv: host private area to store config values |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 505 | * |
| 506 | * Some registers containing configuration info might be setup by |
| 507 | * BIOS and might be cleared on reset. This function saves the |
| 508 | * initial values of those registers into @hpriv such that they |
| 509 | * can be restored after controller reset. |
| 510 | * |
| 511 | * If inconsistent, config values are fixed up by this function. |
| 512 | * |
| 513 | * LOCKING: |
| 514 | * None. |
| 515 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 516 | static void ahci_save_initial_config(struct pci_dev *pdev, |
| 517 | const struct ata_port_info *pi, |
| 518 | struct ahci_host_priv *hpriv) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 519 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 520 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 521 | u32 cap, port_map; |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 522 | int i; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 523 | |
| 524 | /* Values prefixed with saved_ are written back to host after |
| 525 | * reset. Values without are used for driver operation. |
| 526 | */ |
| 527 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); |
| 528 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); |
| 529 | |
Tejun Heo | c7a4215 | 2007-05-18 16:23:19 +0200 | [diff] [blame] | 530 | /* some chips lie about 64bit support */ |
| 531 | if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) { |
| 532 | dev_printk(KERN_INFO, &pdev->dev, |
| 533 | "controller can't do 64bit DMA, forcing 32bit\n"); |
| 534 | cap &= ~HOST_CAP_64; |
| 535 | } |
| 536 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 537 | /* fixup zero port_map */ |
| 538 | if (!port_map) { |
Tejun Heo | a3d2cc5 | 2007-06-19 18:52:56 +0900 | [diff] [blame] | 539 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 540 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 541 | "PORTS_IMPL is zero, forcing 0x%x\n", port_map); |
| 542 | |
| 543 | /* write the fixed up value to the PI register */ |
| 544 | hpriv->saved_port_map = port_map; |
| 545 | } |
| 546 | |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 547 | /* cross check port_map and cap.n_ports */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 548 | if (pi->flags & AHCI_FLAG_HONOR_PI) { |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 549 | u32 tmp_port_map = port_map; |
| 550 | int n_ports = ahci_nr_ports(cap); |
| 551 | |
| 552 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { |
| 553 | if (tmp_port_map & (1 << i)) { |
| 554 | n_ports--; |
| 555 | tmp_port_map &= ~(1 << i); |
| 556 | } |
| 557 | } |
| 558 | |
| 559 | /* Whine if inconsistent. No need to update cap. |
| 560 | * port_map is used to determine number of ports. |
| 561 | */ |
| 562 | if (n_ports || tmp_port_map) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 563 | dev_printk(KERN_WARNING, &pdev->dev, |
Tejun Heo | 17199b1 | 2007-03-18 22:26:53 +0900 | [diff] [blame] | 564 | "nr_ports (%u) and implemented port map " |
| 565 | "(0x%x) don't match\n", |
| 566 | ahci_nr_ports(cap), port_map); |
| 567 | } else { |
| 568 | /* fabricate port_map from cap.nr_ports */ |
| 569 | port_map = (1 << ahci_nr_ports(cap)) - 1; |
| 570 | } |
| 571 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 572 | /* record values to use during operation */ |
| 573 | hpriv->cap = cap; |
| 574 | hpriv->port_map = port_map; |
| 575 | } |
| 576 | |
| 577 | /** |
| 578 | * ahci_restore_initial_config - Restore initial config |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 579 | * @host: target ATA host |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 580 | * |
| 581 | * Restore initial config stored by ahci_save_initial_config(). |
| 582 | * |
| 583 | * LOCKING: |
| 584 | * None. |
| 585 | */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 586 | static void ahci_restore_initial_config(struct ata_host *host) |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 587 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 588 | struct ahci_host_priv *hpriv = host->private_data; |
| 589 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 590 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 591 | writel(hpriv->saved_cap, mmio + HOST_CAP); |
| 592 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); |
| 593 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
| 594 | } |
| 595 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 596 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
| 597 | { |
| 598 | unsigned int sc_reg; |
| 599 | |
| 600 | switch (sc_reg_in) { |
| 601 | case SCR_STATUS: sc_reg = 0; break; |
| 602 | case SCR_CONTROL: sc_reg = 1; break; |
| 603 | case SCR_ERROR: sc_reg = 2; break; |
| 604 | case SCR_ACTIVE: sc_reg = 3; break; |
| 605 | default: |
| 606 | return 0xffffffffU; |
| 607 | } |
| 608 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 609 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 610 | } |
| 611 | |
| 612 | |
| 613 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, |
| 614 | u32 val) |
| 615 | { |
| 616 | unsigned int sc_reg; |
| 617 | |
| 618 | switch (sc_reg_in) { |
| 619 | case SCR_STATUS: sc_reg = 0; break; |
| 620 | case SCR_CONTROL: sc_reg = 1; break; |
| 621 | case SCR_ERROR: sc_reg = 2; break; |
| 622 | case SCR_ACTIVE: sc_reg = 3; break; |
| 623 | default: |
| 624 | return; |
| 625 | } |
| 626 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 627 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 628 | } |
| 629 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 630 | static void ahci_start_engine(struct ata_port *ap) |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 631 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 632 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 633 | u32 tmp; |
| 634 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 635 | /* start DMA */ |
Tejun Heo | 9f59205 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 636 | tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 637 | tmp |= PORT_CMD_START; |
| 638 | writel(tmp, port_mmio + PORT_CMD); |
| 639 | readl(port_mmio + PORT_CMD); /* flush */ |
| 640 | } |
| 641 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 642 | static int ahci_stop_engine(struct ata_port *ap) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 643 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 644 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 645 | u32 tmp; |
| 646 | |
| 647 | tmp = readl(port_mmio + PORT_CMD); |
| 648 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 649 | /* check if the HBA is idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 650 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
| 651 | return 0; |
| 652 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 653 | /* setting HBA to idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 654 | tmp &= ~PORT_CMD_START; |
| 655 | writel(tmp, port_mmio + PORT_CMD); |
| 656 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 657 | /* wait for engine to stop. This could be as long as 500 msec */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 658 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 659 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 660 | if (tmp & PORT_CMD_LIST_ON) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 661 | return -EIO; |
| 662 | |
| 663 | return 0; |
| 664 | } |
| 665 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 666 | static void ahci_start_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 667 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 668 | void __iomem *port_mmio = ahci_port_base(ap); |
| 669 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 670 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 671 | u32 tmp; |
| 672 | |
| 673 | /* set FIS registers */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 674 | if (hpriv->cap & HOST_CAP_64) |
| 675 | writel((pp->cmd_slot_dma >> 16) >> 16, |
| 676 | port_mmio + PORT_LST_ADDR_HI); |
| 677 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 678 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 679 | if (hpriv->cap & HOST_CAP_64) |
| 680 | writel((pp->rx_fis_dma >> 16) >> 16, |
| 681 | port_mmio + PORT_FIS_ADDR_HI); |
| 682 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 683 | |
| 684 | /* enable FIS reception */ |
| 685 | tmp = readl(port_mmio + PORT_CMD); |
| 686 | tmp |= PORT_CMD_FIS_RX; |
| 687 | writel(tmp, port_mmio + PORT_CMD); |
| 688 | |
| 689 | /* flush */ |
| 690 | readl(port_mmio + PORT_CMD); |
| 691 | } |
| 692 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 693 | static int ahci_stop_fis_rx(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 694 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 695 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 696 | u32 tmp; |
| 697 | |
| 698 | /* disable FIS reception */ |
| 699 | tmp = readl(port_mmio + PORT_CMD); |
| 700 | tmp &= ~PORT_CMD_FIS_RX; |
| 701 | writel(tmp, port_mmio + PORT_CMD); |
| 702 | |
| 703 | /* wait for completion, spec says 500ms, give it 1000 */ |
| 704 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, |
| 705 | PORT_CMD_FIS_ON, 10, 1000); |
| 706 | if (tmp & PORT_CMD_FIS_ON) |
| 707 | return -EBUSY; |
| 708 | |
| 709 | return 0; |
| 710 | } |
| 711 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 712 | static void ahci_power_up(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 713 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 714 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 715 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 716 | u32 cmd; |
| 717 | |
| 718 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
| 719 | |
| 720 | /* spin up device */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 721 | if (hpriv->cap & HOST_CAP_SSS) { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 722 | cmd |= PORT_CMD_SPIN_UP; |
| 723 | writel(cmd, port_mmio + PORT_CMD); |
| 724 | } |
| 725 | |
| 726 | /* wake up link */ |
| 727 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); |
| 728 | } |
| 729 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 730 | #ifdef CONFIG_PM |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 731 | static void ahci_power_down(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 732 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 733 | struct ahci_host_priv *hpriv = ap->host->private_data; |
| 734 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 735 | u32 cmd, scontrol; |
| 736 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 737 | if (!(hpriv->cap & HOST_CAP_SSS)) |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 738 | return; |
| 739 | |
| 740 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
| 741 | scontrol = readl(port_mmio + PORT_SCR_CTL); |
| 742 | scontrol &= ~0xf; |
| 743 | writel(scontrol, port_mmio + PORT_SCR_CTL); |
| 744 | |
| 745 | /* then set PxCMD.SUD to 0 */ |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 746 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
Tejun Heo | 07c53da | 2007-01-21 02:10:11 +0900 | [diff] [blame] | 747 | cmd &= ~PORT_CMD_SPIN_UP; |
| 748 | writel(cmd, port_mmio + PORT_CMD); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 749 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 750 | #endif |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 751 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 752 | static void ahci_start_port(struct ata_port *ap) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 753 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 754 | /* enable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 755 | ahci_start_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 756 | |
| 757 | /* enable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 758 | ahci_start_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 759 | } |
| 760 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 761 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 762 | { |
| 763 | int rc; |
| 764 | |
| 765 | /* disable DMA */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 766 | rc = ahci_stop_engine(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 767 | if (rc) { |
| 768 | *emsg = "failed to stop engine"; |
| 769 | return rc; |
| 770 | } |
| 771 | |
| 772 | /* disable FIS reception */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 773 | rc = ahci_stop_fis_rx(ap); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 774 | if (rc) { |
| 775 | *emsg = "failed stop FIS RX"; |
| 776 | return rc; |
| 777 | } |
| 778 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 779 | return 0; |
| 780 | } |
| 781 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 782 | static int ahci_reset_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 783 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 784 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 785 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 786 | u32 tmp; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 787 | |
| 788 | /* global controller reset */ |
| 789 | tmp = readl(mmio + HOST_CTL); |
| 790 | if ((tmp & HOST_RESET) == 0) { |
| 791 | writel(tmp | HOST_RESET, mmio + HOST_CTL); |
| 792 | readl(mmio + HOST_CTL); /* flush */ |
| 793 | } |
| 794 | |
| 795 | /* reset must complete within 1 second, or |
| 796 | * the hardware should be considered fried. |
| 797 | */ |
| 798 | ssleep(1); |
| 799 | |
| 800 | tmp = readl(mmio + HOST_CTL); |
| 801 | if (tmp & HOST_RESET) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 802 | dev_printk(KERN_ERR, host->dev, |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 803 | "controller reset failed (0x%x)\n", tmp); |
| 804 | return -EIO; |
| 805 | } |
| 806 | |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 807 | /* turn on AHCI mode */ |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 808 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
| 809 | (void) readl(mmio + HOST_CTL); /* flush */ |
Tejun Heo | 98fa4b6 | 2006-11-02 12:17:23 +0900 | [diff] [blame] | 810 | |
Tejun Heo | d447df1 | 2007-03-18 22:15:33 +0900 | [diff] [blame] | 811 | /* some registers might be cleared on reset. restore initial values */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 812 | ahci_restore_initial_config(host); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 813 | |
| 814 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
| 815 | u16 tmp16; |
| 816 | |
| 817 | /* configure PCS */ |
| 818 | pci_read_config_word(pdev, 0x92, &tmp16); |
| 819 | tmp16 |= 0xf; |
| 820 | pci_write_config_word(pdev, 0x92, tmp16); |
| 821 | } |
| 822 | |
| 823 | return 0; |
| 824 | } |
| 825 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 826 | static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap, |
| 827 | int port_no, void __iomem *mmio, |
| 828 | void __iomem *port_mmio) |
| 829 | { |
| 830 | const char *emsg = NULL; |
| 831 | int rc; |
| 832 | u32 tmp; |
| 833 | |
| 834 | /* make sure port is not active */ |
| 835 | rc = ahci_deinit_port(ap, &emsg); |
| 836 | if (rc) |
| 837 | dev_printk(KERN_WARNING, &pdev->dev, |
| 838 | "%s (%d)\n", emsg, rc); |
| 839 | |
| 840 | /* clear SError */ |
| 841 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 842 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); |
| 843 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 844 | |
| 845 | /* clear port IRQ */ |
| 846 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 847 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 848 | if (tmp) |
| 849 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 850 | |
| 851 | writel(1 << port_no, mmio + HOST_IRQ_STAT); |
| 852 | } |
| 853 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 854 | static void ahci_init_controller(struct ata_host *host) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 855 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 856 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 857 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 858 | int i; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 859 | u32 tmp; |
| 860 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 861 | for (i = 0; i < host->n_ports; i++) { |
| 862 | struct ata_port *ap = host->ports[i]; |
| 863 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 864 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 865 | if (ata_port_is_dummy(ap)) |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 866 | continue; |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 867 | |
Jeff Garzik | 2bcd866 | 2007-05-28 07:45:27 -0400 | [diff] [blame] | 868 | ahci_port_init(pdev, ap, i, mmio, port_mmio); |
Tejun Heo | d91542c | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 869 | } |
| 870 | |
| 871 | tmp = readl(mmio + HOST_CTL); |
| 872 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 873 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 874 | tmp = readl(mmio + HOST_CTL); |
| 875 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 876 | } |
| 877 | |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 878 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 879 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 880 | void __iomem *port_mmio = ahci_port_base(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 881 | struct ata_taskfile tf; |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 882 | u32 tmp; |
| 883 | |
| 884 | tmp = readl(port_mmio + PORT_SIG); |
| 885 | tf.lbah = (tmp >> 24) & 0xff; |
| 886 | tf.lbam = (tmp >> 16) & 0xff; |
| 887 | tf.lbal = (tmp >> 8) & 0xff; |
| 888 | tf.nsect = (tmp) & 0xff; |
| 889 | |
| 890 | return ata_dev_classify(&tf); |
| 891 | } |
| 892 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 893 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 894 | u32 opts) |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 895 | { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 896 | dma_addr_t cmd_tbl_dma; |
| 897 | |
| 898 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; |
| 899 | |
| 900 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); |
| 901 | pp->cmd_slot[tag].status = 0; |
| 902 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); |
| 903 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 904 | } |
| 905 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 906 | static int ahci_clo(struct ata_port *ap) |
| 907 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 908 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 909 | struct ahci_host_priv *hpriv = ap->host->private_data; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 910 | u32 tmp; |
| 911 | |
| 912 | if (!(hpriv->cap & HOST_CAP_CLO)) |
| 913 | return -EOPNOTSUPP; |
| 914 | |
| 915 | tmp = readl(port_mmio + PORT_CMD); |
| 916 | tmp |= PORT_CMD_CLO; |
| 917 | writel(tmp, port_mmio + PORT_CMD); |
| 918 | |
| 919 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 920 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); |
| 921 | if (tmp & PORT_CMD_CLO) |
| 922 | return -EIO; |
| 923 | |
| 924 | return 0; |
| 925 | } |
| 926 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 927 | static int ahci_softreset(struct ata_port *ap, unsigned int *class, |
| 928 | unsigned long deadline) |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 929 | { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 930 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 931 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 932 | const u32 cmd_fis_len = 5; /* five dwords */ |
| 933 | const char *reason = NULL; |
| 934 | struct ata_taskfile tf; |
Tejun Heo | 75fe180 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 935 | u32 tmp; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 936 | u8 *fis; |
| 937 | int rc; |
| 938 | |
| 939 | DPRINTK("ENTER\n"); |
| 940 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 941 | if (ata_port_offline(ap)) { |
Tejun Heo | c2a6585 | 2006-04-03 01:58:06 +0900 | [diff] [blame] | 942 | DPRINTK("PHY reports no device\n"); |
| 943 | *class = ATA_DEV_NONE; |
| 944 | return 0; |
| 945 | } |
| 946 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 947 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 948 | rc = ahci_stop_engine(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 949 | if (rc) { |
| 950 | reason = "failed to stop engine"; |
| 951 | goto fail_restart; |
| 952 | } |
| 953 | |
| 954 | /* check BUSY/DRQ, perform Command List Override if necessary */ |
Tejun Heo | 1244a19 | 2006-11-01 17:19:18 +0900 | [diff] [blame] | 955 | if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) { |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 956 | rc = ahci_clo(ap); |
| 957 | |
| 958 | if (rc == -EOPNOTSUPP) { |
| 959 | reason = "port busy but CLO unavailable"; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 960 | goto fail_restart; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 961 | } else if (rc) { |
| 962 | reason = "port busy but CLO failed"; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 963 | goto fail_restart; |
| 964 | } |
| 965 | } |
| 966 | |
| 967 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 968 | ahci_start_engine(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 969 | |
Tejun Heo | 3373efd | 2006-05-15 20:57:53 +0900 | [diff] [blame] | 970 | ata_tf_init(ap->device, &tf); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 971 | fis = pp->cmd_tbl; |
| 972 | |
| 973 | /* issue the first D2H Register FIS */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 974 | ahci_fill_cmd_slot(pp, 0, |
| 975 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 976 | |
| 977 | tf.ctl |= ATA_SRST; |
| 978 | ata_tf_to_fis(&tf, fis, 0); |
| 979 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ |
| 980 | |
| 981 | writel(1, port_mmio + PORT_CMD_ISSUE); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 982 | |
Tejun Heo | 75fe180 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 983 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
| 984 | if (tmp & 0x1) { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 985 | rc = -EIO; |
| 986 | reason = "1st FIS failed"; |
| 987 | goto fail; |
| 988 | } |
| 989 | |
| 990 | /* spec says at least 5us, but be generous and sleep for 1ms */ |
| 991 | msleep(1); |
| 992 | |
| 993 | /* issue the second D2H Register FIS */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 994 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 995 | |
| 996 | tf.ctl &= ~ATA_SRST; |
| 997 | ata_tf_to_fis(&tf, fis, 0); |
| 998 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ |
| 999 | |
| 1000 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 1001 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1002 | |
| 1003 | /* spec mandates ">= 2ms" before checking status. |
| 1004 | * We wait 150ms, because that was the magic delay used for |
| 1005 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time |
| 1006 | * between when the ATA command register is written, and then |
| 1007 | * status is checked. Because waiting for "a while" before |
| 1008 | * checking status is fine, post SRST, we perform this magic |
| 1009 | * delay here as well. |
| 1010 | */ |
| 1011 | msleep(150); |
| 1012 | |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1013 | rc = ata_wait_ready(ap, deadline); |
| 1014 | /* link occupied, -ENODEV too is an error */ |
| 1015 | if (rc) { |
| 1016 | reason = "device not ready"; |
| 1017 | goto fail; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1018 | } |
Tejun Heo | 9b89391 | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1019 | *class = ahci_dev_classify(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1020 | |
| 1021 | DPRINTK("EXIT, class=%u\n", *class); |
| 1022 | return 0; |
| 1023 | |
| 1024 | fail_restart: |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1025 | ahci_start_engine(ap); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1026 | fail: |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 1027 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 1028 | return rc; |
| 1029 | } |
| 1030 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1031 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class, |
| 1032 | unsigned long deadline) |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 1033 | { |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1034 | struct ahci_port_priv *pp = ap->private_data; |
| 1035 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1036 | struct ata_taskfile tf; |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1037 | int rc; |
| 1038 | |
| 1039 | DPRINTK("ENTER\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1040 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1041 | ahci_stop_engine(ap); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1042 | |
| 1043 | /* clear D2H reception area to properly wait for D2H FIS */ |
| 1044 | ata_tf_init(ap->device, &tf); |
Tejun Heo | dfd7a3d | 2007-01-26 15:37:20 +0900 | [diff] [blame] | 1045 | tf.command = 0x80; |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1046 | ata_tf_to_fis(&tf, d2h_fis, 0); |
| 1047 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1048 | rc = sata_std_hardreset(ap, class, deadline); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1049 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1050 | ahci_start_engine(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1051 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 1052 | if (rc == 0 && ata_port_online(ap)) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1053 | *class = ahci_dev_classify(ap); |
| 1054 | if (*class == ATA_DEV_UNKNOWN) |
| 1055 | *class = ATA_DEV_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1056 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1057 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1058 | return rc; |
| 1059 | } |
| 1060 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1061 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class, |
| 1062 | unsigned long deadline) |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1063 | { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1064 | int rc; |
| 1065 | |
| 1066 | DPRINTK("ENTER\n"); |
| 1067 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1068 | ahci_stop_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1069 | |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 1070 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context), |
| 1071 | deadline); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1072 | |
| 1073 | /* vt8251 needs SError cleared for the port to operate */ |
| 1074 | ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); |
| 1075 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1076 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1077 | |
| 1078 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 1079 | |
| 1080 | /* vt8251 doesn't clear BSY on signature FIS reception, |
| 1081 | * request follow-up softreset. |
| 1082 | */ |
| 1083 | return rc ?: -EAGAIN; |
| 1084 | } |
| 1085 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1086 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
| 1087 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1088 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1089 | u32 new_tmp, tmp; |
| 1090 | |
| 1091 | ata_std_postreset(ap, class); |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1092 | |
| 1093 | /* Make sure port's ATAPI bit is set appropriately */ |
| 1094 | new_tmp = tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 1095 | if (*class == ATA_DEV_ATAPI) |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 1096 | new_tmp |= PORT_CMD_ATAPI; |
| 1097 | else |
| 1098 | new_tmp &= ~PORT_CMD_ATAPI; |
| 1099 | if (new_tmp != tmp) { |
| 1100 | writel(new_tmp, port_mmio + PORT_CMD); |
| 1101 | readl(port_mmio + PORT_CMD); /* flush */ |
| 1102 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1103 | } |
| 1104 | |
| 1105 | static u8 ahci_check_status(struct ata_port *ap) |
| 1106 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1107 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1108 | |
| 1109 | return readl(mmio + PORT_TFDATA) & 0xFF; |
| 1110 | } |
| 1111 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1112 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| 1113 | { |
| 1114 | struct ahci_port_priv *pp = ap->private_data; |
| 1115 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 1116 | |
| 1117 | ata_tf_from_fis(d2h_fis, tf); |
| 1118 | } |
| 1119 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1120 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1121 | { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1122 | struct scatterlist *sg; |
| 1123 | struct ahci_sg *ahci_sg; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1124 | unsigned int n_sg = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1125 | |
| 1126 | VPRINTK("ENTER\n"); |
| 1127 | |
| 1128 | /* |
| 1129 | * Next, the S/G list. |
| 1130 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1131 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1132 | ata_for_each_sg(sg, qc) { |
| 1133 | dma_addr_t addr = sg_dma_address(sg); |
| 1134 | u32 sg_len = sg_dma_len(sg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1135 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1136 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 1137 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 1138 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1139 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 1140 | ahci_sg++; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1141 | n_sg++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1142 | } |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1143 | |
| 1144 | return n_sg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1145 | } |
| 1146 | |
| 1147 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
| 1148 | { |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1149 | struct ata_port *ap = qc->ap; |
| 1150 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1151 | int is_atapi = is_atapi_taskfile(&qc->tf); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1152 | void *cmd_tbl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1153 | u32 opts; |
| 1154 | const u32 cmd_fis_len = 5; /* five dwords */ |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1155 | unsigned int n_elem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1156 | |
| 1157 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1158 | * Fill in command table information. First, the header, |
| 1159 | * a SATA Register - Host to Device command FIS. |
| 1160 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1161 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
| 1162 | |
| 1163 | ata_tf_to_fis(&qc->tf, cmd_tbl, 0); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1164 | if (is_atapi) { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1165 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
| 1166 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 1167 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1168 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1169 | n_elem = 0; |
| 1170 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1171 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1172 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 1173 | /* |
| 1174 | * Fill in command slot information. |
| 1175 | */ |
| 1176 | opts = cmd_fis_len | n_elem << 16; |
| 1177 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
| 1178 | opts |= AHCI_CMD_WRITE; |
| 1179 | if (is_atapi) |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 1180 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 1181 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1182 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1183 | } |
| 1184 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1185 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1186 | { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1187 | struct ahci_port_priv *pp = ap->private_data; |
| 1188 | struct ata_eh_info *ehi = &ap->eh_info; |
| 1189 | unsigned int err_mask = 0, action = 0; |
| 1190 | struct ata_queued_cmd *qc; |
| 1191 | u32 serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1192 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1193 | ata_ehi_clear_desc(ehi); |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 1194 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1195 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
| 1196 | serror = ahci_scr_read(ap, SCR_ERROR); |
| 1197 | ahci_scr_write(ap, SCR_ERROR, serror); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1198 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1199 | /* analyze @irq_stat */ |
| 1200 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1201 | |
Tejun Heo | 4166955 | 2006-11-29 11:33:14 +0900 | [diff] [blame] | 1202 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
| 1203 | if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR) |
| 1204 | irq_stat &= ~PORT_IRQ_IF_ERR; |
| 1205 | |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 1206 | if (irq_stat & PORT_IRQ_TF_ERR) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1207 | err_mask |= AC_ERR_DEV; |
Conke Hu | 55a6160 | 2007-03-27 18:33:05 +0800 | [diff] [blame] | 1208 | if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL) |
| 1209 | serror &= ~SERR_INTERNAL; |
| 1210 | } |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1211 | |
| 1212 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { |
| 1213 | err_mask |= AC_ERR_HOST_BUS; |
| 1214 | action |= ATA_EH_SOFTRESET; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1215 | } |
| 1216 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1217 | if (irq_stat & PORT_IRQ_IF_ERR) { |
| 1218 | err_mask |= AC_ERR_ATA_BUS; |
| 1219 | action |= ATA_EH_SOFTRESET; |
| 1220 | ata_ehi_push_desc(ehi, ", interface fatal error"); |
| 1221 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1222 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1223 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 1224 | ata_ehi_hotplugged(ehi); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1225 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
| 1226 | "connection status changed" : "PHY RDY changed"); |
| 1227 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1228 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1229 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
| 1230 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1231 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1232 | err_mask |= AC_ERR_HSM; |
| 1233 | action |= ATA_EH_SOFTRESET; |
| 1234 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", |
| 1235 | unk[0], unk[1], unk[2], unk[3]); |
| 1236 | } |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 1237 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1238 | /* okay, let's hand over to EH */ |
| 1239 | ehi->serror |= serror; |
| 1240 | ehi->action |= action; |
| 1241 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1242 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1243 | if (qc) |
| 1244 | qc->err_mask |= err_mask; |
| 1245 | else |
| 1246 | ehi->err_mask |= err_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1247 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1248 | if (irq_stat & PORT_IRQ_FREEZE) |
| 1249 | ata_port_freeze(ap); |
| 1250 | else |
| 1251 | ata_port_abort(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1252 | } |
| 1253 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1254 | static void ahci_port_intr(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1255 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1256 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1257 | struct ata_eh_info *ehi = &ap->eh_info; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1258 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1259 | u32 status, qc_active; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1260 | int rc, known_irq = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1261 | |
| 1262 | status = readl(port_mmio + PORT_IRQ_STAT); |
| 1263 | writel(status, port_mmio + PORT_IRQ_STAT); |
| 1264 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1265 | if (unlikely(status & PORT_IRQ_ERROR)) { |
| 1266 | ahci_error_intr(ap, status); |
| 1267 | return; |
| 1268 | } |
| 1269 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1270 | if (ap->sactive) |
| 1271 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
| 1272 | else |
| 1273 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); |
| 1274 | |
| 1275 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); |
| 1276 | if (rc > 0) |
| 1277 | return; |
| 1278 | if (rc < 0) { |
| 1279 | ehi->err_mask |= AC_ERR_HSM; |
| 1280 | ehi->action |= ATA_EH_SOFTRESET; |
| 1281 | ata_port_freeze(ap); |
| 1282 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1283 | } |
| 1284 | |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 1285 | /* hmmm... a spurious interupt */ |
| 1286 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1287 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
| 1288 | * implementation for non-NCQ commands. |
| 1289 | */ |
| 1290 | if (!ap->sactive) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1291 | return; |
| 1292 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1293 | if (status & PORT_IRQ_D2H_REG_FIS) { |
| 1294 | if (!pp->ncq_saw_d2h) |
| 1295 | ata_port_printk(ap, KERN_INFO, |
| 1296 | "D2H reg with I during NCQ, " |
| 1297 | "this message won't be printed again\n"); |
| 1298 | pp->ncq_saw_d2h = 1; |
| 1299 | known_irq = 1; |
| 1300 | } |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 1301 | |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1302 | if (status & PORT_IRQ_DMAS_FIS) { |
| 1303 | if (!pp->ncq_saw_dmas) |
| 1304 | ata_port_printk(ap, KERN_INFO, |
| 1305 | "DMAS FIS during NCQ, " |
| 1306 | "this message won't be printed again\n"); |
| 1307 | pp->ncq_saw_dmas = 1; |
| 1308 | known_irq = 1; |
| 1309 | } |
| 1310 | |
Tejun Heo | a2bbd0c | 2007-02-21 16:34:25 +0900 | [diff] [blame] | 1311 | if (status & PORT_IRQ_SDB_FIS) { |
Al Viro | 04d4f7a | 2007-02-09 16:39:30 +0000 | [diff] [blame] | 1312 | const __le32 *f = pp->rx_fis + RX_FIS_SDB; |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1313 | |
Tejun Heo | afb2d55 | 2007-02-27 13:24:19 +0900 | [diff] [blame] | 1314 | if (le32_to_cpu(f[1])) { |
| 1315 | /* SDB FIS containing spurious completions |
| 1316 | * might be dangerous, whine and fail commands |
| 1317 | * with HSM violation. EH will turn off NCQ |
| 1318 | * after several such failures. |
| 1319 | */ |
| 1320 | ata_ehi_push_desc(ehi, |
| 1321 | "spurious completions during NCQ " |
| 1322 | "issue=0x%x SAct=0x%x FIS=%08x:%08x", |
| 1323 | readl(port_mmio + PORT_CMD_ISSUE), |
| 1324 | readl(port_mmio + PORT_SCR_ACT), |
| 1325 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); |
| 1326 | ehi->err_mask |= AC_ERR_HSM; |
| 1327 | ehi->action |= ATA_EH_SOFTRESET; |
| 1328 | ata_port_freeze(ap); |
| 1329 | } else { |
| 1330 | if (!pp->ncq_saw_sdb) |
| 1331 | ata_port_printk(ap, KERN_INFO, |
| 1332 | "spurious SDB FIS %08x:%08x during NCQ, " |
| 1333 | "this message won't be printed again\n", |
| 1334 | le32_to_cpu(f[0]), le32_to_cpu(f[1])); |
| 1335 | pp->ncq_saw_sdb = 1; |
| 1336 | } |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1337 | known_irq = 1; |
| 1338 | } |
| 1339 | |
| 1340 | if (!known_irq) |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1341 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
Tejun Heo | 0291f95 | 2007-01-25 19:16:28 +0900 | [diff] [blame] | 1342 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1343 | status, ap->active_tag, ap->sactive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1344 | } |
| 1345 | |
| 1346 | static void ahci_irq_clear(struct ata_port *ap) |
| 1347 | { |
| 1348 | /* TODO */ |
| 1349 | } |
| 1350 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1351 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1353 | struct ata_host *host = dev_instance; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1354 | struct ahci_host_priv *hpriv; |
| 1355 | unsigned int i, handled = 0; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1356 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1357 | u32 irq_stat, irq_ack = 0; |
| 1358 | |
| 1359 | VPRINTK("ENTER\n"); |
| 1360 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1361 | hpriv = host->private_data; |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1362 | mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1363 | |
| 1364 | /* sigh. 0xffffffff is a valid return from h/w */ |
| 1365 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
| 1366 | irq_stat &= hpriv->port_map; |
| 1367 | if (!irq_stat) |
| 1368 | return IRQ_NONE; |
| 1369 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1370 | spin_lock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1371 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1372 | for (i = 0; i < host->n_ports; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1373 | struct ata_port *ap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1374 | |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1375 | if (!(irq_stat & (1 << i))) |
| 1376 | continue; |
| 1377 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1378 | ap = host->ports[i]; |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1379 | if (ap) { |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1380 | ahci_port_intr(ap); |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1381 | VPRINTK("port %u\n", i); |
| 1382 | } else { |
| 1383 | VPRINTK("port %u (no irq)\n", i); |
Tejun Heo | 6971ed1 | 2006-03-11 12:47:54 +0900 | [diff] [blame] | 1384 | if (ata_ratelimit()) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1385 | dev_printk(KERN_WARNING, host->dev, |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1386 | "interrupt on disabled port %u\n", i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1387 | } |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 1388 | |
| 1389 | irq_ack |= (1 << i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1390 | } |
| 1391 | |
| 1392 | if (irq_ack) { |
| 1393 | writel(irq_ack, mmio + HOST_IRQ_STAT); |
| 1394 | handled = 1; |
| 1395 | } |
| 1396 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1397 | spin_unlock(&host->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1398 | |
| 1399 | VPRINTK("EXIT\n"); |
| 1400 | |
| 1401 | return IRQ_RETVAL(handled); |
| 1402 | } |
| 1403 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 1404 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1405 | { |
| 1406 | struct ata_port *ap = qc->ap; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1407 | void __iomem *port_mmio = ahci_port_base(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1408 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1409 | if (qc->tf.protocol == ATA_PROT_NCQ) |
| 1410 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
| 1411 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1412 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 1413 | |
| 1414 | return 0; |
| 1415 | } |
| 1416 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1417 | static void ahci_freeze(struct ata_port *ap) |
| 1418 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1419 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1420 | |
| 1421 | /* turn IRQ off */ |
| 1422 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 1423 | } |
| 1424 | |
| 1425 | static void ahci_thaw(struct ata_port *ap) |
| 1426 | { |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1427 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1428 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1429 | u32 tmp; |
| 1430 | |
| 1431 | /* clear IRQ */ |
| 1432 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1433 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
Tejun Heo | a718728 | 2007-01-27 11:04:26 +0900 | [diff] [blame] | 1434 | writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1435 | |
| 1436 | /* turn IRQ back on */ |
| 1437 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); |
| 1438 | } |
| 1439 | |
| 1440 | static void ahci_error_handler(struct ata_port *ap) |
| 1441 | { |
Tejun Heo | b51e9e5 | 2006-06-29 01:29:30 +0900 | [diff] [blame] | 1442 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1443 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1444 | ahci_stop_engine(ap); |
| 1445 | ahci_start_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1446 | } |
| 1447 | |
| 1448 | /* perform recovery */ |
Tejun Heo | 4aeb0e3 | 2006-11-01 17:58:33 +0900 | [diff] [blame] | 1449 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset, |
Tejun Heo | f5914a4 | 2006-05-31 18:27:48 +0900 | [diff] [blame] | 1450 | ahci_postreset); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1451 | } |
| 1452 | |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1453 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
| 1454 | { |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1455 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
| 1456 | /* restart engine */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1457 | ahci_stop_engine(ap); |
| 1458 | ahci_start_engine(ap); |
Tejun Heo | ad616ff | 2006-11-01 18:00:24 +0900 | [diff] [blame] | 1459 | } |
| 1460 | |
| 1461 | /* perform recovery */ |
| 1462 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, |
| 1463 | ahci_postreset); |
| 1464 | } |
| 1465 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1466 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
| 1467 | { |
| 1468 | struct ata_port *ap = qc->ap; |
| 1469 | |
Tejun Heo | a51d644 | 2007-03-20 15:24:11 +0900 | [diff] [blame] | 1470 | if (qc->flags & ATA_QCFLAG_FAILED) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1471 | /* make DMA engine forget about the failed command */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1472 | ahci_stop_engine(ap); |
| 1473 | ahci_start_engine(ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 1474 | } |
| 1475 | } |
| 1476 | |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1477 | #ifdef CONFIG_PM |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1478 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
| 1479 | { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1480 | const char *emsg = NULL; |
| 1481 | int rc; |
| 1482 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1483 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1484 | if (rc == 0) |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1485 | ahci_power_down(ap); |
Tejun Heo | 8e16f94 | 2006-11-20 15:42:36 +0900 | [diff] [blame] | 1486 | else { |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1487 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1488 | ahci_start_port(ap); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1489 | } |
| 1490 | |
| 1491 | return rc; |
| 1492 | } |
| 1493 | |
| 1494 | static int ahci_port_resume(struct ata_port *ap) |
| 1495 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1496 | ahci_power_up(ap); |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1497 | ahci_start_port(ap); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1498 | |
| 1499 | return 0; |
| 1500 | } |
| 1501 | |
| 1502 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
| 1503 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1504 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1505 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1506 | u32 ctl; |
| 1507 | |
| 1508 | if (mesg.event == PM_EVENT_SUSPEND) { |
| 1509 | /* AHCI spec rev1.1 section 8.3.3: |
| 1510 | * Software must disable interrupts prior to requesting a |
| 1511 | * transition of the HBA to D3 state. |
| 1512 | */ |
| 1513 | ctl = readl(mmio + HOST_CTL); |
| 1514 | ctl &= ~HOST_IRQ_EN; |
| 1515 | writel(ctl, mmio + HOST_CTL); |
| 1516 | readl(mmio + HOST_CTL); /* flush */ |
| 1517 | } |
| 1518 | |
| 1519 | return ata_pci_device_suspend(pdev, mesg); |
| 1520 | } |
| 1521 | |
| 1522 | static int ahci_pci_device_resume(struct pci_dev *pdev) |
| 1523 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1524 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1525 | int rc; |
| 1526 | |
Tejun Heo | 553c4aa | 2006-12-26 19:39:50 +0900 | [diff] [blame] | 1527 | rc = ata_pci_device_do_resume(pdev); |
| 1528 | if (rc) |
| 1529 | return rc; |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1530 | |
| 1531 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1532 | rc = ahci_reset_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1533 | if (rc) |
| 1534 | return rc; |
| 1535 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1536 | ahci_init_controller(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1537 | } |
| 1538 | |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1539 | ata_host_resume(host); |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1540 | |
| 1541 | return 0; |
| 1542 | } |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 1543 | #endif |
Tejun Heo | c133287 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1544 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1545 | static int ahci_port_start(struct ata_port *ap) |
| 1546 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1547 | struct device *dev = ap->host->dev; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1548 | struct ahci_port_priv *pp; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1549 | void *mem; |
| 1550 | dma_addr_t mem_dma; |
| 1551 | int rc; |
| 1552 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1553 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1554 | if (!pp) |
| 1555 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1556 | |
| 1557 | rc = ata_pad_alloc(ap, dev); |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1558 | if (rc) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1559 | return rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1560 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1561 | mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, |
| 1562 | GFP_KERNEL); |
| 1563 | if (!mem) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1564 | return -ENOMEM; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1565 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 1566 | |
| 1567 | /* |
| 1568 | * First item in chunk of DMA memory: 32-slot command table, |
| 1569 | * 32 bytes each in size |
| 1570 | */ |
| 1571 | pp->cmd_slot = mem; |
| 1572 | pp->cmd_slot_dma = mem_dma; |
| 1573 | |
| 1574 | mem += AHCI_CMD_SLOT_SZ; |
| 1575 | mem_dma += AHCI_CMD_SLOT_SZ; |
| 1576 | |
| 1577 | /* |
| 1578 | * Second item: Received-FIS area |
| 1579 | */ |
| 1580 | pp->rx_fis = mem; |
| 1581 | pp->rx_fis_dma = mem_dma; |
| 1582 | |
| 1583 | mem += AHCI_RX_FIS_SZ; |
| 1584 | mem_dma += AHCI_RX_FIS_SZ; |
| 1585 | |
| 1586 | /* |
| 1587 | * Third item: data area for storing a single command |
| 1588 | * and its scatter-gather table |
| 1589 | */ |
| 1590 | pp->cmd_tbl = mem; |
| 1591 | pp->cmd_tbl_dma = mem_dma; |
| 1592 | |
| 1593 | ap->private_data = pp; |
| 1594 | |
Jeff Garzik | df69c9c | 2007-05-26 20:46:51 -0400 | [diff] [blame] | 1595 | /* engage engines, captain */ |
| 1596 | return ahci_port_resume(ap); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1597 | } |
| 1598 | |
| 1599 | static void ahci_port_stop(struct ata_port *ap) |
| 1600 | { |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1601 | const char *emsg = NULL; |
| 1602 | int rc; |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1603 | |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1604 | /* de-initialize port */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1605 | rc = ahci_deinit_port(ap, &emsg); |
Tejun Heo | 0be0aa9 | 2006-07-26 15:59:26 +0900 | [diff] [blame] | 1606 | if (rc) |
| 1607 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 1608 | } |
| 1609 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1610 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1611 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1612 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1613 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1614 | if (using_dac && |
| 1615 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 1616 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 1617 | if (rc) { |
| 1618 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1619 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1620 | dev_printk(KERN_ERR, &pdev->dev, |
| 1621 | "64-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1622 | return rc; |
| 1623 | } |
| 1624 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1625 | } else { |
| 1626 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 1627 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1628 | dev_printk(KERN_ERR, &pdev->dev, |
| 1629 | "32-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1630 | return rc; |
| 1631 | } |
| 1632 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1633 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1634 | dev_printk(KERN_ERR, &pdev->dev, |
| 1635 | "32-bit consistent DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1636 | return rc; |
| 1637 | } |
| 1638 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1639 | return 0; |
| 1640 | } |
| 1641 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1642 | static void ahci_print_info(struct ata_host *host) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1643 | { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1644 | struct ahci_host_priv *hpriv = host->private_data; |
| 1645 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 1646 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1647 | u32 vers, cap, impl, speed; |
| 1648 | const char *speed_s; |
| 1649 | u16 cc; |
| 1650 | const char *scc_s; |
| 1651 | |
| 1652 | vers = readl(mmio + HOST_VERSION); |
| 1653 | cap = hpriv->cap; |
| 1654 | impl = hpriv->port_map; |
| 1655 | |
| 1656 | speed = (cap >> 20) & 0xf; |
| 1657 | if (speed == 1) |
| 1658 | speed_s = "1.5"; |
| 1659 | else if (speed == 2) |
| 1660 | speed_s = "3"; |
| 1661 | else |
| 1662 | speed_s = "?"; |
| 1663 | |
| 1664 | pci_read_config_word(pdev, 0x0a, &cc); |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1665 | if (cc == PCI_CLASS_STORAGE_IDE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1666 | scc_s = "IDE"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1667 | else if (cc == PCI_CLASS_STORAGE_SATA) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1668 | scc_s = "SATA"; |
Conke Hu | c9f8947 | 2007-01-09 05:32:51 -0500 | [diff] [blame] | 1669 | else if (cc == PCI_CLASS_STORAGE_RAID) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1670 | scc_s = "RAID"; |
| 1671 | else |
| 1672 | scc_s = "unknown"; |
| 1673 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1674 | dev_printk(KERN_INFO, &pdev->dev, |
| 1675 | "AHCI %02x%02x.%02x%02x " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1676 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
| 1677 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1678 | |
| 1679 | (vers >> 24) & 0xff, |
| 1680 | (vers >> 16) & 0xff, |
| 1681 | (vers >> 8) & 0xff, |
| 1682 | vers & 0xff, |
| 1683 | |
| 1684 | ((cap >> 8) & 0x1f) + 1, |
| 1685 | (cap & 0x1f) + 1, |
| 1686 | speed_s, |
| 1687 | impl, |
| 1688 | scc_s); |
| 1689 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1690 | dev_printk(KERN_INFO, &pdev->dev, |
| 1691 | "flags: " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1692 | "%s%s%s%s%s%s" |
| 1693 | "%s%s%s%s%s%s%s\n" |
| 1694 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1695 | |
| 1696 | cap & (1 << 31) ? "64bit " : "", |
| 1697 | cap & (1 << 30) ? "ncq " : "", |
| 1698 | cap & (1 << 28) ? "ilck " : "", |
| 1699 | cap & (1 << 27) ? "stag " : "", |
| 1700 | cap & (1 << 26) ? "pm " : "", |
| 1701 | cap & (1 << 25) ? "led " : "", |
| 1702 | |
| 1703 | cap & (1 << 24) ? "clo " : "", |
| 1704 | cap & (1 << 19) ? "nz " : "", |
| 1705 | cap & (1 << 18) ? "only " : "", |
| 1706 | cap & (1 << 17) ? "pmp " : "", |
| 1707 | cap & (1 << 15) ? "pio " : "", |
| 1708 | cap & (1 << 14) ? "slum " : "", |
| 1709 | cap & (1 << 13) ? "part " : "" |
| 1710 | ); |
| 1711 | } |
| 1712 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1713 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1714 | { |
| 1715 | static int printed_version; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1716 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
| 1717 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1718 | struct device *dev = &pdev->dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1719 | struct ahci_host_priv *hpriv; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1720 | struct ata_host *host; |
| 1721 | int i, rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1722 | |
| 1723 | VPRINTK("ENTER\n"); |
| 1724 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1725 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
| 1726 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1727 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1728 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1729 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1730 | /* acquire resources */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1731 | rc = pcim_enable_device(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1732 | if (rc) |
| 1733 | return rc; |
| 1734 | |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1735 | rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
| 1736 | if (rc == -EBUSY) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1737 | pcim_pin_device(pdev); |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 1738 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1739 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1740 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1741 | if (pci_enable_msi(pdev)) |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1742 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1743 | |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1744 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
| 1745 | if (!hpriv) |
| 1746 | return -ENOMEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1747 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1748 | /* save initial config */ |
| 1749 | ahci_save_initial_config(pdev, &pi, hpriv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1750 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1751 | /* prepare host */ |
| 1752 | if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ)) |
| 1753 | pi.flags |= ATA_FLAG_NCQ; |
| 1754 | |
| 1755 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); |
| 1756 | if (!host) |
| 1757 | return -ENOMEM; |
| 1758 | host->iomap = pcim_iomap_table(pdev); |
| 1759 | host->private_data = hpriv; |
| 1760 | |
| 1761 | for (i = 0; i < host->n_ports; i++) { |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 1762 | struct ata_port *ap = host->ports[i]; |
| 1763 | void __iomem *port_mmio = ahci_port_base(ap); |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1764 | |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 1765 | /* standard SATA port setup */ |
| 1766 | if (hpriv->port_map & (1 << i)) { |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1767 | ap->ioaddr.cmd_addr = port_mmio; |
| 1768 | ap->ioaddr.scr_addr = port_mmio + PORT_SCR; |
Jeff Garzik | dab632e | 2007-05-28 08:33:01 -0400 | [diff] [blame] | 1769 | } |
| 1770 | |
| 1771 | /* disabled/not-implemented port */ |
| 1772 | else |
| 1773 | ap->ops = &ata_dummy_port_ops; |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1774 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1775 | |
| 1776 | /* initialize adapter */ |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1777 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1778 | if (rc) |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1779 | return rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1780 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1781 | rc = ahci_reset_controller(host); |
| 1782 | if (rc) |
| 1783 | return rc; |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1784 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1785 | ahci_init_controller(host); |
| 1786 | ahci_print_info(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1787 | |
Tejun Heo | 4447d35 | 2007-04-17 23:44:08 +0900 | [diff] [blame] | 1788 | pci_set_master(pdev); |
| 1789 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, |
| 1790 | &ahci_sht); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1791 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1792 | |
| 1793 | static int __init ahci_init(void) |
| 1794 | { |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 1795 | return pci_register_driver(&ahci_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1796 | } |
| 1797 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1798 | static void __exit ahci_exit(void) |
| 1799 | { |
| 1800 | pci_unregister_driver(&ahci_pci_driver); |
| 1801 | } |
| 1802 | |
| 1803 | |
| 1804 | MODULE_AUTHOR("Jeff Garzik"); |
| 1805 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); |
| 1806 | MODULE_LICENSE("GPL"); |
| 1807 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); |
Jeff Garzik | 6885433 | 2005-08-23 02:53:51 -0400 | [diff] [blame] | 1808 | MODULE_VERSION(DRV_VERSION); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1809 | |
| 1810 | module_init(ahci_init); |
| 1811 | module_exit(ahci_exit); |