blob: ed61297686814be272dbde922bf94d8977894bf5 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * TLB support routines.
3 *
4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 *
7 * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
8 * Modified RID allocation for SMP
9 * Goutham Rao <goutham.rao@intel.com>
10 * IPI based ptc implementation and A-step IPI implementation.
Peter Keiltydcc17d12005-10-31 16:44:47 -050011 * Rohit Seth <rohit.seth@intel.com>
12 * Ken Chen <kenneth.w.chen@intel.com>
de Dinechin, Christophe (Integrity VM)aec103b2007-12-13 15:03:07 +000013 * Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
Fenghua Yu2046b942008-04-04 11:05:59 -070014 * Copyright (C) 2007 Intel Corp
15 * Fenghua Yu <fenghua.yu@intel.com>
16 * Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/smp.h>
23#include <linux/mm.h>
Peter Keiltydcc17d12005-10-31 16:44:47 -050024#include <linux/bootmem.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090025#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
27#include <asm/delay.h>
28#include <asm/mmu_context.h>
29#include <asm/pgalloc.h>
30#include <asm/pal.h>
31#include <asm/tlbflush.h>
Peter Keiltydcc17d12005-10-31 16:44:47 -050032#include <asm/dma.h>
Xiantao Zhang96651892008-04-03 11:02:58 -070033#include <asm/processor.h>
Fenghua Yu2046b942008-04-04 11:05:59 -070034#include <asm/sal.h>
Xiantao Zhang96651892008-04-03 11:02:58 -070035#include <asm/tlb.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
37static struct {
Matthew Wilcoxe088a4a2009-05-22 13:49:49 -070038 u64 mask; /* mask of supported purge page-sizes */
Chen, Kenneth W58cd9082005-10-29 18:47:04 -070039 unsigned long max_bits; /* log2 of largest supported purge page-size */
Linus Torvalds1da177e2005-04-16 15:20:36 -070040} purge;
41
42struct ia64_ctx ia64_ctx = {
Milind Arun Choudhary8737d592007-04-15 22:51:23 +053043 .lock = __SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
44 .next = 1,
45 .max_ctx = ~0U
Linus Torvalds1da177e2005-04-16 15:20:36 -070046};
47
48DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
Xiantao Zhang96651892008-04-03 11:02:58 -070049DEFINE_PER_CPU(u8, ia64_tr_num); /*Number of TR slots in current processor*/
50DEFINE_PER_CPU(u8, ia64_tr_used); /*Max Slot number used by kernel*/
51
Tony Luck6c57a332010-01-07 16:10:57 -080052struct ia64_tr_entry *ia64_idtrs[NR_CPUS];
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54/*
Peter Keiltydcc17d12005-10-31 16:44:47 -050055 * Initializes the ia64_ctx.bitmap array based on max_ctx+1.
56 * Called after cpu_init() has setup ia64_ctx.max_ctx based on
57 * maximum RID that is supported by boot CPU.
58 */
59void __init
60mmu_context_init (void)
61{
62 ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
63 ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
64}
65
66/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070067 * Acquire the ia64_ctx.lock before calling this function!
68 */
69void
70wrap_mmu_context (struct mm_struct *mm)
71{
Chen, Kenneth W58cd9082005-10-29 18:47:04 -070072 int i, cpu;
Peter Keiltydcc17d12005-10-31 16:44:47 -050073 unsigned long flush_bit;
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
Peter Keiltydcc17d12005-10-31 16:44:47 -050075 for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
76 flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
77 ia64_ctx.bitmap[i] ^= flush_bit;
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 }
Peter Keiltydcc17d12005-10-31 16:44:47 -050079
80 /* use offset at 300 to skip daemons */
81 ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
82 ia64_ctx.max_ctx, 300);
83 ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
84 ia64_ctx.max_ctx, ia64_ctx.next);
85
Chen, Kenneth W58cd9082005-10-29 18:47:04 -070086 /*
87 * can't call flush_tlb_all() here because of race condition
88 * with O(1) scheduler [EF]
89 */
90 cpu = get_cpu(); /* prevent preemption/migration */
91 for_each_online_cpu(i)
92 if (i != cpu)
93 per_cpu(ia64_need_tlb_flush, i) = 1;
94 put_cpu();
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 local_flush_tlb_all();
96}
97
Fenghua Yu2046b942008-04-04 11:05:59 -070098/*
99 * Implement "spinaphores" ... like counting semaphores, but they
100 * spin instead of sleeping. If there are ever any other users for
101 * this primitive it can be moved up to a spinaphore.h header.
102 */
103struct spinaphore {
Tony Luck883a3ac2009-10-09 10:52:39 -0700104 unsigned long ticket;
105 unsigned long serve;
Fenghua Yu2046b942008-04-04 11:05:59 -0700106};
107
108static inline void spinaphore_init(struct spinaphore *ss, int val)
109{
Tony Luck883a3ac2009-10-09 10:52:39 -0700110 ss->ticket = 0;
111 ss->serve = val;
Fenghua Yu2046b942008-04-04 11:05:59 -0700112}
113
114static inline void down_spin(struct spinaphore *ss)
115{
Tony Luck883a3ac2009-10-09 10:52:39 -0700116 unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve;
117
118 if (time_before(t, ss->serve))
119 return;
120
121 ia64_invala();
122
123 for (;;) {
Tony Luckb70f4e82010-06-30 10:46:16 -0700124 asm volatile ("ld8.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory");
Tony Luck883a3ac2009-10-09 10:52:39 -0700125 if (time_before(t, serve))
126 return;
127 cpu_relax();
128 }
Fenghua Yu2046b942008-04-04 11:05:59 -0700129}
130
131static inline void up_spin(struct spinaphore *ss)
132{
Tony Luck883a3ac2009-10-09 10:52:39 -0700133 ia64_fetchadd(1, &ss->serve, rel);
Fenghua Yu2046b942008-04-04 11:05:59 -0700134}
135
136static struct spinaphore ptcg_sem;
137static u16 nptcg = 1;
138static int need_ptcg_sem = 1;
139static int toolatetochangeptcgsem = 0;
140
141/*
Fenghua Yua6c75b862008-03-14 13:57:08 -0700142 * Kernel parameter "nptcg=" overrides max number of concurrent global TLB
143 * purges which is reported from either PAL or SAL PALO.
144 *
145 * We don't have sanity checking for nptcg value. It's the user's responsibility
146 * for valid nptcg value on the platform. Otherwise, kernel may hang in some
147 * cases.
148 */
149static int __init
150set_nptcg(char *str)
151{
152 int value = 0;
153
154 get_option(&str, &value);
155 setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER);
156
157 return 1;
158}
159
160__setup("nptcg=", set_nptcg);
161
162/*
Fenghua Yu2046b942008-04-04 11:05:59 -0700163 * Maximum number of simultaneous ptc.g purges in the system can
164 * be defined by PAL_VM_SUMMARY (in which case we should take
165 * the smallest value for any cpu in the system) or by the PAL
166 * override table (in which case we should ignore the value from
167 * PAL_VM_SUMMARY).
168 *
Fenghua Yua6c75b862008-03-14 13:57:08 -0700169 * Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g
170 * purges defined in either PAL_VM_SUMMARY or PAL override table. In this case,
171 * we should ignore the value from either PAL_VM_SUMMARY or PAL override table.
172 *
Fenghua Yu2046b942008-04-04 11:05:59 -0700173 * Complicating the logic here is the fact that num_possible_cpus()
174 * isn't fully setup until we start bringing cpus online.
175 */
176void
Fenghua Yua6c75b862008-03-14 13:57:08 -0700177setup_ptcg_sem(int max_purges, int nptcg_from)
Fenghua Yu2046b942008-04-04 11:05:59 -0700178{
Fenghua Yua6c75b862008-03-14 13:57:08 -0700179 static int kp_override;
180 static int palo_override;
Fenghua Yu2046b942008-04-04 11:05:59 -0700181 static int firstcpu = 1;
182
183 if (toolatetochangeptcgsem) {
Hidetoshi Setoe617fce2008-04-25 23:13:09 +0900184 if (nptcg_from == NPTCG_FROM_PAL && max_purges == 0)
185 BUG_ON(1 < nptcg);
186 else
187 BUG_ON(max_purges < nptcg);
Fenghua Yu2046b942008-04-04 11:05:59 -0700188 return;
189 }
190
Fenghua Yua6c75b862008-03-14 13:57:08 -0700191 if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) {
192 kp_override = 1;
193 nptcg = max_purges;
194 goto resetsema;
195 }
196 if (kp_override) {
197 need_ptcg_sem = num_possible_cpus() > nptcg;
198 return;
199 }
200
201 if (nptcg_from == NPTCG_FROM_PALO) {
202 palo_override = 1;
Fenghua Yu2046b942008-04-04 11:05:59 -0700203
204 /* In PALO max_purges == 0 really means it! */
205 if (max_purges == 0)
206 panic("Whoa! Platform does not support global TLB purges.\n");
207 nptcg = max_purges;
208 if (nptcg == PALO_MAX_TLB_PURGES) {
209 need_ptcg_sem = 0;
210 return;
211 }
212 goto resetsema;
213 }
Fenghua Yua6c75b862008-03-14 13:57:08 -0700214 if (palo_override) {
Fenghua Yu2046b942008-04-04 11:05:59 -0700215 if (nptcg != PALO_MAX_TLB_PURGES)
216 need_ptcg_sem = (num_possible_cpus() > nptcg);
217 return;
218 }
219
220 /* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
221 if (max_purges == 0) max_purges = 1;
222
223 if (firstcpu) {
224 nptcg = max_purges;
225 firstcpu = 0;
226 }
227 if (max_purges < nptcg)
228 nptcg = max_purges;
229 if (nptcg == PAL_MAX_PURGES) {
230 need_ptcg_sem = 0;
231 return;
232 } else
233 need_ptcg_sem = (num_possible_cpus() > nptcg);
234
235resetsema:
236 spinaphore_init(&ptcg_sem, max_purges);
237}
238
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239void
Chen, Kenneth W58cd9082005-10-29 18:47:04 -0700240ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
241 unsigned long end, unsigned long nbits)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242{
de Dinechin, Christophe (Integrity VM)aec103b2007-12-13 15:03:07 +0000243 struct mm_struct *active_mm = current->active_mm;
244
Fenghua Yu2046b942008-04-04 11:05:59 -0700245 toolatetochangeptcgsem = 1;
246
de Dinechin, Christophe (Integrity VM)aec103b2007-12-13 15:03:07 +0000247 if (mm != active_mm) {
248 /* Restore region IDs for mm */
249 if (mm && active_mm) {
250 activate_context(mm);
251 } else {
252 flush_tlb_all();
253 return;
254 }
Dean Roec1902aa2005-10-27 15:41:04 -0500255 }
256
Fenghua Yu2046b942008-04-04 11:05:59 -0700257 if (need_ptcg_sem)
258 down_spin(&ptcg_sem);
259
260 do {
261 /*
262 * Flush ALAT entries also.
263 */
264 ia64_ptcga(start, (nbits << 2));
265 ia64_srlz_i();
266 start += (1UL << nbits);
267 } while (start < end);
268
269 if (need_ptcg_sem)
270 up_spin(&ptcg_sem);
de Dinechin, Christophe (Integrity VM)aec103b2007-12-13 15:03:07 +0000271
272 if (mm != active_mm) {
273 activate_context(active_mm);
274 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275}
276
277void
278local_flush_tlb_all (void)
279{
280 unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
281
282 addr = local_cpu_data->ptce_base;
283 count0 = local_cpu_data->ptce_count[0];
284 count1 = local_cpu_data->ptce_count[1];
285 stride0 = local_cpu_data->ptce_stride[0];
286 stride1 = local_cpu_data->ptce_stride[1];
287
288 local_irq_save(flags);
289 for (i = 0; i < count0; ++i) {
290 for (j = 0; j < count1; ++j) {
291 ia64_ptce(addr);
292 addr += stride1;
293 }
294 addr += stride0;
295 }
296 local_irq_restore(flags);
297 ia64_srlz_i(); /* srlz.i implies srlz.d */
298}
299
300void
Chen, Kenneth W58cd9082005-10-29 18:47:04 -0700301flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
302 unsigned long end)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303{
304 struct mm_struct *mm = vma->vm_mm;
305 unsigned long size = end - start;
306 unsigned long nbits;
307
Dean Roec1902aa2005-10-27 15:41:04 -0500308#ifndef CONFIG_SMP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309 if (mm != current->active_mm) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 mm->context = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311 return;
312 }
Dean Roec1902aa2005-10-27 15:41:04 -0500313#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314
315 nbits = ia64_fls(size + 0xfff);
Chen, Kenneth W58cd9082005-10-29 18:47:04 -0700316 while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
317 (nbits < purge.max_bits))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318 ++nbits;
319 if (nbits > purge.max_bits)
320 nbits = purge.max_bits;
321 start &= ~((1UL << nbits) - 1);
322
Hugh Dickins663b97f2005-10-29 18:16:28 -0700323 preempt_disable();
Chen, Kenneth Wce9eed52006-03-06 14:12:54 -0800324#ifdef CONFIG_SMP
Rusty Russell5d8c39f2009-03-16 14:12:48 +1030325 if (mm != current->active_mm || cpumask_weight(mm_cpumask(mm)) != 1) {
Chen, Kenneth Wce9eed52006-03-06 14:12:54 -0800326 platform_global_tlb_purge(mm, start, end, nbits);
327 preempt_enable();
328 return;
329 }
330#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331 do {
332 ia64_ptcl(start, (nbits<<2));
333 start += (1UL << nbits);
334 } while (start < end);
Hugh Dickins663b97f2005-10-29 18:16:28 -0700335 preempt_enable();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 ia64_srlz_i(); /* srlz.i implies srlz.d */
337}
338EXPORT_SYMBOL(flush_tlb_range);
339
Greg Kroah-Hartman5b5e76e2012-12-21 14:05:13 -0800340void ia64_tlb_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341{
Jes Sorensen256a7e02007-07-11 17:26:30 +0200342 ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
Matthew Wilcoxe088a4a2009-05-22 13:49:49 -0700343 u64 tr_pgbits;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344 long status;
Xiantao Zhang96651892008-04-03 11:02:58 -0700345 pal_vm_info_1_u_t vm_info_1;
346 pal_vm_info_2_u_t vm_info_2;
347 int cpu = smp_processor_id();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348
349 if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
Joe Perchesc2eeb322007-11-19 17:47:53 -0800350 printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 "defaulting to architected purge page-sizes.\n", status);
352 purge.mask = 0x115557000UL;
353 }
354 purge.max_bits = ia64_fls(purge.mask);
355
356 ia64_get_ptce(&ptce_info);
357 local_cpu_data->ptce_base = ptce_info.base;
358 local_cpu_data->ptce_count[0] = ptce_info.count[0];
359 local_cpu_data->ptce_count[1] = ptce_info.count[1];
360 local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
361 local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
362
Chen, Kenneth W58cd9082005-10-29 18:47:04 -0700363 local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
Xiantao Zhang96651892008-04-03 11:02:58 -0700364 status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
365
366 if (status) {
367 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
368 per_cpu(ia64_tr_num, cpu) = 8;
369 return;
370 }
371 per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
372 if (per_cpu(ia64_tr_num, cpu) >
373 (vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
374 per_cpu(ia64_tr_num, cpu) =
375 vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
376 if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
Tony Lucka9894a42008-10-17 13:47:53 -0700377 static int justonce = 1;
Xiantao Zhang96651892008-04-03 11:02:58 -0700378 per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
Tony Lucka9894a42008-10-17 13:47:53 -0700379 if (justonce) {
380 justonce = 0;
381 printk(KERN_DEBUG "TR register number exceeds "
382 "IA64_TR_ALLOC_MAX!\n");
383 }
Xiantao Zhang96651892008-04-03 11:02:58 -0700384 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385}
Xiantao Zhang96651892008-04-03 11:02:58 -0700386
387/*
388 * is_tr_overlap
389 *
390 * Check overlap with inserted TRs.
391 */
392static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
393{
394 u64 tr_log_size;
395 u64 tr_end;
396 u64 va_rr = ia64_get_rr(va);
397 u64 va_rid = RR_TO_RID(va_rr);
398 u64 va_end = va + (1<<log_size) - 1;
399
400 if (va_rid != RR_TO_RID(p->rr))
401 return 0;
402 tr_log_size = (p->itir & 0xff) >> 2;
403 tr_end = p->ifa + (1<<tr_log_size) - 1;
404
405 if (va > tr_end || p->ifa > va_end)
406 return 0;
407 return 1;
408
409}
410
411/*
412 * ia64_insert_tr in virtual mode. Allocate a TR slot
413 *
414 * target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
415 *
416 * va : virtual address.
417 * pte : pte entries inserted.
418 * log_size: range to be covered.
419 *
420 * Return value: <0 : error No.
421 *
422 * >=0 : slot number allocated for TR.
423 * Must be called with preemption disabled.
424 */
425int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
426{
427 int i, r;
428 unsigned long psr;
429 struct ia64_tr_entry *p;
430 int cpu = smp_processor_id();
431
Tony Luck6c57a332010-01-07 16:10:57 -0800432 if (!ia64_idtrs[cpu]) {
433 ia64_idtrs[cpu] = kmalloc(2 * IA64_TR_ALLOC_MAX *
434 sizeof (struct ia64_tr_entry), GFP_KERNEL);
435 if (!ia64_idtrs[cpu])
436 return -ENOMEM;
437 }
Xiantao Zhang96651892008-04-03 11:02:58 -0700438 r = -EINVAL;
439 /*Check overlap with existing TR entries*/
440 if (target_mask & 0x1) {
Tony Luck6c57a332010-01-07 16:10:57 -0800441 p = ia64_idtrs[cpu];
Xiantao Zhang96651892008-04-03 11:02:58 -0700442 for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
443 i++, p++) {
444 if (p->pte & 0x1)
445 if (is_tr_overlap(p, va, log_size)) {
446 printk(KERN_DEBUG "Overlapped Entry"
447 "Inserted for TR Reigster!!\n");
448 goto out;
449 }
450 }
451 }
452 if (target_mask & 0x2) {
Tony Luck6c57a332010-01-07 16:10:57 -0800453 p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX;
Xiantao Zhang96651892008-04-03 11:02:58 -0700454 for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
455 i++, p++) {
456 if (p->pte & 0x1)
457 if (is_tr_overlap(p, va, log_size)) {
458 printk(KERN_DEBUG "Overlapped Entry"
459 "Inserted for TR Reigster!!\n");
460 goto out;
461 }
462 }
463 }
464
465 for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
466 switch (target_mask & 0x3) {
467 case 1:
Tony Luck6c57a332010-01-07 16:10:57 -0800468 if (!((ia64_idtrs[cpu] + i)->pte & 0x1))
Xiantao Zhang96651892008-04-03 11:02:58 -0700469 goto found;
470 continue;
471 case 2:
Tony Luck6c57a332010-01-07 16:10:57 -0800472 if (!((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
Xiantao Zhang96651892008-04-03 11:02:58 -0700473 goto found;
474 continue;
475 case 3:
Tony Luck6c57a332010-01-07 16:10:57 -0800476 if (!((ia64_idtrs[cpu] + i)->pte & 0x1) &&
477 !((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
Xiantao Zhang96651892008-04-03 11:02:58 -0700478 goto found;
479 continue;
480 default:
481 r = -EINVAL;
482 goto out;
483 }
484 }
485found:
486 if (i >= per_cpu(ia64_tr_num, cpu))
487 return -EBUSY;
488
489 /*Record tr info for mca hander use!*/
490 if (i > per_cpu(ia64_tr_used, cpu))
491 per_cpu(ia64_tr_used, cpu) = i;
492
493 psr = ia64_clear_ic();
494 if (target_mask & 0x1) {
495 ia64_itr(0x1, i, va, pte, log_size);
496 ia64_srlz_i();
Tony Luck6c57a332010-01-07 16:10:57 -0800497 p = ia64_idtrs[cpu] + i;
Xiantao Zhang96651892008-04-03 11:02:58 -0700498 p->ifa = va;
499 p->pte = pte;
500 p->itir = log_size << 2;
501 p->rr = ia64_get_rr(va);
502 }
503 if (target_mask & 0x2) {
504 ia64_itr(0x2, i, va, pte, log_size);
505 ia64_srlz_i();
Tony Luck6c57a332010-01-07 16:10:57 -0800506 p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i;
Xiantao Zhang96651892008-04-03 11:02:58 -0700507 p->ifa = va;
508 p->pte = pte;
509 p->itir = log_size << 2;
510 p->rr = ia64_get_rr(va);
511 }
512 ia64_set_psr(psr);
513 r = i;
514out:
515 return r;
516}
517EXPORT_SYMBOL_GPL(ia64_itr_entry);
518
519/*
520 * ia64_purge_tr
521 *
522 * target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
523 * slot: slot number to be freed.
524 *
525 * Must be called with preemption disabled.
526 */
527void ia64_ptr_entry(u64 target_mask, int slot)
528{
529 int cpu = smp_processor_id();
530 int i;
531 struct ia64_tr_entry *p;
532
533 if (slot < IA64_TR_ALLOC_BASE || slot >= per_cpu(ia64_tr_num, cpu))
534 return;
535
536 if (target_mask & 0x1) {
Tony Luck6c57a332010-01-07 16:10:57 -0800537 p = ia64_idtrs[cpu] + slot;
Xiantao Zhang96651892008-04-03 11:02:58 -0700538 if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
539 p->pte = 0;
540 ia64_ptr(0x1, p->ifa, p->itir>>2);
541 ia64_srlz_i();
542 }
543 }
544
545 if (target_mask & 0x2) {
Tony Luck6c57a332010-01-07 16:10:57 -0800546 p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + slot;
Xiantao Zhang96651892008-04-03 11:02:58 -0700547 if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
548 p->pte = 0;
549 ia64_ptr(0x2, p->ifa, p->itir>>2);
550 ia64_srlz_i();
551 }
552 }
553
554 for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
Tony Luck6c57a332010-01-07 16:10:57 -0800555 if (((ia64_idtrs[cpu] + i)->pte & 0x1) ||
556 ((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
Xiantao Zhang96651892008-04-03 11:02:58 -0700557 break;
558 }
559 per_cpu(ia64_tr_used, cpu) = i;
560}
561EXPORT_SYMBOL_GPL(ia64_ptr_entry);