Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
| 32 | #include "drm_crtc.h" |
| 33 | #include "drm_crtc_helper.h" |
| 34 | #include "intel_drv.h" |
| 35 | #include "i915_drm.h" |
| 36 | #include "i915_drv.h" |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 37 | #include "drm_dp_helper.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | |
Zhao Yakui | ae266c9 | 2009-11-24 09:48:46 +0800 | [diff] [blame] | 39 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 40 | #define DP_LINK_STATUS_SIZE 6 |
| 41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 42 | |
| 43 | #define DP_LINK_CONFIGURATION_SIZE 9 |
| 44 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 45 | struct intel_dp { |
| 46 | struct intel_encoder base; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 47 | uint32_t output_reg; |
| 48 | uint32_t DP; |
| 49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 50 | bool has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 51 | int force_audio; |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 52 | uint32_t color_range; |
Keith Packard | d2b996a | 2011-07-25 22:37:51 -0700 | [diff] [blame] | 53 | int dpms_mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 54 | uint8_t link_bw; |
| 55 | uint8_t lane_count; |
Adam Jackson | 9de88e6 | 2011-07-12 17:38:02 -0400 | [diff] [blame] | 56 | uint8_t dpcd[8]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 57 | struct i2c_adapter adapter; |
| 58 | struct i2c_algo_dp_aux_data algo; |
Adam Jackson | f091737 | 2010-07-16 14:46:27 -0400 | [diff] [blame] | 59 | bool is_pch_edp; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 60 | uint8_t train_set[4]; |
| 61 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 62 | int panel_power_up_delay; |
| 63 | int panel_power_down_delay; |
| 64 | int panel_power_cycle_delay; |
| 65 | int backlight_on_delay; |
| 66 | int backlight_off_delay; |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 67 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 68 | struct delayed_work panel_vdd_work; |
| 69 | bool want_panel_vdd; |
| 70 | unsigned long panel_off_jiffies; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 71 | }; |
| 72 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 73 | /** |
| 74 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 75 | * @intel_dp: DP struct |
| 76 | * |
| 77 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 78 | * will return true, and false otherwise. |
| 79 | */ |
| 80 | static bool is_edp(struct intel_dp *intel_dp) |
| 81 | { |
| 82 | return intel_dp->base.type == INTEL_OUTPUT_EDP; |
| 83 | } |
| 84 | |
| 85 | /** |
| 86 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? |
| 87 | * @intel_dp: DP struct |
| 88 | * |
| 89 | * Returns true if the given DP struct corresponds to a PCH DP port attached |
| 90 | * to an eDP panel, false otherwise. Helpful for determining whether we |
| 91 | * may need FDI resources for a given DP output or not. |
| 92 | */ |
| 93 | static bool is_pch_edp(struct intel_dp *intel_dp) |
| 94 | { |
| 95 | return intel_dp->is_pch_edp; |
| 96 | } |
| 97 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 98 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| 99 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 100 | return container_of(encoder, struct intel_dp, base.base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 101 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 102 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 103 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 104 | { |
| 105 | return container_of(intel_attached_encoder(connector), |
| 106 | struct intel_dp, base); |
| 107 | } |
| 108 | |
Jesse Barnes | 814948a | 2010-10-07 16:01:09 -0700 | [diff] [blame] | 109 | /** |
| 110 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? |
| 111 | * @encoder: DRM encoder |
| 112 | * |
| 113 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed |
| 114 | * by intel_display.c. |
| 115 | */ |
| 116 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) |
| 117 | { |
| 118 | struct intel_dp *intel_dp; |
| 119 | |
| 120 | if (!encoder) |
| 121 | return false; |
| 122 | |
| 123 | intel_dp = enc_to_intel_dp(encoder); |
| 124 | |
| 125 | return is_pch_edp(intel_dp); |
| 126 | } |
| 127 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 128 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| 129 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 130 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 131 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 132 | void |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 133 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 134 | int *lane_num, int *link_bw) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 135 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 136 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 137 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 138 | *lane_num = intel_dp->lane_count; |
| 139 | if (intel_dp->link_bw == DP_LINK_BW_1_62) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 140 | *link_bw = 162000; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 141 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 142 | *link_bw = 270000; |
| 143 | } |
| 144 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 145 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 146 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 147 | { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 148 | int max_lane_count = 4; |
| 149 | |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 150 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 151 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 152 | switch (max_lane_count) { |
| 153 | case 1: case 2: case 4: |
| 154 | break; |
| 155 | default: |
| 156 | max_lane_count = 4; |
| 157 | } |
| 158 | } |
| 159 | return max_lane_count; |
| 160 | } |
| 161 | |
| 162 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 163 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 164 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 165 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 166 | |
| 167 | switch (max_link_bw) { |
| 168 | case DP_LINK_BW_1_62: |
| 169 | case DP_LINK_BW_2_7: |
| 170 | break; |
| 171 | default: |
| 172 | max_link_bw = DP_LINK_BW_1_62; |
| 173 | break; |
| 174 | } |
| 175 | return max_link_bw; |
| 176 | } |
| 177 | |
| 178 | static int |
| 179 | intel_dp_link_clock(uint8_t link_bw) |
| 180 | { |
| 181 | if (link_bw == DP_LINK_BW_2_7) |
| 182 | return 270000; |
| 183 | else |
| 184 | return 162000; |
| 185 | } |
| 186 | |
| 187 | /* I think this is a fiction */ |
| 188 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 189 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 190 | { |
Jesse Barnes | 89c6143 | 2011-06-24 12:19:28 -0700 | [diff] [blame] | 191 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
| 192 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 193 | int bpp = 24; |
Zhenyu Wang | 885a5fb | 2010-01-12 05:38:31 +0800 | [diff] [blame] | 194 | |
Jesse Barnes | 89c6143 | 2011-06-24 12:19:28 -0700 | [diff] [blame] | 195 | if (intel_crtc) |
| 196 | bpp = intel_crtc->bpp; |
| 197 | |
| 198 | return (pixel_clock * bpp + 7) / 8; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 202 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 203 | { |
| 204 | return (max_link_clock * max_lanes * 8) / 10; |
| 205 | } |
| 206 | |
| 207 | static int |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 208 | intel_dp_mode_valid(struct drm_connector *connector, |
| 209 | struct drm_display_mode *mode) |
| 210 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 211 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 212 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
| 213 | int max_lanes = intel_dp_max_lane_count(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 214 | |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 215 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
| 216 | if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 217 | return MODE_PANEL; |
| 218 | |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 219 | if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 220 | return MODE_PANEL; |
| 221 | } |
| 222 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 223 | /* only refuse the mode on non eDP since we have seen some weird eDP panels |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 224 | which are outside spec tolerances but somehow work by magic */ |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 225 | if (!is_edp(intel_dp) && |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 226 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 227 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 228 | return MODE_CLOCK_HIGH; |
| 229 | |
| 230 | if (mode->clock < 10000) |
| 231 | return MODE_CLOCK_LOW; |
| 232 | |
| 233 | return MODE_OK; |
| 234 | } |
| 235 | |
| 236 | static uint32_t |
| 237 | pack_aux(uint8_t *src, int src_bytes) |
| 238 | { |
| 239 | int i; |
| 240 | uint32_t v = 0; |
| 241 | |
| 242 | if (src_bytes > 4) |
| 243 | src_bytes = 4; |
| 244 | for (i = 0; i < src_bytes; i++) |
| 245 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 246 | return v; |
| 247 | } |
| 248 | |
| 249 | static void |
| 250 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
| 251 | { |
| 252 | int i; |
| 253 | if (dst_bytes > 4) |
| 254 | dst_bytes = 4; |
| 255 | for (i = 0; i < dst_bytes; i++) |
| 256 | dst[i] = src >> ((3-i) * 8); |
| 257 | } |
| 258 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 259 | /* hrawclock is 1/4 the FSB frequency */ |
| 260 | static int |
| 261 | intel_hrawclk(struct drm_device *dev) |
| 262 | { |
| 263 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 264 | uint32_t clkcfg; |
| 265 | |
| 266 | clkcfg = I915_READ(CLKCFG); |
| 267 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 268 | case CLKCFG_FSB_400: |
| 269 | return 100; |
| 270 | case CLKCFG_FSB_533: |
| 271 | return 133; |
| 272 | case CLKCFG_FSB_667: |
| 273 | return 166; |
| 274 | case CLKCFG_FSB_800: |
| 275 | return 200; |
| 276 | case CLKCFG_FSB_1067: |
| 277 | return 266; |
| 278 | case CLKCFG_FSB_1333: |
| 279 | return 333; |
| 280 | /* these two are just a guess; one of them might be right */ |
| 281 | case CLKCFG_FSB_1600: |
| 282 | case CLKCFG_FSB_1600_ALT: |
| 283 | return 400; |
| 284 | default: |
| 285 | return 133; |
| 286 | } |
| 287 | } |
| 288 | |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 289 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
| 290 | { |
| 291 | struct drm_device *dev = intel_dp->base.base.dev; |
| 292 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 293 | |
| 294 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; |
| 295 | } |
| 296 | |
| 297 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) |
| 298 | { |
| 299 | struct drm_device *dev = intel_dp->base.base.dev; |
| 300 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 301 | |
| 302 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; |
| 303 | } |
| 304 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 305 | static void |
| 306 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 307 | { |
| 308 | struct drm_device *dev = intel_dp->base.base.dev; |
| 309 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 310 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 311 | if (!is_edp(intel_dp)) |
| 312 | return; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 313 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 314 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 315 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 316 | I915_READ(PCH_PP_STATUS), |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 317 | I915_READ(PCH_PP_CONTROL)); |
| 318 | } |
| 319 | } |
| 320 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 321 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 322 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 323 | uint8_t *send, int send_bytes, |
| 324 | uint8_t *recv, int recv_size) |
| 325 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 326 | uint32_t output_reg = intel_dp->output_reg; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 327 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 328 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 329 | uint32_t ch_ctl = output_reg + 0x10; |
| 330 | uint32_t ch_data = ch_ctl + 4; |
| 331 | int i; |
| 332 | int recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 333 | uint32_t status; |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 334 | uint32_t aux_clock_divider; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 335 | int try, precharge; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 336 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 337 | intel_dp_check_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 338 | /* The clock divider is based off the hrawclk, |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 339 | * and would like to run at 2MHz. So, take the |
| 340 | * hrawclk value and divide by 2 and use that |
Jesse Barnes | 6176b8f | 2010-09-08 12:42:00 -0700 | [diff] [blame] | 341 | * |
| 342 | * Note that PCH attached eDP panels should use a 125MHz input |
| 343 | * clock divider. |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 344 | */ |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 345 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 346 | if (IS_GEN6(dev)) |
| 347 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ |
| 348 | else |
| 349 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
| 350 | } else if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 351 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 352 | else |
| 353 | aux_clock_divider = intel_hrawclk(dev) / 2; |
| 354 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 355 | if (IS_GEN6(dev)) |
| 356 | precharge = 3; |
| 357 | else |
| 358 | precharge = 5; |
| 359 | |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 360 | /* Try to wait for any previous AUX channel activity */ |
| 361 | for (try = 0; try < 3; try++) { |
| 362 | status = I915_READ(ch_ctl); |
| 363 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 364 | break; |
| 365 | msleep(1); |
| 366 | } |
| 367 | |
| 368 | if (try == 3) { |
| 369 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 370 | I915_READ(ch_ctl)); |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 371 | return -EBUSY; |
| 372 | } |
| 373 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 374 | /* Must try at least 3 times according to DP spec */ |
| 375 | for (try = 0; try < 5; try++) { |
| 376 | /* Load the send data into the aux channel data registers */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 377 | for (i = 0; i < send_bytes; i += 4) |
| 378 | I915_WRITE(ch_data + i, |
| 379 | pack_aux(send + i, send_bytes - i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 380 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 381 | /* Send the command and wait for it to complete */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 382 | I915_WRITE(ch_ctl, |
| 383 | DP_AUX_CH_CTL_SEND_BUSY | |
| 384 | DP_AUX_CH_CTL_TIME_OUT_400us | |
| 385 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 386 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 387 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
| 388 | DP_AUX_CH_CTL_DONE | |
| 389 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 390 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 391 | for (;;) { |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 392 | status = I915_READ(ch_ctl); |
| 393 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 394 | break; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 395 | udelay(100); |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 396 | } |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 397 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 398 | /* Clear done status and any errors */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 399 | I915_WRITE(ch_ctl, |
| 400 | status | |
| 401 | DP_AUX_CH_CTL_DONE | |
| 402 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 403 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
| 404 | if (status & DP_AUX_CH_CTL_DONE) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 405 | break; |
| 406 | } |
| 407 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 408 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 409 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 410 | return -EBUSY; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | /* Check for timeout or receive error. |
| 414 | * Timeouts occur when the sink is not connected |
| 415 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 416 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 417 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 418 | return -EIO; |
| 419 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 420 | |
| 421 | /* Timeouts occur when the device isn't connected, so they're |
| 422 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 423 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 424 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 425 | return -ETIMEDOUT; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 426 | } |
| 427 | |
| 428 | /* Unload any bytes sent back from the other side */ |
| 429 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 430 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 431 | if (recv_bytes > recv_size) |
| 432 | recv_bytes = recv_size; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 433 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 434 | for (i = 0; i < recv_bytes; i += 4) |
| 435 | unpack_aux(I915_READ(ch_data + i), |
| 436 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 437 | |
| 438 | return recv_bytes; |
| 439 | } |
| 440 | |
| 441 | /* Write data to the aux channel in native mode */ |
| 442 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 443 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 444 | uint16_t address, uint8_t *send, int send_bytes) |
| 445 | { |
| 446 | int ret; |
| 447 | uint8_t msg[20]; |
| 448 | int msg_bytes; |
| 449 | uint8_t ack; |
| 450 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 451 | intel_dp_check_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 452 | if (send_bytes > 16) |
| 453 | return -1; |
| 454 | msg[0] = AUX_NATIVE_WRITE << 4; |
| 455 | msg[1] = address >> 8; |
Zhenyu Wang | eebc863 | 2009-07-24 01:00:30 +0800 | [diff] [blame] | 456 | msg[2] = address & 0xff; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 457 | msg[3] = send_bytes - 1; |
| 458 | memcpy(&msg[4], send, send_bytes); |
| 459 | msg_bytes = send_bytes + 4; |
| 460 | for (;;) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 461 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 462 | if (ret < 0) |
| 463 | return ret; |
| 464 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
| 465 | break; |
| 466 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 467 | udelay(100); |
| 468 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 469 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 470 | } |
| 471 | return send_bytes; |
| 472 | } |
| 473 | |
| 474 | /* Write a single byte to the aux channel in native mode */ |
| 475 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 476 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 477 | uint16_t address, uint8_t byte) |
| 478 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 479 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 480 | } |
| 481 | |
| 482 | /* read bytes from a native aux channel */ |
| 483 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 484 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 485 | uint16_t address, uint8_t *recv, int recv_bytes) |
| 486 | { |
| 487 | uint8_t msg[4]; |
| 488 | int msg_bytes; |
| 489 | uint8_t reply[20]; |
| 490 | int reply_bytes; |
| 491 | uint8_t ack; |
| 492 | int ret; |
| 493 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 494 | intel_dp_check_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 495 | msg[0] = AUX_NATIVE_READ << 4; |
| 496 | msg[1] = address >> 8; |
| 497 | msg[2] = address & 0xff; |
| 498 | msg[3] = recv_bytes - 1; |
| 499 | |
| 500 | msg_bytes = 4; |
| 501 | reply_bytes = recv_bytes + 1; |
| 502 | |
| 503 | for (;;) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 504 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 505 | reply, reply_bytes); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 506 | if (ret == 0) |
| 507 | return -EPROTO; |
| 508 | if (ret < 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 509 | return ret; |
| 510 | ack = reply[0]; |
| 511 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { |
| 512 | memcpy(recv, reply + 1, ret - 1); |
| 513 | return ret - 1; |
| 514 | } |
| 515 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 516 | udelay(100); |
| 517 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 518 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 519 | } |
| 520 | } |
| 521 | |
| 522 | static int |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 523 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
| 524 | uint8_t write_byte, uint8_t *read_byte) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 525 | { |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 526 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 527 | struct intel_dp *intel_dp = container_of(adapter, |
| 528 | struct intel_dp, |
| 529 | adapter); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 530 | uint16_t address = algo_data->address; |
| 531 | uint8_t msg[5]; |
| 532 | uint8_t reply[2]; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 533 | unsigned retry; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 534 | int msg_bytes; |
| 535 | int reply_bytes; |
| 536 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 537 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 538 | intel_dp_check_edp(intel_dp); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 539 | /* Set up the command byte */ |
| 540 | if (mode & MODE_I2C_READ) |
| 541 | msg[0] = AUX_I2C_READ << 4; |
| 542 | else |
| 543 | msg[0] = AUX_I2C_WRITE << 4; |
| 544 | |
| 545 | if (!(mode & MODE_I2C_STOP)) |
| 546 | msg[0] |= AUX_I2C_MOT << 4; |
| 547 | |
| 548 | msg[1] = address >> 8; |
| 549 | msg[2] = address; |
| 550 | |
| 551 | switch (mode) { |
| 552 | case MODE_I2C_WRITE: |
| 553 | msg[3] = 0; |
| 554 | msg[4] = write_byte; |
| 555 | msg_bytes = 5; |
| 556 | reply_bytes = 1; |
| 557 | break; |
| 558 | case MODE_I2C_READ: |
| 559 | msg[3] = 0; |
| 560 | msg_bytes = 4; |
| 561 | reply_bytes = 2; |
| 562 | break; |
| 563 | default: |
| 564 | msg_bytes = 3; |
| 565 | reply_bytes = 1; |
| 566 | break; |
| 567 | } |
| 568 | |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 569 | for (retry = 0; retry < 5; retry++) { |
| 570 | ret = intel_dp_aux_ch(intel_dp, |
| 571 | msg, msg_bytes, |
| 572 | reply, reply_bytes); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 573 | if (ret < 0) { |
Dave Airlie | 3ff9916 | 2009-12-08 14:03:47 +1000 | [diff] [blame] | 574 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 575 | return ret; |
| 576 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 577 | |
| 578 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { |
| 579 | case AUX_NATIVE_REPLY_ACK: |
| 580 | /* I2C-over-AUX Reply field is only valid |
| 581 | * when paired with AUX ACK. |
| 582 | */ |
| 583 | break; |
| 584 | case AUX_NATIVE_REPLY_NACK: |
| 585 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
| 586 | return -EREMOTEIO; |
| 587 | case AUX_NATIVE_REPLY_DEFER: |
| 588 | udelay(100); |
| 589 | continue; |
| 590 | default: |
| 591 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
| 592 | reply[0]); |
| 593 | return -EREMOTEIO; |
| 594 | } |
| 595 | |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 596 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
| 597 | case AUX_I2C_REPLY_ACK: |
| 598 | if (mode == MODE_I2C_READ) { |
| 599 | *read_byte = reply[1]; |
| 600 | } |
| 601 | return reply_bytes - 1; |
| 602 | case AUX_I2C_REPLY_NACK: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 603 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 604 | return -EREMOTEIO; |
| 605 | case AUX_I2C_REPLY_DEFER: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 606 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 607 | udelay(100); |
| 608 | break; |
| 609 | default: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 610 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 611 | return -EREMOTEIO; |
| 612 | } |
| 613 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 614 | |
| 615 | DRM_ERROR("too many retries, giving up\n"); |
| 616 | return -EREMOTEIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 617 | } |
| 618 | |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 619 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 620 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 621 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 622 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 623 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 624 | struct intel_connector *intel_connector, const char *name) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 625 | { |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 626 | int ret; |
| 627 | |
Zhenyu Wang | d54e9d2 | 2009-10-19 15:43:51 +0800 | [diff] [blame] | 628 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 629 | intel_dp->algo.running = false; |
| 630 | intel_dp->algo.address = 0; |
| 631 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 632 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 633 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 634 | intel_dp->adapter.owner = THIS_MODULE; |
| 635 | intel_dp->adapter.class = I2C_CLASS_DDC; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 636 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 637 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
| 638 | intel_dp->adapter.algo_data = &intel_dp->algo; |
| 639 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; |
| 640 | |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 641 | ironlake_edp_panel_vdd_on(intel_dp); |
| 642 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 643 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 644 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | static bool |
| 648 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, |
| 649 | struct drm_display_mode *adjusted_mode) |
| 650 | { |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 651 | struct drm_device *dev = encoder->dev; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 652 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 653 | int lane_count, clock; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 654 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
| 655 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 656 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
| 657 | |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 658 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
| 659 | intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 660 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
| 661 | mode, adjusted_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 662 | /* |
| 663 | * the mode->clock is used to calculate the Data&Link M/N |
| 664 | * of the pipe. For the eDP the fixed clock should be used. |
| 665 | */ |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 666 | mode->clock = intel_dp->panel_fixed_mode->clock; |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 667 | } |
| 668 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 669 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
| 670 | for (clock = 0; clock <= max_clock; clock++) { |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 671 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 672 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 673 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
Zhenyu Wang | 885a5fb | 2010-01-12 05:38:31 +0800 | [diff] [blame] | 674 | <= link_avail) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 675 | intel_dp->link_bw = bws[clock]; |
| 676 | intel_dp->lane_count = lane_count; |
| 677 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 678 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
| 679 | "count %d clock %d\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 680 | intel_dp->link_bw, intel_dp->lane_count, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 681 | adjusted_mode->clock); |
| 682 | return true; |
| 683 | } |
| 684 | } |
| 685 | } |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 686 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 687 | if (is_edp(intel_dp)) { |
| 688 | /* okay we failed just pick the highest */ |
| 689 | intel_dp->lane_count = max_lane_count; |
| 690 | intel_dp->link_bw = bws[max_clock]; |
| 691 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); |
| 692 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " |
| 693 | "count %d clock %d\n", |
| 694 | intel_dp->link_bw, intel_dp->lane_count, |
| 695 | adjusted_mode->clock); |
| 696 | |
| 697 | return true; |
| 698 | } |
| 699 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 700 | return false; |
| 701 | } |
| 702 | |
| 703 | struct intel_dp_m_n { |
| 704 | uint32_t tu; |
| 705 | uint32_t gmch_m; |
| 706 | uint32_t gmch_n; |
| 707 | uint32_t link_m; |
| 708 | uint32_t link_n; |
| 709 | }; |
| 710 | |
| 711 | static void |
| 712 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
| 713 | { |
| 714 | while (*num > 0xffffff || *den > 0xffffff) { |
| 715 | *num >>= 1; |
| 716 | *den >>= 1; |
| 717 | } |
| 718 | } |
| 719 | |
| 720 | static void |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 721 | intel_dp_compute_m_n(int bpp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 722 | int nlanes, |
| 723 | int pixel_clock, |
| 724 | int link_clock, |
| 725 | struct intel_dp_m_n *m_n) |
| 726 | { |
| 727 | m_n->tu = 64; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 728 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 729 | m_n->gmch_n = link_clock * nlanes; |
| 730 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
| 731 | m_n->link_m = pixel_clock; |
| 732 | m_n->link_n = link_clock; |
| 733 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
| 734 | } |
| 735 | |
| 736 | void |
| 737 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| 738 | struct drm_display_mode *adjusted_mode) |
| 739 | { |
| 740 | struct drm_device *dev = crtc->dev; |
| 741 | struct drm_mode_config *mode_config = &dev->mode_config; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 742 | struct drm_encoder *encoder; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 743 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 858fa035 | 2011-06-24 12:19:24 -0700 | [diff] [blame] | 745 | int lane_count = 4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 746 | struct intel_dp_m_n m_n; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 747 | int pipe = intel_crtc->pipe; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 748 | |
| 749 | /* |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 750 | * Find the lane count in the intel_encoder private |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 751 | */ |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 752 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 753 | struct intel_dp *intel_dp; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 754 | |
Dan Carpenter | d8201ab | 2010-05-07 10:39:00 +0200 | [diff] [blame] | 755 | if (encoder->crtc != crtc) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 756 | continue; |
| 757 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 758 | intel_dp = enc_to_intel_dp(encoder); |
| 759 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { |
| 760 | lane_count = intel_dp->lane_count; |
Jesse Barnes | 5119066 | 2010-10-07 16:01:08 -0700 | [diff] [blame] | 761 | break; |
| 762 | } else if (is_edp(intel_dp)) { |
| 763 | lane_count = dev_priv->edp.lanes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 764 | break; |
| 765 | } |
| 766 | } |
| 767 | |
| 768 | /* |
| 769 | * Compute the GMCH and Link ratios. The '3' here is |
| 770 | * the number of bytes_per_pixel post-LUT, which we always |
| 771 | * set up for 8-bits of R/G/B, or 3 bytes total. |
| 772 | */ |
Jesse Barnes | 858fa035 | 2011-06-24 12:19:24 -0700 | [diff] [blame] | 773 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 774 | mode->clock, adjusted_mode->clock, &m_n); |
| 775 | |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 776 | if (HAS_PCH_SPLIT(dev)) { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 777 | I915_WRITE(TRANSDATA_M1(pipe), |
| 778 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
| 779 | m_n.gmch_m); |
| 780 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); |
| 781 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); |
| 782 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 783 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 784 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
| 785 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
| 786 | m_n.gmch_m); |
| 787 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); |
| 788 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); |
| 789 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 790 | } |
| 791 | } |
| 792 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 793 | static void ironlake_edp_pll_on(struct drm_encoder *encoder); |
| 794 | static void ironlake_edp_pll_off(struct drm_encoder *encoder); |
| 795 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 796 | static void |
| 797 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
| 798 | struct drm_display_mode *adjusted_mode) |
| 799 | { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 800 | struct drm_device *dev = encoder->dev; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 801 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 802 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 803 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 804 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 805 | /* Turn on the eDP PLL if needed */ |
| 806 | if (is_edp(intel_dp)) { |
| 807 | if (!is_pch_edp(intel_dp)) |
| 808 | ironlake_edp_pll_on(encoder); |
| 809 | else |
| 810 | ironlake_edp_pll_off(encoder); |
| 811 | } |
| 812 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 813 | intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
| 814 | intel_dp->DP |= intel_dp->color_range; |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 815 | |
| 816 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 817 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 818 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 819 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 820 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 821 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 822 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 823 | else |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 824 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 825 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 826 | switch (intel_dp->lane_count) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 827 | case 1: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 828 | intel_dp->DP |= DP_PORT_WIDTH_1; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 829 | break; |
| 830 | case 2: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 831 | intel_dp->DP |= DP_PORT_WIDTH_2; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 832 | break; |
| 833 | case 4: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 834 | intel_dp->DP |= DP_PORT_WIDTH_4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 835 | break; |
| 836 | } |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 837 | if (intel_dp->has_audio) { |
| 838 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
| 839 | pipe_name(intel_crtc->pipe)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 840 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 841 | intel_write_eld(encoder, adjusted_mode); |
| 842 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 843 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 844 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
| 845 | intel_dp->link_configuration[0] = intel_dp->link_bw; |
| 846 | intel_dp->link_configuration[1] = intel_dp->lane_count; |
Adam Jackson | a2cab1b | 2011-07-12 17:38:05 -0400 | [diff] [blame] | 847 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 848 | |
| 849 | /* |
Adam Jackson | 9962c92 | 2010-05-13 14:45:42 -0400 | [diff] [blame] | 850 | * Check for DPCD version > 1.1 and enhanced framing support |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 851 | */ |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 852 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 853 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 854 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 855 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 856 | } |
| 857 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 858 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
| 859 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 860 | intel_dp->DP |= DP_PIPEB_SELECT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 861 | |
Jesse Barnes | 895692b | 2010-10-07 16:01:23 -0700 | [diff] [blame] | 862 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 863 | /* don't miss out required setting for eDP */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 864 | intel_dp->DP |= DP_PLL_ENABLE; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 865 | if (adjusted_mode->clock < 200000) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 866 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 867 | else |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 868 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 869 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 870 | } |
| 871 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 872 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
| 873 | { |
| 874 | unsigned long off_time; |
| 875 | unsigned long delay; |
Keith Packard | 32ce697 | 2011-09-29 16:51:26 -0700 | [diff] [blame] | 876 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 877 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
Keith Packard | 32ce697 | 2011-09-29 16:51:26 -0700 | [diff] [blame] | 878 | |
| 879 | if (ironlake_edp_have_panel_power(intel_dp) || |
| 880 | ironlake_edp_have_panel_vdd(intel_dp)) |
| 881 | { |
| 882 | DRM_DEBUG_KMS("Panel still on, no delay needed\n"); |
| 883 | return; |
| 884 | } |
| 885 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 886 | off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay); |
| 887 | if (time_after(jiffies, off_time)) { |
| 888 | DRM_DEBUG_KMS("Time already passed"); |
| 889 | return; |
| 890 | } |
| 891 | delay = jiffies_to_msecs(off_time - jiffies); |
| 892 | if (delay > intel_dp->panel_power_down_delay) |
| 893 | delay = intel_dp->panel_power_down_delay; |
| 894 | DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay); |
| 895 | msleep(delay); |
| 896 | } |
| 897 | |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 898 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
| 899 | { |
| 900 | struct drm_device *dev = intel_dp->base.base.dev; |
| 901 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 902 | u32 pp; |
| 903 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 904 | if (!is_edp(intel_dp)) |
| 905 | return; |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 906 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 907 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 908 | WARN(intel_dp->want_panel_vdd, |
| 909 | "eDP VDD already requested on\n"); |
| 910 | |
| 911 | intel_dp->want_panel_vdd = true; |
| 912 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
| 913 | DRM_DEBUG_KMS("eDP VDD already on\n"); |
| 914 | return; |
| 915 | } |
| 916 | |
| 917 | ironlake_wait_panel_off(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 918 | pp = I915_READ(PCH_PP_CONTROL); |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 919 | pp &= ~PANEL_UNLOCK_MASK; |
| 920 | pp |= PANEL_UNLOCK_REGS; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 921 | pp |= EDP_FORCE_VDD; |
| 922 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 923 | POSTING_READ(PCH_PP_CONTROL); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 924 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
| 925 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 926 | |
| 927 | /* |
| 928 | * If the panel wasn't on, delay before accessing aux channel |
| 929 | */ |
| 930 | if (!ironlake_edp_have_panel_power(intel_dp)) { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 931 | DRM_DEBUG_KMS("eDP was not running\n"); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 932 | msleep(intel_dp->panel_power_up_delay); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 933 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 934 | } |
| 935 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 936 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 937 | { |
| 938 | struct drm_device *dev = intel_dp->base.base.dev; |
| 939 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 940 | u32 pp; |
| 941 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 942 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
| 943 | pp = I915_READ(PCH_PP_CONTROL); |
| 944 | pp &= ~PANEL_UNLOCK_MASK; |
| 945 | pp |= PANEL_UNLOCK_REGS; |
| 946 | pp &= ~EDP_FORCE_VDD; |
| 947 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 948 | POSTING_READ(PCH_PP_CONTROL); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 949 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 950 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 951 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
| 952 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); |
| 953 | intel_dp->panel_off_jiffies = jiffies; |
| 954 | } |
| 955 | } |
| 956 | |
| 957 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
| 958 | { |
| 959 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 960 | struct intel_dp, panel_vdd_work); |
| 961 | struct drm_device *dev = intel_dp->base.base.dev; |
| 962 | |
| 963 | mutex_lock(&dev->struct_mutex); |
| 964 | ironlake_panel_vdd_off_sync(intel_dp); |
| 965 | mutex_unlock(&dev->struct_mutex); |
| 966 | } |
| 967 | |
| 968 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
| 969 | { |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 970 | if (!is_edp(intel_dp)) |
| 971 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 972 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 973 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
| 974 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
| 975 | |
| 976 | intel_dp->want_panel_vdd = false; |
| 977 | |
| 978 | if (sync) { |
| 979 | ironlake_panel_vdd_off_sync(intel_dp); |
| 980 | } else { |
| 981 | /* |
| 982 | * Queue the timer to fire a long |
| 983 | * time from now (relative to the power down delay) |
| 984 | * to keep the panel power up across a sequence of operations |
| 985 | */ |
| 986 | schedule_delayed_work(&intel_dp->panel_vdd_work, |
| 987 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
| 988 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 989 | } |
| 990 | |
Jesse Barnes | 7eaf554 | 2010-09-08 12:41:59 -0700 | [diff] [blame] | 991 | /* Returns true if the panel was already on when called */ |
Keith Packard | 86a3073 | 2011-10-20 13:40:33 -0700 | [diff] [blame] | 992 | static void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 993 | { |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 994 | struct drm_device *dev = intel_dp->base.base.dev; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 995 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 996 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 997 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 998 | if (!is_edp(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 999 | return; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1000 | if (ironlake_edp_have_panel_power(intel_dp)) |
Keith Packard | 7d639f3 | 2011-09-29 16:05:34 -0700 | [diff] [blame] | 1001 | return; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1002 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1003 | ironlake_wait_panel_off(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1004 | pp = I915_READ(PCH_PP_CONTROL); |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1005 | pp &= ~PANEL_UNLOCK_MASK; |
| 1006 | pp |= PANEL_UNLOCK_REGS; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1007 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1008 | if (IS_GEN5(dev)) { |
| 1009 | /* ILK workaround: disable reset around power sequence */ |
| 1010 | pp &= ~PANEL_POWER_RESET; |
| 1011 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1012 | POSTING_READ(PCH_PP_CONTROL); |
| 1013 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1014 | |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1015 | pp |= POWER_TARGET_ON; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1016 | I915_WRITE(PCH_PP_CONTROL, pp); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1017 | POSTING_READ(PCH_PP_CONTROL); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1018 | |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1019 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
| 1020 | 5000)) |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 1021 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
| 1022 | I915_READ(PCH_PP_STATUS)); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1023 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1024 | if (IS_GEN5(dev)) { |
| 1025 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
| 1026 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1027 | POSTING_READ(PCH_PP_CONTROL); |
| 1028 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1029 | } |
| 1030 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1031 | static void ironlake_edp_panel_off(struct drm_encoder *encoder) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1032 | { |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1033 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1034 | struct drm_device *dev = encoder->dev; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1035 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1036 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
| 1037 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1038 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1039 | if (!is_edp(intel_dp)) |
| 1040 | return; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1041 | pp = I915_READ(PCH_PP_CONTROL); |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1042 | pp &= ~PANEL_UNLOCK_MASK; |
| 1043 | pp |= PANEL_UNLOCK_REGS; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1044 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1045 | if (IS_GEN5(dev)) { |
| 1046 | /* ILK workaround: disable reset around power sequence */ |
| 1047 | pp &= ~PANEL_POWER_RESET; |
| 1048 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1049 | POSTING_READ(PCH_PP_CONTROL); |
| 1050 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1051 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1052 | intel_dp->panel_off_jiffies = jiffies; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1053 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1054 | if (IS_GEN5(dev)) { |
| 1055 | pp &= ~POWER_TARGET_ON; |
| 1056 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1057 | POSTING_READ(PCH_PP_CONTROL); |
| 1058 | pp &= ~POWER_TARGET_ON; |
| 1059 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1060 | POSTING_READ(PCH_PP_CONTROL); |
| 1061 | msleep(intel_dp->panel_power_cycle_delay); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1062 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1063 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
| 1064 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
| 1065 | I915_READ(PCH_PP_STATUS)); |
| 1066 | |
| 1067 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
| 1068 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1069 | POSTING_READ(PCH_PP_CONTROL); |
| 1070 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1071 | } |
| 1072 | |
Keith Packard | 86a3073 | 2011-10-20 13:40:33 -0700 | [diff] [blame] | 1073 | static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1074 | { |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1075 | struct drm_device *dev = intel_dp->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1076 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1077 | u32 pp; |
| 1078 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1079 | if (!is_edp(intel_dp)) |
| 1080 | return; |
| 1081 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1082 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1083 | /* |
| 1084 | * If we enable the backlight right away following a panel power |
| 1085 | * on, we may see slight flicker as the panel syncs with the eDP |
| 1086 | * link. So delay a bit to make sure the image is solid before |
| 1087 | * allowing it to appear. |
| 1088 | */ |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1089 | msleep(intel_dp->backlight_on_delay); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1090 | pp = I915_READ(PCH_PP_CONTROL); |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1091 | pp &= ~PANEL_UNLOCK_MASK; |
| 1092 | pp |= PANEL_UNLOCK_REGS; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1093 | pp |= EDP_BLC_ENABLE; |
| 1094 | I915_WRITE(PCH_PP_CONTROL, pp); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1095 | POSTING_READ(PCH_PP_CONTROL); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1096 | } |
| 1097 | |
Keith Packard | 86a3073 | 2011-10-20 13:40:33 -0700 | [diff] [blame] | 1098 | static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1099 | { |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1100 | struct drm_device *dev = intel_dp->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1101 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1102 | u32 pp; |
| 1103 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1104 | if (!is_edp(intel_dp)) |
| 1105 | return; |
| 1106 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1107 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1108 | pp = I915_READ(PCH_PP_CONTROL); |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1109 | pp &= ~PANEL_UNLOCK_MASK; |
| 1110 | pp |= PANEL_UNLOCK_REGS; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1111 | pp &= ~EDP_BLC_ENABLE; |
| 1112 | I915_WRITE(PCH_PP_CONTROL, pp); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1113 | POSTING_READ(PCH_PP_CONTROL); |
| 1114 | msleep(intel_dp->backlight_off_delay); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1115 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1116 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1117 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
| 1118 | { |
| 1119 | struct drm_device *dev = encoder->dev; |
| 1120 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1121 | u32 dpa_ctl; |
| 1122 | |
| 1123 | DRM_DEBUG_KMS("\n"); |
| 1124 | dpa_ctl = I915_READ(DP_A); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1125 | dpa_ctl |= DP_PLL_ENABLE; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1126 | I915_WRITE(DP_A, dpa_ctl); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1127 | POSTING_READ(DP_A); |
| 1128 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1129 | } |
| 1130 | |
| 1131 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) |
| 1132 | { |
| 1133 | struct drm_device *dev = encoder->dev; |
| 1134 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1135 | u32 dpa_ctl; |
| 1136 | |
| 1137 | dpa_ctl = I915_READ(DP_A); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1138 | dpa_ctl &= ~DP_PLL_ENABLE; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1139 | I915_WRITE(DP_A, dpa_ctl); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 1140 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1141 | udelay(200); |
| 1142 | } |
| 1143 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1144 | /* If the sink supports it, try to set the power state appropriately */ |
| 1145 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
| 1146 | { |
| 1147 | int ret, i; |
| 1148 | |
| 1149 | /* Should have a valid DPCD by this point */ |
| 1150 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 1151 | return; |
| 1152 | |
| 1153 | if (mode != DRM_MODE_DPMS_ON) { |
| 1154 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, |
| 1155 | DP_SET_POWER_D3); |
| 1156 | if (ret != 1) |
| 1157 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
| 1158 | } else { |
| 1159 | /* |
| 1160 | * When turning on, we need to retry for 1ms to give the sink |
| 1161 | * time to wake up. |
| 1162 | */ |
| 1163 | for (i = 0; i < 3; i++) { |
| 1164 | ret = intel_dp_aux_native_write_1(intel_dp, |
| 1165 | DP_SET_POWER, |
| 1166 | DP_SET_POWER_D0); |
| 1167 | if (ret == 1) |
| 1168 | break; |
| 1169 | msleep(1); |
| 1170 | } |
| 1171 | } |
| 1172 | } |
| 1173 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1174 | static void intel_dp_prepare(struct drm_encoder *encoder) |
| 1175 | { |
| 1176 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1177 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1178 | /* Wake up the sink first */ |
Keith Packard | f58ff85 | 2011-09-28 16:44:14 -0700 | [diff] [blame] | 1179 | ironlake_edp_panel_vdd_on(intel_dp); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1180 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1181 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1182 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1183 | /* Make sure the panel is off before trying to |
| 1184 | * change the mode |
| 1185 | */ |
| 1186 | ironlake_edp_backlight_off(intel_dp); |
Jesse Barnes | 736085b | 2010-10-08 10:35:55 -0700 | [diff] [blame] | 1187 | intel_dp_link_down(intel_dp); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1188 | ironlake_edp_panel_off(encoder); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1189 | } |
| 1190 | |
| 1191 | static void intel_dp_commit(struct drm_encoder *encoder) |
| 1192 | { |
| 1193 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 1194 | struct drm_device *dev = encoder->dev; |
| 1195 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1196 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1197 | ironlake_edp_panel_vdd_on(intel_dp); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1198 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1199 | intel_dp_start_link_train(intel_dp); |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1200 | ironlake_edp_panel_on(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1201 | ironlake_edp_panel_vdd_off(intel_dp, true); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1202 | |
| 1203 | intel_dp_complete_link_train(intel_dp); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1204 | ironlake_edp_backlight_on(intel_dp); |
Keith Packard | d2b996a | 2011-07-25 22:37:51 -0700 | [diff] [blame] | 1205 | |
| 1206 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; |
Jesse Barnes | d4270e5 | 2011-10-11 10:43:02 -0700 | [diff] [blame] | 1207 | |
| 1208 | if (HAS_PCH_CPT(dev)) |
| 1209 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1210 | } |
| 1211 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1212 | static void |
| 1213 | intel_dp_dpms(struct drm_encoder *encoder, int mode) |
| 1214 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1215 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 1216 | struct drm_device *dev = encoder->dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1217 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1218 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1219 | |
| 1220 | if (mode != DRM_MODE_DPMS_ON) { |
Keith Packard | 245e270 | 2011-10-05 19:53:09 -0700 | [diff] [blame] | 1221 | ironlake_edp_panel_vdd_on(intel_dp); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1222 | if (is_edp(intel_dp)) |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1223 | ironlake_edp_backlight_off(intel_dp); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1224 | intel_dp_sink_dpms(intel_dp, mode); |
Jesse Barnes | 736085b | 2010-10-08 10:35:55 -0700 | [diff] [blame] | 1225 | intel_dp_link_down(intel_dp); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1226 | ironlake_edp_panel_off(encoder); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1227 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1228 | ironlake_edp_pll_off(encoder); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1229 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1230 | } else { |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1231 | ironlake_edp_panel_vdd_on(intel_dp); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1232 | intel_dp_sink_dpms(intel_dp, mode); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1233 | if (!(dp_reg & DP_PORT_EN)) { |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1234 | intel_dp_start_link_train(intel_dp); |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1235 | ironlake_edp_panel_on(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1236 | ironlake_edp_panel_vdd_off(intel_dp, true); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1237 | intel_dp_complete_link_train(intel_dp); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1238 | ironlake_edp_backlight_on(intel_dp); |
Keith Packard | bee7eb2 | 2011-09-28 16:28:00 -0700 | [diff] [blame] | 1239 | } else |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1240 | ironlake_edp_panel_vdd_off(intel_dp, false); |
| 1241 | ironlake_edp_backlight_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1242 | } |
Keith Packard | d2b996a | 2011-07-25 22:37:51 -0700 | [diff] [blame] | 1243 | intel_dp->dpms_mode = mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1244 | } |
| 1245 | |
| 1246 | /* |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1247 | * Native read with retry for link status and receiver capability reads for |
| 1248 | * cases where the sink may still be asleep. |
| 1249 | */ |
| 1250 | static bool |
| 1251 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
| 1252 | uint8_t *recv, int recv_bytes) |
| 1253 | { |
| 1254 | int ret, i; |
| 1255 | |
| 1256 | /* |
| 1257 | * Sinks are *supposed* to come up within 1ms from an off state, |
| 1258 | * but we're also supposed to retry 3 times per the spec. |
| 1259 | */ |
| 1260 | for (i = 0; i < 3; i++) { |
| 1261 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
| 1262 | recv_bytes); |
| 1263 | if (ret == recv_bytes) |
| 1264 | return true; |
| 1265 | msleep(1); |
| 1266 | } |
| 1267 | |
| 1268 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1269 | } |
| 1270 | |
| 1271 | /* |
| 1272 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 1273 | * link status information |
| 1274 | */ |
| 1275 | static bool |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1276 | intel_dp_get_link_status(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1277 | { |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1278 | return intel_dp_aux_native_read_retry(intel_dp, |
| 1279 | DP_LANE0_1_STATUS, |
| 1280 | intel_dp->link_status, |
| 1281 | DP_LINK_STATUS_SIZE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1282 | } |
| 1283 | |
| 1284 | static uint8_t |
| 1285 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 1286 | int r) |
| 1287 | { |
| 1288 | return link_status[r - DP_LANE0_1_STATUS]; |
| 1289 | } |
| 1290 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1291 | static uint8_t |
| 1292 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 1293 | int lane) |
| 1294 | { |
| 1295 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 1296 | int s = ((lane & 1) ? |
| 1297 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : |
| 1298 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); |
| 1299 | uint8_t l = intel_dp_link_status(link_status, i); |
| 1300 | |
| 1301 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; |
| 1302 | } |
| 1303 | |
| 1304 | static uint8_t |
| 1305 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 1306 | int lane) |
| 1307 | { |
| 1308 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); |
| 1309 | int s = ((lane & 1) ? |
| 1310 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : |
| 1311 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); |
| 1312 | uint8_t l = intel_dp_link_status(link_status, i); |
| 1313 | |
| 1314 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; |
| 1315 | } |
| 1316 | |
| 1317 | |
| 1318 | #if 0 |
| 1319 | static char *voltage_names[] = { |
| 1320 | "0.4V", "0.6V", "0.8V", "1.2V" |
| 1321 | }; |
| 1322 | static char *pre_emph_names[] = { |
| 1323 | "0dB", "3.5dB", "6dB", "9.5dB" |
| 1324 | }; |
| 1325 | static char *link_train_names[] = { |
| 1326 | "pattern 1", "pattern 2", "idle", "off" |
| 1327 | }; |
| 1328 | #endif |
| 1329 | |
| 1330 | /* |
| 1331 | * These are source-specific values; current Intel hardware supports |
| 1332 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
| 1333 | */ |
| 1334 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 |
| 1335 | |
| 1336 | static uint8_t |
| 1337 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) |
| 1338 | { |
| 1339 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1340 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1341 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1342 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1343 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1344 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1345 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 1346 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1347 | default: |
| 1348 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 1349 | } |
| 1350 | } |
| 1351 | |
| 1352 | static void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1353 | intel_get_adjust_train(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1354 | { |
| 1355 | uint8_t v = 0; |
| 1356 | uint8_t p = 0; |
| 1357 | int lane; |
| 1358 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1359 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
| 1360 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); |
| 1361 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1362 | |
| 1363 | if (this_v > v) |
| 1364 | v = this_v; |
| 1365 | if (this_p > p) |
| 1366 | p = this_p; |
| 1367 | } |
| 1368 | |
| 1369 | if (v >= I830_DP_VOLTAGE_MAX) |
| 1370 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; |
| 1371 | |
| 1372 | if (p >= intel_dp_pre_emphasis_max(v)) |
| 1373 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
| 1374 | |
| 1375 | for (lane = 0; lane < 4; lane++) |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1376 | intel_dp->train_set[lane] = v | p; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1377 | } |
| 1378 | |
| 1379 | static uint32_t |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1380 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1381 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1382 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1383 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1384 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1385 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1386 | default: |
| 1387 | signal_levels |= DP_VOLTAGE_0_4; |
| 1388 | break; |
| 1389 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1390 | signal_levels |= DP_VOLTAGE_0_6; |
| 1391 | break; |
| 1392 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1393 | signal_levels |= DP_VOLTAGE_0_8; |
| 1394 | break; |
| 1395 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1396 | signal_levels |= DP_VOLTAGE_1_2; |
| 1397 | break; |
| 1398 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1399 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1400 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 1401 | default: |
| 1402 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 1403 | break; |
| 1404 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1405 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 1406 | break; |
| 1407 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 1408 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 1409 | break; |
| 1410 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 1411 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 1412 | break; |
| 1413 | } |
| 1414 | return signal_levels; |
| 1415 | } |
| 1416 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1417 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 1418 | static uint32_t |
| 1419 | intel_gen6_edp_signal_levels(uint8_t train_set) |
| 1420 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1421 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 1422 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 1423 | switch (signal_levels) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1424 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1425 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1426 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 1427 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1428 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1429 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1430 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1431 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1432 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1433 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1434 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1435 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1436 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1437 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1438 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1439 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 1440 | "0x%x\n", signal_levels); |
| 1441 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1442 | } |
| 1443 | } |
| 1444 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1445 | static uint8_t |
| 1446 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], |
| 1447 | int lane) |
| 1448 | { |
| 1449 | int i = DP_LANE0_1_STATUS + (lane >> 1); |
| 1450 | int s = (lane & 1) * 4; |
| 1451 | uint8_t l = intel_dp_link_status(link_status, i); |
| 1452 | |
| 1453 | return (l >> s) & 0xf; |
| 1454 | } |
| 1455 | |
| 1456 | /* Check for clock recovery is done on all channels */ |
| 1457 | static bool |
| 1458 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) |
| 1459 | { |
| 1460 | int lane; |
| 1461 | uint8_t lane_status; |
| 1462 | |
| 1463 | for (lane = 0; lane < lane_count; lane++) { |
| 1464 | lane_status = intel_get_lane_status(link_status, lane); |
| 1465 | if ((lane_status & DP_LANE_CR_DONE) == 0) |
| 1466 | return false; |
| 1467 | } |
| 1468 | return true; |
| 1469 | } |
| 1470 | |
| 1471 | /* Check to see if channel eq is done on all channels */ |
| 1472 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ |
| 1473 | DP_LANE_CHANNEL_EQ_DONE|\ |
| 1474 | DP_LANE_SYMBOL_LOCKED) |
| 1475 | static bool |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1476 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1477 | { |
| 1478 | uint8_t lane_align; |
| 1479 | uint8_t lane_status; |
| 1480 | int lane; |
| 1481 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1482 | lane_align = intel_dp_link_status(intel_dp->link_status, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1483 | DP_LANE_ALIGN_STATUS_UPDATED); |
| 1484 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) |
| 1485 | return false; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1486 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
| 1487 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1488 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
| 1489 | return false; |
| 1490 | } |
| 1491 | return true; |
| 1492 | } |
| 1493 | |
| 1494 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1495 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1496 | uint32_t dp_reg_value, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1497 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1498 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1499 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1500 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1501 | int ret; |
| 1502 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1503 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
| 1504 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1505 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1506 | intel_dp_aux_native_write_1(intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1507 | DP_TRAINING_PATTERN_SET, |
| 1508 | dp_train_pat); |
| 1509 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1510 | ret = intel_dp_aux_native_write(intel_dp, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1511 | DP_TRAINING_LANE0_SET, |
| 1512 | intel_dp->train_set, 4); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1513 | if (ret != 4) |
| 1514 | return false; |
| 1515 | |
| 1516 | return true; |
| 1517 | } |
| 1518 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1519 | /* Enable corresponding port and start training pattern 1 */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1520 | static void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1521 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1522 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1523 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1524 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1525 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1526 | int i; |
| 1527 | uint8_t voltage; |
| 1528 | bool clock_recovery = false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1529 | int tries; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1530 | u32 reg; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1531 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1532 | |
Adam Jackson | e851946 | 2011-07-21 17:48:38 -0400 | [diff] [blame] | 1533 | /* |
| 1534 | * On CPT we have to enable the port in training pattern 1, which |
| 1535 | * will happen below in intel_dp_set_link_train. Otherwise, enable |
| 1536 | * the port and wait for it to become active. |
| 1537 | */ |
| 1538 | if (!HAS_PCH_CPT(dev)) { |
| 1539 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
| 1540 | POSTING_READ(intel_dp->output_reg); |
| 1541 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 1542 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1543 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1544 | /* Write the link configuration data */ |
| 1545 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
| 1546 | intel_dp->link_configuration, |
| 1547 | DP_LINK_CONFIGURATION_SIZE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1548 | |
| 1549 | DP |= DP_PORT_EN; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1550 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1551 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
| 1552 | else |
| 1553 | DP &= ~DP_LINK_TRAIN_MASK; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1554 | memset(intel_dp->train_set, 0, 4); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1555 | voltage = 0xff; |
| 1556 | tries = 0; |
| 1557 | clock_recovery = false; |
| 1558 | for (;;) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1559 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1560 | uint32_t signal_levels; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1561 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1562 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1563 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
| 1564 | } else { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1565 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1566 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
| 1567 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1568 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1569 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1570 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
| 1571 | else |
| 1572 | reg = DP | DP_LINK_TRAIN_PAT_1; |
| 1573 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1574 | if (!intel_dp_set_link_train(intel_dp, reg, |
Adam Jackson | 8105585 | 2011-07-21 17:48:37 -0400 | [diff] [blame] | 1575 | DP_TRAINING_PATTERN_1 | |
| 1576 | DP_LINK_SCRAMBLING_DISABLE)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1577 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1578 | /* Set training pattern 1 */ |
| 1579 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1580 | udelay(100); |
| 1581 | if (!intel_dp_get_link_status(intel_dp)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1582 | break; |
| 1583 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1584 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
| 1585 | clock_recovery = true; |
| 1586 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1587 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1588 | |
| 1589 | /* Check to see if we've tried the max voltage */ |
| 1590 | for (i = 0; i < intel_dp->lane_count; i++) |
| 1591 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 1592 | break; |
| 1593 | if (i == intel_dp->lane_count) |
| 1594 | break; |
| 1595 | |
| 1596 | /* Check to see if we've tried the same voltage 5 times */ |
| 1597 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
| 1598 | ++tries; |
| 1599 | if (tries == 5) |
| 1600 | break; |
| 1601 | } else |
| 1602 | tries = 0; |
| 1603 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 1604 | |
| 1605 | /* Compute new intel_dp->train_set as requested by target */ |
| 1606 | intel_get_adjust_train(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1607 | } |
| 1608 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1609 | intel_dp->DP = DP; |
| 1610 | } |
| 1611 | |
| 1612 | static void |
| 1613 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
| 1614 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1615 | struct drm_device *dev = intel_dp->base.base.dev; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1616 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1617 | bool channel_eq = false; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1618 | int tries, cr_tries; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1619 | u32 reg; |
| 1620 | uint32_t DP = intel_dp->DP; |
| 1621 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1622 | /* channel equalization */ |
| 1623 | tries = 0; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1624 | cr_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1625 | channel_eq = false; |
| 1626 | for (;;) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1627 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1628 | uint32_t signal_levels; |
| 1629 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1630 | if (cr_tries > 5) { |
| 1631 | DRM_ERROR("failed to train DP, aborting\n"); |
| 1632 | intel_dp_link_down(intel_dp); |
| 1633 | break; |
| 1634 | } |
| 1635 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1636 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1637 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1638 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
| 1639 | } else { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1640 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1641 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
| 1642 | } |
| 1643 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1644 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1645 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
| 1646 | else |
| 1647 | reg = DP | DP_LINK_TRAIN_PAT_2; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1648 | |
| 1649 | /* channel eq pattern */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1650 | if (!intel_dp_set_link_train(intel_dp, reg, |
Adam Jackson | 8105585 | 2011-07-21 17:48:37 -0400 | [diff] [blame] | 1651 | DP_TRAINING_PATTERN_2 | |
| 1652 | DP_LINK_SCRAMBLING_DISABLE)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1653 | break; |
| 1654 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1655 | udelay(400); |
| 1656 | if (!intel_dp_get_link_status(intel_dp)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1657 | break; |
Jesse Barnes | 869184a | 2010-10-07 16:01:22 -0700 | [diff] [blame] | 1658 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1659 | /* Make sure clock is still ok */ |
| 1660 | if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
| 1661 | intel_dp_start_link_train(intel_dp); |
| 1662 | cr_tries++; |
| 1663 | continue; |
| 1664 | } |
| 1665 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1666 | if (intel_channel_eq_ok(intel_dp)) { |
| 1667 | channel_eq = true; |
| 1668 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1669 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1670 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1671 | /* Try 5 times, then try clock recovery if that fails */ |
| 1672 | if (tries > 5) { |
| 1673 | intel_dp_link_down(intel_dp); |
| 1674 | intel_dp_start_link_train(intel_dp); |
| 1675 | tries = 0; |
| 1676 | cr_tries++; |
| 1677 | continue; |
| 1678 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1679 | |
| 1680 | /* Compute new intel_dp->train_set as requested by target */ |
| 1681 | intel_get_adjust_train(intel_dp); |
| 1682 | ++tries; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1683 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1684 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1685 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1686 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
| 1687 | else |
| 1688 | reg = DP | DP_LINK_TRAIN_OFF; |
| 1689 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1690 | I915_WRITE(intel_dp->output_reg, reg); |
| 1691 | POSTING_READ(intel_dp->output_reg); |
| 1692 | intel_dp_aux_native_write_1(intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1693 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
| 1694 | } |
| 1695 | |
| 1696 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1697 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1698 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1699 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1700 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1701 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1702 | |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 1703 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
| 1704 | return; |
| 1705 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1706 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1707 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1708 | if (is_edp(intel_dp)) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1709 | DP &= ~DP_PLL_ENABLE; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1710 | I915_WRITE(intel_dp->output_reg, DP); |
| 1711 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1712 | udelay(100); |
| 1713 | } |
| 1714 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1715 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1716 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1717 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1718 | } else { |
| 1719 | DP &= ~DP_LINK_TRAIN_MASK; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1720 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1721 | } |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 1722 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1723 | |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 1724 | msleep(17); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1725 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 1726 | if (is_edp(intel_dp)) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1727 | DP |= DP_LINK_TRAIN_OFF; |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 1728 | |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 1729 | if (!HAS_PCH_CPT(dev) && |
| 1730 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 1731 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
| 1732 | |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 1733 | /* Hardware workaround: leaving our transcoder select |
| 1734 | * set to transcoder B while it's off will prevent the |
| 1735 | * corresponding HDMI output on transcoder A. |
| 1736 | * |
| 1737 | * Combine this with another hardware workaround: |
| 1738 | * transcoder select bit can only be cleared while the |
| 1739 | * port is enabled. |
| 1740 | */ |
| 1741 | DP &= ~DP_PIPEB_SELECT; |
| 1742 | I915_WRITE(intel_dp->output_reg, DP); |
| 1743 | |
| 1744 | /* Changes to enable or select take place the vblank |
| 1745 | * after being written. |
| 1746 | */ |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 1747 | if (crtc == NULL) { |
| 1748 | /* We can arrive here never having been attached |
| 1749 | * to a CRTC, for instance, due to inheriting |
| 1750 | * random state from the BIOS. |
| 1751 | * |
| 1752 | * If the pipe is not running, play safe and |
| 1753 | * wait for the clocks to stabilise before |
| 1754 | * continuing. |
| 1755 | */ |
| 1756 | POSTING_READ(intel_dp->output_reg); |
| 1757 | msleep(50); |
| 1758 | } else |
| 1759 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 1760 | } |
| 1761 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1762 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 1763 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1764 | msleep(intel_dp->panel_power_down_delay); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1765 | } |
| 1766 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 1767 | static bool |
| 1768 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 1769 | { |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 1770 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1771 | sizeof(intel_dp->dpcd)) && |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 1772 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 1773 | return true; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 1774 | } |
| 1775 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 1776 | return false; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 1777 | } |
| 1778 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1779 | /* |
| 1780 | * According to DP spec |
| 1781 | * 5.1.2: |
| 1782 | * 1. Read DPCD |
| 1783 | * 2. Configure link according to Receiver Capabilities |
| 1784 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 1785 | * 4. Check link status on receipt of hot-plug interrupt |
| 1786 | */ |
| 1787 | |
| 1788 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1789 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1790 | { |
Keith Packard | d2b996a | 2011-07-25 22:37:51 -0700 | [diff] [blame] | 1791 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
| 1792 | return; |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 1793 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1794 | if (!intel_dp->base.base.crtc) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1795 | return; |
| 1796 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 1797 | /* Try to read receiver status if the link appears to be up */ |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1798 | if (!intel_dp_get_link_status(intel_dp)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1799 | intel_dp_link_down(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1800 | return; |
| 1801 | } |
| 1802 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 1803 | /* Now read the DPCD to see if it's actually running */ |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 1804 | if (!intel_dp_get_dpcd(intel_dp)) { |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 1805 | intel_dp_link_down(intel_dp); |
| 1806 | return; |
| 1807 | } |
| 1808 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1809 | if (!intel_channel_eq_ok(intel_dp)) { |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 1810 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
| 1811 | drm_get_encoder_name(&intel_dp->base.base)); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1812 | intel_dp_start_link_train(intel_dp); |
| 1813 | intel_dp_complete_link_train(intel_dp); |
| 1814 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1815 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1816 | |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1817 | static enum drm_connector_status |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 1818 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 1819 | { |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 1820 | if (intel_dp_get_dpcd(intel_dp)) |
| 1821 | return connector_status_connected; |
| 1822 | return connector_status_disconnected; |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 1823 | } |
| 1824 | |
| 1825 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1826 | ironlake_dp_detect(struct intel_dp *intel_dp) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1827 | { |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1828 | enum drm_connector_status status; |
| 1829 | |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 1830 | /* Can't disconnect eDP, but you can close the lid... */ |
| 1831 | if (is_edp(intel_dp)) { |
| 1832 | status = intel_panel_detect(intel_dp->base.base.dev); |
| 1833 | if (status == connector_status_unknown) |
| 1834 | status = connector_status_connected; |
| 1835 | return status; |
| 1836 | } |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1837 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 1838 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1839 | } |
| 1840 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1841 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1842 | g4x_dp_detect(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1843 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1844 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1845 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1846 | uint32_t temp, bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1847 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1848 | switch (intel_dp->output_reg) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1849 | case DP_B: |
| 1850 | bit = DPB_HOTPLUG_INT_STATUS; |
| 1851 | break; |
| 1852 | case DP_C: |
| 1853 | bit = DPC_HOTPLUG_INT_STATUS; |
| 1854 | break; |
| 1855 | case DP_D: |
| 1856 | bit = DPD_HOTPLUG_INT_STATUS; |
| 1857 | break; |
| 1858 | default: |
| 1859 | return connector_status_unknown; |
| 1860 | } |
| 1861 | |
| 1862 | temp = I915_READ(PORT_HOTPLUG_STAT); |
| 1863 | |
| 1864 | if ((temp & bit) == 0) |
| 1865 | return connector_status_disconnected; |
| 1866 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 1867 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1868 | } |
| 1869 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 1870 | static struct edid * |
| 1871 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 1872 | { |
| 1873 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 1874 | struct edid *edid; |
| 1875 | |
| 1876 | ironlake_edp_panel_vdd_on(intel_dp); |
| 1877 | edid = drm_get_edid(connector, adapter); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1878 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 1879 | return edid; |
| 1880 | } |
| 1881 | |
| 1882 | static int |
| 1883 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 1884 | { |
| 1885 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 1886 | int ret; |
| 1887 | |
| 1888 | ironlake_edp_panel_vdd_on(intel_dp); |
| 1889 | ret = intel_ddc_get_modes(connector, adapter); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1890 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 1891 | return ret; |
| 1892 | } |
| 1893 | |
| 1894 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1895 | /** |
| 1896 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. |
| 1897 | * |
| 1898 | * \return true if DP port is connected. |
| 1899 | * \return false if DP port is disconnected. |
| 1900 | */ |
| 1901 | static enum drm_connector_status |
| 1902 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 1903 | { |
| 1904 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 1905 | struct drm_device *dev = intel_dp->base.base.dev; |
| 1906 | enum drm_connector_status status; |
| 1907 | struct edid *edid = NULL; |
| 1908 | |
| 1909 | intel_dp->has_audio = false; |
| 1910 | |
| 1911 | if (HAS_PCH_SPLIT(dev)) |
| 1912 | status = ironlake_dp_detect(intel_dp); |
| 1913 | else |
| 1914 | status = g4x_dp_detect(intel_dp); |
Adam Jackson | 1b9be9d | 2011-07-12 17:38:01 -0400 | [diff] [blame] | 1915 | |
Adam Jackson | ac66ae8 | 2011-07-12 17:38:03 -0400 | [diff] [blame] | 1916 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
| 1917 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], |
| 1918 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], |
| 1919 | intel_dp->dpcd[6], intel_dp->dpcd[7]); |
Adam Jackson | 1b9be9d | 2011-07-12 17:38:01 -0400 | [diff] [blame] | 1920 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1921 | if (status != connector_status_connected) |
| 1922 | return status; |
| 1923 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1924 | if (intel_dp->force_audio) { |
| 1925 | intel_dp->has_audio = intel_dp->force_audio > 0; |
| 1926 | } else { |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 1927 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 1928 | if (edid) { |
| 1929 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
| 1930 | connector->display_info.raw_edid = NULL; |
| 1931 | kfree(edid); |
| 1932 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 1933 | } |
| 1934 | |
| 1935 | return connector_status_connected; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1936 | } |
| 1937 | |
| 1938 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 1939 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1940 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1941 | struct drm_device *dev = intel_dp->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1942 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1943 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1944 | |
| 1945 | /* We should parse the EDID data and find out if it has an audio sink |
| 1946 | */ |
| 1947 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 1948 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
Zhao Yakui | b9efc48 | 2010-07-19 09:43:11 +0100 | [diff] [blame] | 1949 | if (ret) { |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 1950 | if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { |
Zhao Yakui | b9efc48 | 2010-07-19 09:43:11 +0100 | [diff] [blame] | 1951 | struct drm_display_mode *newmode; |
| 1952 | list_for_each_entry(newmode, &connector->probed_modes, |
| 1953 | head) { |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 1954 | if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { |
| 1955 | intel_dp->panel_fixed_mode = |
Zhao Yakui | b9efc48 | 2010-07-19 09:43:11 +0100 | [diff] [blame] | 1956 | drm_mode_duplicate(dev, newmode); |
| 1957 | break; |
| 1958 | } |
| 1959 | } |
| 1960 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1961 | return ret; |
Zhao Yakui | b9efc48 | 2010-07-19 09:43:11 +0100 | [diff] [blame] | 1962 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1963 | |
| 1964 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 1965 | if (is_edp(intel_dp)) { |
Keith Packard | 47f0eb2 | 2011-09-19 14:33:26 -0700 | [diff] [blame] | 1966 | /* initialize panel mode from VBT if available for eDP */ |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 1967 | if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { |
| 1968 | intel_dp->panel_fixed_mode = |
Keith Packard | 47f0eb2 | 2011-09-19 14:33:26 -0700 | [diff] [blame] | 1969 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 1970 | if (intel_dp->panel_fixed_mode) { |
| 1971 | intel_dp->panel_fixed_mode->type |= |
Keith Packard | 47f0eb2 | 2011-09-19 14:33:26 -0700 | [diff] [blame] | 1972 | DRM_MODE_TYPE_PREFERRED; |
| 1973 | } |
| 1974 | } |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 1975 | if (intel_dp->panel_fixed_mode) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1976 | struct drm_display_mode *mode; |
Keith Packard | d15456d | 2011-09-18 17:35:47 -0700 | [diff] [blame] | 1977 | mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1978 | drm_mode_probed_add(connector, mode); |
| 1979 | return 1; |
| 1980 | } |
| 1981 | } |
| 1982 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1983 | } |
| 1984 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1985 | static bool |
| 1986 | intel_dp_detect_audio(struct drm_connector *connector) |
| 1987 | { |
| 1988 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 1989 | struct edid *edid; |
| 1990 | bool has_audio = false; |
| 1991 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 1992 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 1993 | if (edid) { |
| 1994 | has_audio = drm_detect_monitor_audio(edid); |
| 1995 | |
| 1996 | connector->display_info.raw_edid = NULL; |
| 1997 | kfree(edid); |
| 1998 | } |
| 1999 | |
| 2000 | return has_audio; |
| 2001 | } |
| 2002 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2003 | static int |
| 2004 | intel_dp_set_property(struct drm_connector *connector, |
| 2005 | struct drm_property *property, |
| 2006 | uint64_t val) |
| 2007 | { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2008 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2009 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 2010 | int ret; |
| 2011 | |
| 2012 | ret = drm_connector_property_set_value(connector, property, val); |
| 2013 | if (ret) |
| 2014 | return ret; |
| 2015 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2016 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2017 | int i = val; |
| 2018 | bool has_audio; |
| 2019 | |
| 2020 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2021 | return 0; |
| 2022 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2023 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2024 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2025 | if (i == 0) |
| 2026 | has_audio = intel_dp_detect_audio(connector); |
| 2027 | else |
| 2028 | has_audio = i > 0; |
| 2029 | |
| 2030 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2031 | return 0; |
| 2032 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2033 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2034 | goto done; |
| 2035 | } |
| 2036 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2037 | if (property == dev_priv->broadcast_rgb_property) { |
| 2038 | if (val == !!intel_dp->color_range) |
| 2039 | return 0; |
| 2040 | |
| 2041 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; |
| 2042 | goto done; |
| 2043 | } |
| 2044 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2045 | return -EINVAL; |
| 2046 | |
| 2047 | done: |
| 2048 | if (intel_dp->base.base.crtc) { |
| 2049 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
| 2050 | drm_crtc_helper_set_mode(crtc, &crtc->mode, |
| 2051 | crtc->x, crtc->y, |
| 2052 | crtc->fb); |
| 2053 | } |
| 2054 | |
| 2055 | return 0; |
| 2056 | } |
| 2057 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2058 | static void |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2059 | intel_dp_destroy(struct drm_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2060 | { |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 2061 | struct drm_device *dev = connector->dev; |
| 2062 | |
| 2063 | if (intel_dpd_is_edp(dev)) |
| 2064 | intel_panel_destroy_backlight(dev); |
| 2065 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2066 | drm_sysfs_connector_remove(connector); |
| 2067 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2068 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2069 | } |
| 2070 | |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2071 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
| 2072 | { |
| 2073 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2074 | |
| 2075 | i2c_del_adapter(&intel_dp->adapter); |
| 2076 | drm_encoder_cleanup(encoder); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2077 | if (is_edp(intel_dp)) { |
| 2078 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 2079 | ironlake_panel_vdd_off_sync(intel_dp); |
| 2080 | } |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2081 | kfree(intel_dp); |
| 2082 | } |
| 2083 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2084 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
| 2085 | .dpms = intel_dp_dpms, |
| 2086 | .mode_fixup = intel_dp_mode_fixup, |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2087 | .prepare = intel_dp_prepare, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2088 | .mode_set = intel_dp_mode_set, |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 2089 | .commit = intel_dp_commit, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2090 | }; |
| 2091 | |
| 2092 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
| 2093 | .dpms = drm_helper_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2094 | .detect = intel_dp_detect, |
| 2095 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2096 | .set_property = intel_dp_set_property, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2097 | .destroy = intel_dp_destroy, |
| 2098 | }; |
| 2099 | |
| 2100 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 2101 | .get_modes = intel_dp_get_modes, |
| 2102 | .mode_valid = intel_dp_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2103 | .best_encoder = intel_best_encoder, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2104 | }; |
| 2105 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2106 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2107 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2108 | }; |
| 2109 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 2110 | static void |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2111 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2112 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2113 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2114 | |
Jesse Barnes | 885a501 | 2011-07-07 11:11:01 -0700 | [diff] [blame] | 2115 | intel_dp_check_link_status(intel_dp); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2116 | } |
| 2117 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2118 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 2119 | int |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2120 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2121 | { |
| 2122 | struct drm_device *dev = crtc->dev; |
| 2123 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 2124 | struct drm_encoder *encoder; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2125 | |
| 2126 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2127 | struct intel_dp *intel_dp; |
| 2128 | |
Dan Carpenter | d8201ab | 2010-05-07 10:39:00 +0200 | [diff] [blame] | 2129 | if (encoder->crtc != crtc) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2130 | continue; |
| 2131 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2132 | intel_dp = enc_to_intel_dp(encoder); |
| 2133 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) |
| 2134 | return intel_dp->output_reg; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2135 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2136 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2137 | return -1; |
| 2138 | } |
| 2139 | |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 2140 | /* check the VBT to see whether the eDP is on DP-D port */ |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 2141 | bool intel_dpd_is_edp(struct drm_device *dev) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 2142 | { |
| 2143 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2144 | struct child_device_config *p_child; |
| 2145 | int i; |
| 2146 | |
| 2147 | if (!dev_priv->child_dev_num) |
| 2148 | return false; |
| 2149 | |
| 2150 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
| 2151 | p_child = dev_priv->child_dev + i; |
| 2152 | |
| 2153 | if (p_child->dvo_port == PORT_IDPD && |
| 2154 | p_child->device_type == DEVICE_TYPE_eDP) |
| 2155 | return true; |
| 2156 | } |
| 2157 | return false; |
| 2158 | } |
| 2159 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2160 | static void |
| 2161 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 2162 | { |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2163 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2164 | intel_attach_broadcast_rgb_property(connector); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2165 | } |
| 2166 | |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2167 | void |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2168 | intel_dp_init(struct drm_device *dev, int output_reg) |
| 2169 | { |
| 2170 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2171 | struct drm_connector *connector; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2172 | struct intel_dp *intel_dp; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2173 | struct intel_encoder *intel_encoder; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2174 | struct intel_connector *intel_connector; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2175 | const char *name = NULL; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2176 | int type; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2177 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2178 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
| 2179 | if (!intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2180 | return; |
| 2181 | |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2182 | intel_dp->output_reg = output_reg; |
Keith Packard | d2b996a | 2011-07-25 22:37:51 -0700 | [diff] [blame] | 2183 | intel_dp->dpms_mode = -1; |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2184 | |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2185 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 2186 | if (!intel_connector) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2187 | kfree(intel_dp); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2188 | return; |
| 2189 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2190 | intel_encoder = &intel_dp->base; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2191 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2192 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2193 | if (intel_dpd_is_edp(dev)) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2194 | intel_dp->is_pch_edp = true; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2195 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 2196 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2197 | type = DRM_MODE_CONNECTOR_eDP; |
| 2198 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 2199 | } else { |
| 2200 | type = DRM_MODE_CONNECTOR_DisplayPort; |
| 2201 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 2202 | } |
| 2203 | |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2204 | connector = &intel_connector->base; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2205 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2206 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 2207 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 2208 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 2209 | |
Zhao Yakui | 652af9d | 2009-12-02 10:03:33 +0800 | [diff] [blame] | 2210 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2211 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
Zhao Yakui | 652af9d | 2009-12-02 10:03:33 +0800 | [diff] [blame] | 2212 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2213 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
Zhao Yakui | 652af9d | 2009-12-02 10:03:33 +0800 | [diff] [blame] | 2214 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2215 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 2216 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2217 | if (is_edp(intel_dp)) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2218 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2219 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
| 2220 | ironlake_panel_vdd_work); |
| 2221 | } |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 2222 | |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 2223 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2224 | connector->interlace_allowed = true; |
| 2225 | connector->doublescan_allowed = 0; |
| 2226 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2227 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2228 | DRM_MODE_ENCODER_TMDS); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2229 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2230 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2231 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2232 | drm_sysfs_connector_add(connector); |
| 2233 | |
| 2234 | /* Set up the DDC bus. */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2235 | switch (output_reg) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2236 | case DP_A: |
| 2237 | name = "DPDDC-A"; |
| 2238 | break; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2239 | case DP_B: |
| 2240 | case PCH_DP_B: |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2241 | dev_priv->hotplug_supported_mask |= |
| 2242 | HDMIB_HOTPLUG_INT_STATUS; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2243 | name = "DPDDC-B"; |
| 2244 | break; |
| 2245 | case DP_C: |
| 2246 | case PCH_DP_C: |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2247 | dev_priv->hotplug_supported_mask |= |
| 2248 | HDMIC_HOTPLUG_INT_STATUS; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2249 | name = "DPDDC-C"; |
| 2250 | break; |
| 2251 | case DP_D: |
| 2252 | case PCH_DP_D: |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2253 | dev_priv->hotplug_supported_mask |= |
| 2254 | HDMID_HOTPLUG_INT_STATUS; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2255 | name = "DPDDC-D"; |
| 2256 | break; |
| 2257 | } |
| 2258 | |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2259 | /* Cache some DPCD data in the eDP case */ |
| 2260 | if (is_edp(intel_dp)) { |
Keith Packard | 59f3e27 | 2011-07-25 20:01:56 -0700 | [diff] [blame] | 2261 | bool ret; |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2262 | struct edp_power_seq cur, vbt; |
| 2263 | u32 pp_on, pp_off, pp_div; |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2264 | |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2265 | pp_on = I915_READ(PCH_PP_ON_DELAYS); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2266 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2267 | pp_div = I915_READ(PCH_PP_DIVISOR); |
| 2268 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2269 | /* Pull timing values out of registers */ |
| 2270 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 2271 | PANEL_POWER_UP_DELAY_SHIFT; |
| 2272 | |
| 2273 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 2274 | PANEL_LIGHT_ON_DELAY_SHIFT; |
| 2275 | |
| 2276 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 2277 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
| 2278 | |
| 2279 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 2280 | PANEL_POWER_DOWN_DELAY_SHIFT; |
| 2281 | |
| 2282 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
| 2283 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
| 2284 | |
| 2285 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 2286 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
| 2287 | |
| 2288 | vbt = dev_priv->edp.pps; |
| 2289 | |
| 2290 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 2291 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
| 2292 | |
| 2293 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) |
| 2294 | |
| 2295 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 2296 | intel_dp->backlight_on_delay = get_delay(t8); |
| 2297 | intel_dp->backlight_off_delay = get_delay(t9); |
| 2298 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 2299 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 2300 | |
| 2301 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 2302 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 2303 | intel_dp->panel_power_cycle_delay); |
| 2304 | |
| 2305 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 2306 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2307 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2308 | intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2309 | |
| 2310 | ironlake_edp_panel_vdd_on(intel_dp); |
Keith Packard | 59f3e27 | 2011-07-25 20:01:56 -0700 | [diff] [blame] | 2311 | ret = intel_dp_get_dpcd(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2312 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Keith Packard | 59f3e27 | 2011-07-25 20:01:56 -0700 | [diff] [blame] | 2313 | if (ret) { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 2314 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 2315 | dev_priv->no_aux_handshake = |
| 2316 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2317 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 2318 | } else { |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2319 | /* if this fails, presume the device is a ghost */ |
Takashi Iwai | 48898b0 | 2011-03-18 09:06:49 +0000 | [diff] [blame] | 2320 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2321 | intel_dp_encoder_destroy(&intel_dp->base.base); |
Takashi Iwai | 48898b0 | 2011-03-18 09:06:49 +0000 | [diff] [blame] | 2322 | intel_dp_destroy(&intel_connector->base); |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2323 | return; |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2324 | } |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2325 | } |
| 2326 | |
Keith Packard | 552fb0b | 2011-09-28 16:31:53 -0700 | [diff] [blame] | 2327 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
| 2328 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2329 | intel_encoder->hot_plug = intel_dp_hot_plug; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2330 | |
Jesse Barnes | 4d92646 | 2010-10-07 16:01:07 -0700 | [diff] [blame] | 2331 | if (is_edp(intel_dp)) { |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 2332 | dev_priv->int_edp_connector = connector; |
| 2333 | intel_panel_setup_backlight(dev); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2334 | } |
| 2335 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2336 | intel_dp_add_properties(intel_dp, connector); |
| 2337 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2338 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 2339 | * 0xd. Failure to do so will result in spurious interrupts being |
| 2340 | * generated on the port when a cable is not attached. |
| 2341 | */ |
| 2342 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 2343 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 2344 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 2345 | } |
| 2346 | } |