Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <dt-bindings/msm/msm-bus-ids.h> |
| 14 | |
| 15 | &soc { |
| 16 | /* QUPv3 South instances */ |
| 17 | qupv3_0: qcom,qupv3_0_geni_se@8c0000 { |
| 18 | compatible = "qcom,qupv3-geni-se"; |
| 19 | reg = <0x8c0000 0x6000>; |
| 20 | qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_1>; |
| 21 | qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| 22 | qcom,iommu-s1-bypass; |
| 23 | |
| 24 | iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { |
| 25 | compatible = "qcom,qupv3-geni-se-cb"; |
| 26 | iommus = <&apps_smmu 0x003 0x0>; |
| 27 | }; |
| 28 | }; |
| 29 | |
| 30 | /* |
| 31 | * HS UART instances. HS UART usecases can be supported on these |
| 32 | * instances only. |
| 33 | */ |
| 34 | qupv3_se6_4uart: qcom,qup_uart@0x898000 { |
Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 35 | compatible = "qcom,msm-geni-serial-hs"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 36 | reg = <0x898000 0x4000>; |
| 37 | reg-names = "se_phys"; |
| 38 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 39 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 40 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 41 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 42 | pinctrl-names = "default", "sleep"; |
Mukesh Kumar Savaliya | fa00673 | 2017-12-14 17:34:14 +0530 | [diff] [blame] | 43 | pinctrl-0 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>, |
| 44 | <&qupv3_se6_tx>; |
| 45 | pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>, |
| 46 | <&qupv3_se6_tx>; |
Maulik Shah | 30ebbde | 2017-06-15 10:02:54 +0530 | [diff] [blame] | 47 | interrupts-extended = <&pdc GIC_SPI 607 0>, |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 48 | <&tlmm 48 0>; |
| 49 | status = "disabled"; |
| 50 | qcom,wakeup-byte = <0xFD>; |
| 51 | qcom,wrapper-core = <&qupv3_0>; |
| 52 | }; |
| 53 | |
| 54 | qupv3_se7_4uart: qcom,qup_uart@0x89c000 { |
Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 55 | compatible = "qcom,msm-geni-serial-hs"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 56 | reg = <0x89c000 0x4000>; |
| 57 | reg-names = "se_phys"; |
| 58 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 59 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 60 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 61 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 62 | pinctrl-names = "default", "sleep"; |
| 63 | pinctrl-0 = <&qupv3_se7_4uart_active>; |
| 64 | pinctrl-1 = <&qupv3_se7_4uart_sleep>; |
Maulik Shah | 30ebbde | 2017-06-15 10:02:54 +0530 | [diff] [blame] | 65 | interrupts-extended = <&pdc GIC_SPI 608 0>, |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 66 | <&tlmm 96 0>; |
| 67 | status = "disabled"; |
| 68 | qcom,wakeup-byte = <0xFD>; |
| 69 | qcom,wrapper-core = <&qupv3_0>; |
| 70 | }; |
| 71 | |
| 72 | /* I2C */ |
| 73 | qupv3_se0_i2c: i2c@880000 { |
| 74 | compatible = "qcom,i2c-geni"; |
| 75 | reg = <0x880000 0x4000>; |
| 76 | interrupts = <GIC_SPI 601 0>; |
| 77 | #address-cells = <1>; |
| 78 | #size-cells = <0>; |
| 79 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 80 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| 81 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 82 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 83 | dmas = <&gpi_dma0 0 0 3 64 0>, |
| 84 | <&gpi_dma0 1 0 3 64 0>; |
| 85 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 86 | pinctrl-names = "default", "sleep"; |
| 87 | pinctrl-0 = <&qupv3_se0_i2c_active>; |
| 88 | pinctrl-1 = <&qupv3_se0_i2c_sleep>; |
| 89 | qcom,wrapper-core = <&qupv3_0>; |
| 90 | status = "disabled"; |
| 91 | }; |
| 92 | |
| 93 | qupv3_se1_i2c: i2c@884000 { |
| 94 | compatible = "qcom,i2c-geni"; |
| 95 | reg = <0x884000 0x4000>; |
| 96 | interrupts = <GIC_SPI 602 0>; |
| 97 | #address-cells = <1>; |
| 98 | #size-cells = <0>; |
| 99 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 100 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| 101 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 102 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 103 | dmas = <&gpi_dma0 0 1 3 64 0>, |
| 104 | <&gpi_dma0 1 1 3 64 0>; |
| 105 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 106 | pinctrl-names = "default", "sleep"; |
| 107 | pinctrl-0 = <&qupv3_se1_i2c_active>; |
| 108 | pinctrl-1 = <&qupv3_se1_i2c_sleep>; |
| 109 | qcom,wrapper-core = <&qupv3_0>; |
| 110 | status = "disabled"; |
| 111 | }; |
| 112 | |
| 113 | qupv3_se2_i2c: i2c@888000 { |
| 114 | compatible = "qcom,i2c-geni"; |
| 115 | reg = <0x888000 0x4000>; |
| 116 | interrupts = <GIC_SPI 603 0>; |
| 117 | #address-cells = <1>; |
| 118 | #size-cells = <0>; |
| 119 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 120 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| 121 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 122 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 123 | dmas = <&gpi_dma0 0 2 3 64 0>, |
| 124 | <&gpi_dma0 1 2 3 64 0>; |
| 125 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 126 | pinctrl-names = "default", "sleep"; |
| 127 | pinctrl-0 = <&qupv3_se2_i2c_active>; |
| 128 | pinctrl-1 = <&qupv3_se2_i2c_sleep>; |
| 129 | qcom,wrapper-core = <&qupv3_0>; |
| 130 | status = "disabled"; |
| 131 | }; |
| 132 | |
| 133 | qupv3_se3_i2c: i2c@88c000 { |
| 134 | compatible = "qcom,i2c-geni"; |
| 135 | reg = <0x88c000 0x4000>; |
| 136 | interrupts = <GIC_SPI 604 0>; |
| 137 | #address-cells = <1>; |
| 138 | #size-cells = <0>; |
| 139 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 140 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| 141 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 142 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 143 | dmas = <&gpi_dma0 0 3 3 64 0>, |
| 144 | <&gpi_dma0 1 3 3 64 0>; |
| 145 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 146 | pinctrl-names = "default", "sleep"; |
| 147 | pinctrl-0 = <&qupv3_se3_i2c_active>; |
| 148 | pinctrl-1 = <&qupv3_se3_i2c_sleep>; |
| 149 | qcom,wrapper-core = <&qupv3_0>; |
| 150 | status = "disabled"; |
| 151 | }; |
| 152 | |
| 153 | qupv3_se4_i2c: i2c@890000 { |
| 154 | compatible = "qcom,i2c-geni"; |
| 155 | reg = <0x890000 0x4000>; |
| 156 | interrupts = <GIC_SPI 605 0>; |
| 157 | #address-cells = <1>; |
| 158 | #size-cells = <0>; |
| 159 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 160 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| 161 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 162 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 163 | dmas = <&gpi_dma0 0 4 3 64 0>, |
| 164 | <&gpi_dma0 1 4 3 64 0>; |
| 165 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 166 | pinctrl-names = "default", "sleep"; |
| 167 | pinctrl-0 = <&qupv3_se4_i2c_active>; |
| 168 | pinctrl-1 = <&qupv3_se4_i2c_sleep>; |
| 169 | qcom,wrapper-core = <&qupv3_0>; |
| 170 | status = "disabled"; |
| 171 | }; |
| 172 | |
| 173 | qupv3_se5_i2c: i2c@894000 { |
| 174 | compatible = "qcom,i2c-geni"; |
| 175 | reg = <0x894000 0x4000>; |
| 176 | interrupts = <GIC_SPI 606 0>; |
| 177 | #address-cells = <1>; |
| 178 | #size-cells = <0>; |
| 179 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 180 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| 181 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 182 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 183 | dmas = <&gpi_dma0 0 5 3 64 0>, |
| 184 | <&gpi_dma0 1 5 3 64 0>; |
| 185 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 186 | pinctrl-names = "default", "sleep"; |
| 187 | pinctrl-0 = <&qupv3_se5_i2c_active>; |
| 188 | pinctrl-1 = <&qupv3_se5_i2c_sleep>; |
| 189 | qcom,wrapper-core = <&qupv3_0>; |
| 190 | status = "disabled"; |
| 191 | }; |
| 192 | |
| 193 | qupv3_se6_i2c: i2c@898000 { |
| 194 | compatible = "qcom,i2c-geni"; |
| 195 | reg = <0x898000 0x4000>; |
| 196 | interrupts = <GIC_SPI 607 0>; |
| 197 | #address-cells = <1>; |
| 198 | #size-cells = <0>; |
| 199 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 200 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 201 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 202 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 203 | dmas = <&gpi_dma0 0 6 3 64 0>, |
| 204 | <&gpi_dma0 1 6 3 64 0>; |
| 205 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 206 | pinctrl-names = "default", "sleep"; |
| 207 | pinctrl-0 = <&qupv3_se6_i2c_active>; |
| 208 | pinctrl-1 = <&qupv3_se6_i2c_sleep>; |
| 209 | qcom,wrapper-core = <&qupv3_0>; |
| 210 | status = "disabled"; |
| 211 | }; |
| 212 | |
| 213 | qupv3_se7_i2c: i2c@89c000 { |
| 214 | compatible = "qcom,i2c-geni"; |
| 215 | reg = <0x89c000 0x4000>; |
| 216 | interrupts = <GIC_SPI 608 0>; |
| 217 | #address-cells = <1>; |
| 218 | #size-cells = <0>; |
| 219 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 220 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 221 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 222 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 223 | dmas = <&gpi_dma0 0 7 3 64 0>, |
| 224 | <&gpi_dma0 1 7 3 64 0>; |
| 225 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 226 | pinctrl-names = "default", "sleep"; |
| 227 | pinctrl-0 = <&qupv3_se7_i2c_active>; |
| 228 | pinctrl-1 = <&qupv3_se7_i2c_sleep>; |
| 229 | qcom,wrapper-core = <&qupv3_0>; |
| 230 | status = "disabled"; |
| 231 | }; |
| 232 | |
| 233 | /* SPI */ |
| 234 | qupv3_se0_spi: spi@880000 { |
| 235 | compatible = "qcom,spi-geni"; |
| 236 | #address-cells = <1>; |
| 237 | #size-cells = <0>; |
| 238 | reg = <0x880000 0x4000>; |
| 239 | reg-names = "se_phys"; |
| 240 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 241 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| 242 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 243 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 244 | pinctrl-names = "default", "sleep"; |
| 245 | pinctrl-0 = <&qupv3_se0_spi_active>; |
| 246 | pinctrl-1 = <&qupv3_se0_spi_sleep>; |
| 247 | interrupts = <GIC_SPI 601 0>; |
| 248 | spi-max-frequency = <50000000>; |
| 249 | qcom,wrapper-core = <&qupv3_0>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 250 | dmas = <&gpi_dma0 0 0 1 64 0>, |
| 251 | <&gpi_dma0 1 0 1 64 0>; |
| 252 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 253 | status = "disabled"; |
| 254 | }; |
| 255 | |
| 256 | qupv3_se1_spi: spi@884000 { |
| 257 | compatible = "qcom,spi-geni"; |
| 258 | #address-cells = <1>; |
| 259 | #size-cells = <0>; |
| 260 | reg = <0x884000 0x4000>; |
| 261 | reg-names = "se_phys"; |
| 262 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 263 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| 264 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 265 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 266 | pinctrl-names = "default", "sleep"; |
| 267 | pinctrl-0 = <&qupv3_se1_spi_active>; |
| 268 | pinctrl-1 = <&qupv3_se1_spi_sleep>; |
| 269 | interrupts = <GIC_SPI 602 0>; |
| 270 | spi-max-frequency = <50000000>; |
| 271 | qcom,wrapper-core = <&qupv3_0>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 272 | dmas = <&gpi_dma0 0 1 1 64 0>, |
| 273 | <&gpi_dma0 1 1 1 64 0>; |
| 274 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 275 | status = "disabled"; |
| 276 | }; |
| 277 | |
| 278 | qupv3_se2_spi: spi@888000 { |
| 279 | compatible = "qcom,spi-geni"; |
| 280 | #address-cells = <1>; |
| 281 | #size-cells = <0>; |
| 282 | reg = <0x888000 0x4000>; |
| 283 | reg-names = "se_phys"; |
| 284 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 285 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| 286 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 287 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 288 | pinctrl-names = "default", "sleep"; |
| 289 | pinctrl-0 = <&qupv3_se2_spi_active>; |
| 290 | pinctrl-1 = <&qupv3_se2_spi_sleep>; |
| 291 | interrupts = <GIC_SPI 603 0>; |
| 292 | spi-max-frequency = <50000000>; |
| 293 | qcom,wrapper-core = <&qupv3_0>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 294 | dmas = <&gpi_dma0 0 2 1 64 0>, |
| 295 | <&gpi_dma0 1 2 1 64 0>; |
| 296 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 297 | status = "disabled"; |
| 298 | }; |
| 299 | |
| 300 | qupv3_se3_spi: spi@88c000 { |
| 301 | compatible = "qcom,spi-geni"; |
| 302 | #address-cells = <1>; |
| 303 | #size-cells = <0>; |
| 304 | reg = <0x88c000 0x4000>; |
| 305 | reg-names = "se_phys"; |
| 306 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 307 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| 308 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 309 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 310 | pinctrl-names = "default", "sleep"; |
| 311 | pinctrl-0 = <&qupv3_se3_spi_active>; |
| 312 | pinctrl-1 = <&qupv3_se3_spi_sleep>; |
| 313 | interrupts = <GIC_SPI 604 0>; |
| 314 | spi-max-frequency = <50000000>; |
| 315 | qcom,wrapper-core = <&qupv3_0>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 316 | dmas = <&gpi_dma0 0 3 1 64 0>, |
| 317 | <&gpi_dma0 1 3 1 64 0>; |
| 318 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 319 | status = "disabled"; |
| 320 | }; |
| 321 | |
| 322 | qupv3_se4_spi: spi@890000 { |
| 323 | compatible = "qcom,spi-geni"; |
| 324 | #address-cells = <1>; |
| 325 | #size-cells = <0>; |
| 326 | reg = <0x890000 0x4000>; |
| 327 | reg-names = "se_phys"; |
| 328 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 329 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| 330 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 331 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 332 | pinctrl-names = "default", "sleep"; |
| 333 | pinctrl-0 = <&qupv3_se4_spi_active>; |
| 334 | pinctrl-1 = <&qupv3_se4_spi_sleep>; |
| 335 | interrupts = <GIC_SPI 605 0>; |
| 336 | spi-max-frequency = <50000000>; |
| 337 | qcom,wrapper-core = <&qupv3_0>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 338 | dmas = <&gpi_dma0 0 4 1 64 0>, |
| 339 | <&gpi_dma0 1 4 1 64 0>; |
| 340 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 341 | status = "disabled"; |
| 342 | }; |
| 343 | |
| 344 | qupv3_se5_spi: spi@894000 { |
| 345 | compatible = "qcom,spi-geni"; |
| 346 | #address-cells = <1>; |
| 347 | #size-cells = <0>; |
| 348 | reg = <0x894000 0x4000>; |
| 349 | reg-names = "se_phys"; |
| 350 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 351 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| 352 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 353 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 354 | pinctrl-names = "default", "sleep"; |
| 355 | pinctrl-0 = <&qupv3_se5_spi_active>; |
| 356 | pinctrl-1 = <&qupv3_se5_spi_sleep>; |
| 357 | interrupts = <GIC_SPI 606 0>; |
| 358 | spi-max-frequency = <50000000>; |
| 359 | qcom,wrapper-core = <&qupv3_0>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 360 | dmas = <&gpi_dma0 0 5 1 64 0>, |
| 361 | <&gpi_dma0 1 5 1 64 0>; |
| 362 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 363 | status = "disabled"; |
| 364 | }; |
| 365 | |
| 366 | qupv3_se6_spi: spi@898000 { |
| 367 | compatible = "qcom,spi-geni"; |
| 368 | #address-cells = <1>; |
| 369 | #size-cells = <0>; |
| 370 | reg = <0x898000 0x4000>; |
| 371 | reg-names = "se_phys"; |
| 372 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 373 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 374 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 375 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 376 | pinctrl-names = "default", "sleep"; |
| 377 | pinctrl-0 = <&qupv3_se6_spi_active>; |
| 378 | pinctrl-1 = <&qupv3_se6_spi_sleep>; |
| 379 | interrupts = <GIC_SPI 607 0>; |
| 380 | spi-max-frequency = <50000000>; |
| 381 | qcom,wrapper-core = <&qupv3_0>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 382 | dmas = <&gpi_dma0 0 6 1 64 0>, |
| 383 | <&gpi_dma0 1 6 1 64 0>; |
| 384 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 385 | status = "disabled"; |
| 386 | }; |
| 387 | |
| 388 | qupv3_se7_spi: spi@89c000 { |
| 389 | compatible = "qcom,spi-geni"; |
| 390 | #address-cells = <1>; |
| 391 | #size-cells = <0>; |
| 392 | reg = <0x89c000 0x4000>; |
| 393 | reg-names = "se_phys"; |
| 394 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 395 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 396 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 397 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 398 | pinctrl-names = "default", "sleep"; |
| 399 | pinctrl-0 = <&qupv3_se7_spi_active>; |
| 400 | pinctrl-1 = <&qupv3_se7_spi_sleep>; |
| 401 | interrupts = <GIC_SPI 608 0>; |
| 402 | spi-max-frequency = <50000000>; |
| 403 | qcom,wrapper-core = <&qupv3_0>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 404 | dmas = <&gpi_dma0 0 7 1 64 0>, |
| 405 | <&gpi_dma0 1 7 1 64 0>; |
| 406 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 407 | status = "disabled"; |
| 408 | }; |
| 409 | |
| 410 | /* QUPv3 North Instances */ |
| 411 | qupv3_1: qcom,qupv3_1_geni_se@ac0000 { |
| 412 | compatible = "qcom,qupv3-geni-se"; |
| 413 | reg = <0xac0000 0x6000>; |
| 414 | qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_2>; |
| 415 | qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| 416 | qcom,iommu-s1-bypass; |
| 417 | |
| 418 | iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { |
| 419 | compatible = "qcom,qupv3-geni-se-cb"; |
| 420 | iommus = <&apps_smmu 0x6c3 0x0>; |
| 421 | }; |
| 422 | }; |
| 423 | |
| 424 | /* 2-wire UART */ |
| 425 | |
| 426 | /* Debug UART Instance for CDP/MTP platform */ |
| 427 | qupv3_se9_2uart: qcom,qup_uart@0xa84000 { |
Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 428 | compatible = "qcom,msm-geni-console"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 429 | reg = <0xa84000 0x4000>; |
| 430 | reg-names = "se_phys"; |
| 431 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 432 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 433 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 434 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 435 | pinctrl-names = "default", "sleep"; |
| 436 | pinctrl-0 = <&qupv3_se9_2uart_active>; |
| 437 | pinctrl-1 = <&qupv3_se9_2uart_sleep>; |
| 438 | interrupts = <GIC_SPI 354 0>; |
| 439 | qcom,wrapper-core = <&qupv3_1>; |
| 440 | status = "disabled"; |
| 441 | }; |
| 442 | |
| 443 | /* Debug UART Instance for RUMI platform */ |
| 444 | qupv3_se10_2uart: qcom,qup_uart@0xa88000 { |
Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 445 | compatible = "qcom,msm-geni-console"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 446 | reg = <0xa88000 0x4000>; |
| 447 | reg-names = "se_phys"; |
| 448 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 449 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 450 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 451 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 452 | pinctrl-names = "default", "sleep"; |
| 453 | pinctrl-0 = <&qupv3_se10_2uart_active>; |
| 454 | pinctrl-1 = <&qupv3_se10_2uart_sleep>; |
| 455 | interrupts = <GIC_SPI 355 0>; |
| 456 | qcom,wrapper-core = <&qupv3_1>; |
| 457 | status = "disabled"; |
| 458 | }; |
| 459 | |
Mukesh Kumar Savaliya | 7b27254 | 2017-07-10 19:35:29 +0530 | [diff] [blame] | 460 | /* Debug UART Instance for CDP/MTP platform on SDM670 */ |
| 461 | qupv3_se12_2uart: qcom,qup_uart@0xa90000 { |
Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 462 | compatible = "qcom,msm-geni-console"; |
Mukesh Kumar Savaliya | 7b27254 | 2017-07-10 19:35:29 +0530 | [diff] [blame] | 463 | reg = <0xa90000 0x4000>; |
| 464 | reg-names = "se_phys"; |
| 465 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 466 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| 467 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 468 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 469 | pinctrl-names = "default", "sleep"; |
| 470 | pinctrl-0 = <&qupv3_se12_2uart_active>; |
| 471 | pinctrl-1 = <&qupv3_se12_2uart_sleep>; |
| 472 | interrupts = <GIC_SPI 357 0>; |
| 473 | qcom,wrapper-core = <&qupv3_1>; |
| 474 | status = "disabled"; |
| 475 | }; |
| 476 | |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 477 | /* I2C */ |
| 478 | qupv3_se8_i2c: i2c@a80000 { |
| 479 | compatible = "qcom,i2c-geni"; |
| 480 | reg = <0xa80000 0x4000>; |
| 481 | interrupts = <GIC_SPI 353 0>; |
| 482 | #address-cells = <1>; |
| 483 | #size-cells = <0>; |
| 484 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 485 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| 486 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 487 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 488 | dmas = <&gpi_dma1 0 0 3 64 0>, |
| 489 | <&gpi_dma1 1 0 3 64 0>; |
| 490 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 491 | pinctrl-names = "default", "sleep"; |
| 492 | pinctrl-0 = <&qupv3_se8_i2c_active>; |
| 493 | pinctrl-1 = <&qupv3_se8_i2c_sleep>; |
| 494 | qcom,wrapper-core = <&qupv3_1>; |
| 495 | status = "disabled"; |
| 496 | }; |
| 497 | |
| 498 | qupv3_se9_i2c: i2c@a84000 { |
| 499 | compatible = "qcom,i2c-geni"; |
| 500 | reg = <0xa84000 0x4000>; |
| 501 | interrupts = <GIC_SPI 354 0>; |
| 502 | #address-cells = <1>; |
| 503 | #size-cells = <0>; |
| 504 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 505 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 506 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 507 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 508 | dmas = <&gpi_dma1 0 1 3 64 0>, |
| 509 | <&gpi_dma1 1 1 3 64 0>; |
| 510 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 511 | pinctrl-names = "default", "sleep"; |
| 512 | pinctrl-0 = <&qupv3_se9_i2c_active>; |
| 513 | pinctrl-1 = <&qupv3_se9_i2c_sleep>; |
| 514 | qcom,wrapper-core = <&qupv3_1>; |
| 515 | status = "disabled"; |
| 516 | }; |
| 517 | |
| 518 | qupv3_se10_i2c: i2c@a88000 { |
| 519 | compatible = "qcom,i2c-geni"; |
| 520 | reg = <0xa88000 0x4000>; |
| 521 | interrupts = <GIC_SPI 355 0>; |
| 522 | #address-cells = <1>; |
| 523 | #size-cells = <0>; |
| 524 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 525 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 526 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 527 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 528 | dmas = <&gpi_dma1 0 2 3 64 0>, |
| 529 | <&gpi_dma1 1 2 3 64 0>; |
| 530 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 531 | pinctrl-names = "default", "sleep"; |
| 532 | pinctrl-0 = <&qupv3_se10_i2c_active>; |
| 533 | pinctrl-1 = <&qupv3_se10_i2c_sleep>; |
| 534 | qcom,wrapper-core = <&qupv3_1>; |
| 535 | status = "disabled"; |
| 536 | }; |
| 537 | |
| 538 | qupv3_se11_i2c: i2c@a8c000 { |
| 539 | compatible = "qcom,i2c-geni"; |
| 540 | reg = <0xa8c000 0x4000>; |
| 541 | interrupts = <GIC_SPI 356 0>; |
| 542 | #address-cells = <1>; |
| 543 | #size-cells = <0>; |
| 544 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 545 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| 546 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 547 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 548 | dmas = <&gpi_dma1 0 3 3 64 0>, |
| 549 | <&gpi_dma1 1 3 3 64 0>; |
| 550 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 551 | pinctrl-names = "default", "sleep"; |
| 552 | pinctrl-0 = <&qupv3_se11_i2c_active>; |
| 553 | pinctrl-1 = <&qupv3_se11_i2c_sleep>; |
| 554 | qcom,wrapper-core = <&qupv3_1>; |
| 555 | status = "disabled"; |
| 556 | }; |
| 557 | |
| 558 | qupv3_se12_i2c: i2c@a90000 { |
| 559 | compatible = "qcom,i2c-geni"; |
| 560 | reg = <0xa90000 0x4000>; |
| 561 | interrupts = <GIC_SPI 357 0>; |
| 562 | #address-cells = <1>; |
| 563 | #size-cells = <0>; |
| 564 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 565 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| 566 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 567 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 568 | dmas = <&gpi_dma1 0 4 3 64 0>, |
| 569 | <&gpi_dma1 1 4 3 64 0>; |
| 570 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 571 | pinctrl-names = "default", "sleep"; |
| 572 | pinctrl-0 = <&qupv3_se12_i2c_active>; |
| 573 | pinctrl-1 = <&qupv3_se12_i2c_sleep>; |
| 574 | qcom,wrapper-core = <&qupv3_1>; |
| 575 | status = "disabled"; |
| 576 | }; |
| 577 | |
| 578 | qupv3_se13_i2c: i2c@a94000 { |
| 579 | compatible = "qcom,i2c-geni"; |
| 580 | reg = <0xa94000 0x4000>; |
| 581 | interrupts = <GIC_SPI 358 0>; |
| 582 | #address-cells = <1>; |
| 583 | #size-cells = <0>; |
| 584 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 585 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| 586 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 587 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 588 | dmas = <&gpi_dma1 0 5 3 64 0>, |
| 589 | <&gpi_dma1 1 5 3 64 0>; |
| 590 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 591 | pinctrl-names = "default", "sleep"; |
| 592 | pinctrl-0 = <&qupv3_se13_i2c_active>; |
| 593 | pinctrl-1 = <&qupv3_se13_i2c_sleep>; |
| 594 | qcom,wrapper-core = <&qupv3_1>; |
| 595 | status = "disabled"; |
| 596 | }; |
| 597 | |
| 598 | qupv3_se14_i2c: i2c@a98000 { |
| 599 | compatible = "qcom,i2c-geni"; |
| 600 | reg = <0xa98000 0x4000>; |
| 601 | interrupts = <GIC_SPI 359 0>; |
| 602 | #address-cells = <1>; |
| 603 | #size-cells = <0>; |
| 604 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 605 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>, |
| 606 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 607 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 608 | dmas = <&gpi_dma1 0 6 3 64 0>, |
| 609 | <&gpi_dma1 1 6 3 64 0>; |
| 610 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 611 | pinctrl-names = "default", "sleep"; |
| 612 | pinctrl-0 = <&qupv3_se14_i2c_active>; |
| 613 | pinctrl-1 = <&qupv3_se14_i2c_sleep>; |
| 614 | qcom,wrapper-core = <&qupv3_1>; |
| 615 | status = "disabled"; |
| 616 | }; |
| 617 | |
| 618 | qupv3_se15_i2c: i2c@a9c000 { |
| 619 | compatible = "qcom,i2c-geni"; |
| 620 | reg = <0xa9c000 0x4000>; |
| 621 | interrupts = <GIC_SPI 360 0>; |
| 622 | #address-cells = <1>; |
| 623 | #size-cells = <0>; |
| 624 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 625 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S7_CLK>, |
| 626 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 627 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Shrey Vijay | bc41274 | 2017-10-31 18:40:36 +0530 | [diff] [blame] | 628 | dmas = <&gpi_dma1 0 7 3 64 0>, |
| 629 | <&gpi_dma1 1 7 3 64 0>; |
| 630 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 631 | pinctrl-names = "default", "sleep"; |
| 632 | pinctrl-0 = <&qupv3_se15_i2c_active>; |
| 633 | pinctrl-1 = <&qupv3_se15_i2c_sleep>; |
| 634 | qcom,wrapper-core = <&qupv3_1>; |
| 635 | status = "disabled"; |
| 636 | }; |
| 637 | |
| 638 | /* SPI */ |
| 639 | qupv3_se8_spi: spi@a80000 { |
| 640 | compatible = "qcom,spi-geni"; |
| 641 | #address-cells = <1>; |
| 642 | #size-cells = <0>; |
| 643 | reg = <0xa80000 0x4000>; |
| 644 | reg-names = "se_phys"; |
| 645 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 646 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| 647 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 648 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 649 | pinctrl-names = "default", "sleep"; |
| 650 | pinctrl-0 = <&qupv3_se8_spi_active>; |
| 651 | pinctrl-1 = <&qupv3_se8_spi_sleep>; |
| 652 | interrupts = <GIC_SPI 353 0>; |
| 653 | spi-max-frequency = <50000000>; |
| 654 | qcom,wrapper-core = <&qupv3_1>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 655 | dmas = <&gpi_dma1 0 0 1 64 0>, |
| 656 | <&gpi_dma1 1 0 1 64 0>; |
| 657 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 658 | status = "disabled"; |
| 659 | }; |
| 660 | |
| 661 | qupv3_se9_spi: spi@a84000 { |
| 662 | compatible = "qcom,spi-geni"; |
| 663 | #address-cells = <1>; |
| 664 | #size-cells = <0>; |
| 665 | reg = <0xa84000 0x4000>; |
| 666 | reg-names = "se_phys"; |
| 667 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 668 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 669 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 670 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 671 | pinctrl-names = "default", "sleep"; |
| 672 | pinctrl-0 = <&qupv3_se9_spi_active>; |
| 673 | pinctrl-1 = <&qupv3_se9_spi_sleep>; |
| 674 | interrupts = <GIC_SPI 354 0>; |
| 675 | spi-max-frequency = <50000000>; |
| 676 | qcom,wrapper-core = <&qupv3_1>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 677 | dmas = <&gpi_dma1 0 1 1 64 0>, |
| 678 | <&gpi_dma1 1 1 1 64 0>; |
| 679 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 680 | status = "disabled"; |
| 681 | }; |
| 682 | |
| 683 | qupv3_se10_spi: spi@a88000 { |
| 684 | compatible = "qcom,spi-geni"; |
| 685 | #address-cells = <1>; |
| 686 | #size-cells = <0>; |
| 687 | reg = <0xa88000 0x4000>; |
| 688 | reg-names = "se_phys"; |
| 689 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 690 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 691 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 692 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 693 | pinctrl-names = "default", "sleep"; |
| 694 | pinctrl-0 = <&qupv3_se10_spi_active>; |
| 695 | pinctrl-1 = <&qupv3_se10_spi_sleep>; |
| 696 | interrupts = <GIC_SPI 355 0>; |
| 697 | spi-max-frequency = <50000000>; |
| 698 | qcom,wrapper-core = <&qupv3_1>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 699 | dmas = <&gpi_dma1 0 2 1 64 0>, |
| 700 | <&gpi_dma1 1 2 1 64 0>; |
| 701 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 702 | status = "disabled"; |
| 703 | }; |
| 704 | |
| 705 | qupv3_se11_spi: spi@a8c000 { |
| 706 | compatible = "qcom,spi-geni"; |
| 707 | #address-cells = <1>; |
| 708 | #size-cells = <0>; |
| 709 | reg = <0xa8c000 0x4000>; |
| 710 | reg-names = "se_phys"; |
| 711 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 712 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| 713 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 714 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 715 | pinctrl-names = "default", "sleep"; |
| 716 | pinctrl-0 = <&qupv3_se11_spi_active>; |
| 717 | pinctrl-1 = <&qupv3_se11_spi_sleep>; |
| 718 | interrupts = <GIC_SPI 356 0>; |
| 719 | spi-max-frequency = <50000000>; |
| 720 | qcom,wrapper-core = <&qupv3_1>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 721 | dmas = <&gpi_dma1 0 3 1 64 0>, |
| 722 | <&gpi_dma1 1 3 1 64 0>; |
| 723 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 724 | status = "disabled"; |
| 725 | }; |
| 726 | |
| 727 | qupv3_se12_spi: spi@a90000 { |
| 728 | compatible = "qcom,spi-geni"; |
| 729 | #address-cells = <1>; |
| 730 | #size-cells = <0>; |
| 731 | reg = <0xa90000 0x4000>; |
| 732 | reg-names = "se_phys"; |
| 733 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 734 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| 735 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 736 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 737 | pinctrl-names = "default", "sleep"; |
| 738 | pinctrl-0 = <&qupv3_se12_spi_active>; |
| 739 | pinctrl-1 = <&qupv3_se12_spi_sleep>; |
| 740 | interrupts = <GIC_SPI 357 0>; |
| 741 | spi-max-frequency = <50000000>; |
| 742 | qcom,wrapper-core = <&qupv3_1>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 743 | dmas = <&gpi_dma1 0 4 1 64 0>, |
| 744 | <&gpi_dma1 1 4 1 64 0>; |
| 745 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 746 | status = "disabled"; |
| 747 | }; |
| 748 | |
| 749 | qupv3_se13_spi: spi@a94000 { |
| 750 | compatible = "qcom,spi-geni"; |
| 751 | #address-cells = <1>; |
| 752 | #size-cells = <0>; |
| 753 | reg = <0xa94000 0x4000>; |
| 754 | reg-names = "se_phys"; |
| 755 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 756 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| 757 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 758 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 759 | pinctrl-names = "default", "sleep"; |
| 760 | pinctrl-0 = <&qupv3_se13_spi_active>; |
| 761 | pinctrl-1 = <&qupv3_se13_spi_sleep>; |
| 762 | interrupts = <GIC_SPI 358 0>; |
| 763 | spi-max-frequency = <50000000>; |
| 764 | qcom,wrapper-core = <&qupv3_1>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 765 | dmas = <&gpi_dma1 0 5 1 64 0>, |
| 766 | <&gpi_dma1 1 5 1 64 0>; |
| 767 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 768 | status = "disabled"; |
| 769 | }; |
| 770 | |
| 771 | qupv3_se14_spi: spi@a98000 { |
| 772 | compatible = "qcom,spi-geni"; |
| 773 | #address-cells = <1>; |
| 774 | #size-cells = <0>; |
| 775 | reg = <0xa98000 0x4000>; |
| 776 | reg-names = "se_phys"; |
| 777 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 778 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>, |
| 779 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 780 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 781 | pinctrl-names = "default", "sleep"; |
| 782 | pinctrl-0 = <&qupv3_se14_spi_active>; |
| 783 | pinctrl-1 = <&qupv3_se14_spi_sleep>; |
| 784 | interrupts = <GIC_SPI 359 0>; |
| 785 | spi-max-frequency = <50000000>; |
| 786 | qcom,wrapper-core = <&qupv3_1>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 787 | dmas = <&gpi_dma1 0 6 1 64 0>, |
| 788 | <&gpi_dma1 1 6 1 64 0>; |
| 789 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 790 | status = "disabled"; |
| 791 | }; |
| 792 | |
| 793 | qupv3_se15_spi: spi@a9c000 { |
| 794 | compatible = "qcom,spi-geni"; |
| 795 | #address-cells = <1>; |
| 796 | #size-cells = <0>; |
| 797 | reg = <0xa9c000 0x4000>; |
| 798 | reg-names = "se_phys"; |
| 799 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 800 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S7_CLK>, |
| 801 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 802 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 803 | pinctrl-names = "default", "sleep"; |
| 804 | pinctrl-0 = <&qupv3_se15_spi_active>; |
| 805 | pinctrl-1 = <&qupv3_se15_spi_sleep>; |
| 806 | interrupts = <GIC_SPI 360 0>; |
| 807 | spi-max-frequency = <50000000>; |
| 808 | qcom,wrapper-core = <&qupv3_1>; |
Alok Chauhan | d9e879b | 2017-12-14 13:55:20 +0530 | [diff] [blame] | 809 | dmas = <&gpi_dma1 0 7 1 64 0>, |
| 810 | <&gpi_dma1 1 7 1 64 0>; |
| 811 | dma-names = "tx", "rx"; |
Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame] | 812 | status = "disabled"; |
| 813 | }; |
| 814 | }; |