blob: 16356ffc86ae9824b3f522e475323a7c87295e3b [file] [log] [blame]
Lennert Buytenhekc4713072006-03-28 21:18:54 +01001/*
2 * arch/arm/mach-ixp23xx/core.c
3 *
4 * Core routines for IXP23xx chips
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
Lennert Buytenhekc4713072006-03-28 21:18:54 +010017#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/bitops.h>
25#include <linux/serial.h>
26#include <linux/serial_8250.h>
27#include <linux/serial_core.h>
28#include <linux/device.h>
29#include <linux/mm.h>
30#include <linux/time.h>
31#include <linux/timex.h>
32
33#include <asm/types.h>
34#include <asm/setup.h>
35#include <asm/memory.h>
36#include <asm/hardware.h>
37#include <asm/mach-types.h>
38#include <asm/irq.h>
39#include <asm/system.h>
40#include <asm/tlbflush.h>
41#include <asm/pgtable.h>
42
43#include <asm/mach/map.h>
44#include <asm/mach/time.h>
45#include <asm/mach/irq.h>
46#include <asm/mach/arch.h>
47
48
49/*************************************************************************
50 * Chip specific mappings shared by all IXP23xx systems
51 *************************************************************************/
52static struct map_desc ixp23xx_io_desc[] __initdata = {
53 { /* XSI-CPP CSRs */
54 .virtual = IXP23XX_XSI2CPP_CSR_VIRT,
55 .pfn = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
56 .length = IXP23XX_XSI2CPP_CSR_SIZE,
57 .type = MT_DEVICE,
58 }, { /* Expansion Bus Config */
59 .virtual = IXP23XX_EXP_CFG_VIRT,
60 .pfn = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
61 .length = IXP23XX_EXP_CFG_SIZE,
62 .type = MT_DEVICE,
63 }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
64 .virtual = IXP23XX_PERIPHERAL_VIRT,
65 .pfn = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
66 .length = IXP23XX_PERIPHERAL_SIZE,
67 .type = MT_DEVICE,
68 }, { /* CAP CSRs */
69 .virtual = IXP23XX_CAP_CSR_VIRT,
70 .pfn = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
71 .length = IXP23XX_CAP_CSR_SIZE,
72 .type = MT_DEVICE,
73 }, { /* MSF CSRs */
74 .virtual = IXP23XX_MSF_CSR_VIRT,
75 .pfn = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
76 .length = IXP23XX_MSF_CSR_SIZE,
77 .type = MT_DEVICE,
78 }, { /* PCI I/O Space */
79 .virtual = IXP23XX_PCI_IO_VIRT,
80 .pfn = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
81 .length = IXP23XX_PCI_IO_SIZE,
82 .type = MT_DEVICE,
83 }, { /* PCI Config Space */
84 .virtual = IXP23XX_PCI_CFG_VIRT,
85 .pfn = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
86 .length = IXP23XX_PCI_CFG_SIZE,
87 .type = MT_DEVICE,
88 }, { /* PCI local CFG CSRs */
89 .virtual = IXP23XX_PCI_CREG_VIRT,
90 .pfn = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
91 .length = IXP23XX_PCI_CREG_SIZE,
92 .type = MT_DEVICE,
93 }, { /* PCI MEM Space */
94 .virtual = IXP23XX_PCI_MEM_VIRT,
95 .pfn = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
96 .length = IXP23XX_PCI_MEM_SIZE,
97 .type = MT_DEVICE,
98 }
99};
100
101void __init ixp23xx_map_io(void)
102{
103 iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
104}
105
106
107/***************************************************************************
108 * IXP23xx Interrupt Handling
109 ***************************************************************************/
110enum ixp23xx_irq_type {
111 IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
112};
113
114static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
115
116static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
117{
118 int line = irq - IRQ_IXP23XX_GPIO6 + 6;
119 u32 int_style;
120 enum ixp23xx_irq_type irq_type;
121 volatile u32 *int_reg;
122
123 /*
124 * Only GPIOs 6-15 are wired to interrupts on IXP23xx
125 */
126 if (line < 6 || line > 15)
127 return -EINVAL;
128
129 switch (type) {
130 case IRQT_BOTHEDGE:
131 int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
132 irq_type = IXP23XX_IRQ_EDGE;
133 break;
134 case IRQT_RISING:
135 int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
136 irq_type = IXP23XX_IRQ_EDGE;
137 break;
138 case IRQT_FALLING:
139 int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
140 irq_type = IXP23XX_IRQ_EDGE;
141 break;
142 case IRQT_HIGH:
143 int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
144 irq_type = IXP23XX_IRQ_LEVEL;
145 break;
146 case IRQT_LOW:
147 int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
148 irq_type = IXP23XX_IRQ_LEVEL;
149 break;
150 default:
151 return -EINVAL;
152 }
153
154 ixp23xx_config_irq(irq, irq_type);
155
156 if (line >= 8) { /* pins 8-15 */
157 line -= 8;
158 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
159 } else { /* pins 0-7 */
160 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
161 }
162
163 /*
164 * Clear pending interrupts
165 */
166 *IXP23XX_GPIO_GPISR = (1 << line);
167
168 /* Clear the style for the appropriate pin */
169 *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
170 (line * IXP23XX_GPIO_STYLE_SIZE));
171
172 /* Set the new style */
173 *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
174
175 return 0;
176}
177
178static void ixp23xx_irq_mask(unsigned int irq)
179{
Lennert Buytenhekec8510f2006-06-02 19:51:51 +0100180 volatile unsigned long *intr_reg;
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100181
Lennert Buytenhekec8510f2006-06-02 19:51:51 +0100182 if (irq >= 56)
183 irq += 8;
184
185 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100186 *intr_reg &= ~(1 << (irq % 32));
187}
188
189static void ixp23xx_irq_ack(unsigned int irq)
190{
191 int line = irq - IRQ_IXP23XX_GPIO6 + 6;
192
193 if ((line < 6) || (line > 15))
194 return;
195
196 *IXP23XX_GPIO_GPISR = (1 << line);
197}
198
199/*
200 * Level triggered interrupts on GPIO lines can only be cleared when the
201 * interrupt condition disappears.
202 */
203static void ixp23xx_irq_level_unmask(unsigned int irq)
204{
Lennert Buytenhekec8510f2006-06-02 19:51:51 +0100205 volatile unsigned long *intr_reg;
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100206
207 ixp23xx_irq_ack(irq);
208
Lennert Buytenhekec8510f2006-06-02 19:51:51 +0100209 if (irq >= 56)
210 irq += 8;
211
212 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100213 *intr_reg |= (1 << (irq % 32));
214}
215
216static void ixp23xx_irq_edge_unmask(unsigned int irq)
217{
Lennert Buytenhekec8510f2006-06-02 19:51:51 +0100218 volatile unsigned long *intr_reg;
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100219
Lennert Buytenhekec8510f2006-06-02 19:51:51 +0100220 if (irq >= 56)
221 irq += 8;
222
223 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100224 *intr_reg |= (1 << (irq % 32));
225}
226
Russell King10dd5ce2006-11-23 11:41:32 +0000227static struct irq_chip ixp23xx_irq_level_chip = {
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100228 .ack = ixp23xx_irq_mask,
229 .mask = ixp23xx_irq_mask,
230 .unmask = ixp23xx_irq_level_unmask,
231 .set_type = ixp23xx_irq_set_type
232};
233
Russell King10dd5ce2006-11-23 11:41:32 +0000234static struct irq_chip ixp23xx_irq_edge_chip = {
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100235 .ack = ixp23xx_irq_ack,
236 .mask = ixp23xx_irq_mask,
237 .unmask = ixp23xx_irq_edge_unmask,
238 .set_type = ixp23xx_irq_set_type
239};
240
241static void ixp23xx_pci_irq_mask(unsigned int irq)
242{
243 *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
244}
245
246static void ixp23xx_pci_irq_unmask(unsigned int irq)
247{
248 *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
249}
250
251/*
252 * TODO: Should this just be done at ASM level?
253 */
Russell King10dd5ce2006-11-23 11:41:32 +0000254static void pci_handler(unsigned int irq, struct irq_desc *desc)
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100255{
256 u32 pci_interrupt;
257 unsigned int irqno;
Russell King10dd5ce2006-11-23 11:41:32 +0000258 struct irq_desc *int_desc;
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100259
260 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
261
262 desc->chip->ack(irq);
263
264 /* See which PCI_INTA, or PCI_INTB interrupted */
265 if (pci_interrupt & (1 << 26)) {
266 irqno = IRQ_IXP23XX_INTB;
267 } else if (pci_interrupt & (1 << 27)) {
268 irqno = IRQ_IXP23XX_INTA;
269 } else {
270 BUG();
271 }
272
273 int_desc = irq_desc + irqno;
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700274 desc_handle_irq(irqno, int_desc);
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100275
276 desc->chip->unmask(irq);
277}
278
Russell King10dd5ce2006-11-23 11:41:32 +0000279static struct irq_chip ixp23xx_pci_irq_chip = {
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100280 .ack = ixp23xx_pci_irq_mask,
281 .mask = ixp23xx_pci_irq_mask,
282 .unmask = ixp23xx_pci_irq_unmask
283};
284
285static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
286{
287 switch (type) {
288 case IXP23XX_IRQ_LEVEL:
289 set_irq_chip(irq, &ixp23xx_irq_level_chip);
Russell King10dd5ce2006-11-23 11:41:32 +0000290 set_irq_handler(irq, handle_level_irq);
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100291 break;
292 case IXP23XX_IRQ_EDGE:
293 set_irq_chip(irq, &ixp23xx_irq_edge_chip);
Russell King10dd5ce2006-11-23 11:41:32 +0000294 set_irq_handler(irq, handle_edge_irq);
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100295 break;
296 }
297 set_irq_flags(irq, IRQF_VALID);
298}
299
300void __init ixp23xx_init_irq(void)
301{
302 int irq;
303
304 /* Route everything to IRQ */
305 *IXP23XX_INTR_SEL1 = 0x0;
306 *IXP23XX_INTR_SEL2 = 0x0;
307 *IXP23XX_INTR_SEL3 = 0x0;
308 *IXP23XX_INTR_SEL4 = 0x0;
309
310 /* Mask all sources */
311 *IXP23XX_INTR_EN1 = 0x0;
312 *IXP23XX_INTR_EN2 = 0x0;
313 *IXP23XX_INTR_EN3 = 0x0;
314 *IXP23XX_INTR_EN4 = 0x0;
315
316 /*
317 * Configure all IRQs for level-sensitive operation
318 */
319 for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
320 ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
321 }
322
323 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
324 set_irq_chip(irq, &ixp23xx_pci_irq_chip);
Russell King10dd5ce2006-11-23 11:41:32 +0000325 set_irq_handler(irq, handle_level_irq);
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100326 set_irq_flags(irq, IRQF_VALID);
327 }
328
329 set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
330}
331
332
333/*************************************************************************
334 * Timer-tick functions for IXP23xx
335 *************************************************************************/
Lennert Buytenhekf869afa2006-06-22 10:30:53 +0100336#define CLOCK_TICKS_PER_USEC (CLOCK_TICK_RATE / USEC_PER_SEC)
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100337
338static unsigned long next_jiffy_time;
339
340static unsigned long
341ixp23xx_gettimeoffset(void)
342{
343 unsigned long elapsed;
344
345 elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
346
347 return elapsed / CLOCK_TICKS_PER_USEC;
348}
349
350static irqreturn_t
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700351ixp23xx_timer_interrupt(int irq, void *dev_id)
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100352{
353 /* Clear Pending Interrupt by writing '1' to it */
354 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
Lennert Buytenhekf869afa2006-06-22 10:30:53 +0100355 while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) {
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700356 timer_tick();
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100357 next_jiffy_time += LATCH;
358 }
359
360 return IRQ_HANDLED;
361}
362
363static struct irqaction ixp23xx_timer_irq = {
364 .name = "IXP23xx Timer Tick",
365 .handler = ixp23xx_timer_interrupt,
Bernhard Walleb30faba2007-05-08 00:35:39 -0700366 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100367};
368
369void __init ixp23xx_init_timer(void)
370{
371 /* Clear Pending Interrupt by writing '1' to it */
372 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
373
374 /* Setup the Timer counter value */
375 *IXP23XX_TIMER1_RELOAD =
376 (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
377
378 *IXP23XX_TIMER_CONT = 0;
379 next_jiffy_time = LATCH;
380
381 /* Connect the interrupt handler and enable the interrupt */
382 setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
383}
384
385struct sys_timer ixp23xx_timer = {
386 .init = ixp23xx_init_timer,
387 .offset = ixp23xx_gettimeoffset,
388};
389
390
391/*************************************************************************
Simon Arlott6cbdc8c2007-05-11 20:40:30 +0100392 * IXP23xx Platform Initialization
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100393 *************************************************************************/
394static struct resource ixp23xx_uart_resources[] = {
395 {
396 .start = IXP23XX_UART1_PHYS,
397 .end = IXP23XX_UART1_PHYS + 0x0fff,
398 .flags = IORESOURCE_MEM
399 }, {
400 .start = IXP23XX_UART2_PHYS,
401 .end = IXP23XX_UART2_PHYS + 0x0fff,
402 .flags = IORESOURCE_MEM
403 }
404};
405
406static struct plat_serial8250_port ixp23xx_uart_data[] = {
407 {
408 .mapbase = IXP23XX_UART1_PHYS,
409 .membase = (char *)(IXP23XX_UART1_VIRT + 3),
410 .irq = IRQ_IXP23XX_UART1,
411 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
412 .iotype = UPIO_MEM,
413 .regshift = 2,
414 .uartclk = IXP23XX_UART_XTAL,
415 }, {
416 .mapbase = IXP23XX_UART2_PHYS,
417 .membase = (char *)(IXP23XX_UART2_VIRT + 3),
418 .irq = IRQ_IXP23XX_UART2,
419 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
420 .iotype = UPIO_MEM,
421 .regshift = 2,
422 .uartclk = IXP23XX_UART_XTAL,
423 },
424 { },
425};
426
427static struct platform_device ixp23xx_uart = {
428 .name = "serial8250",
429 .id = 0,
430 .dev.platform_data = ixp23xx_uart_data,
431 .num_resources = 2,
432 .resource = ixp23xx_uart_resources,
433};
434
435static struct platform_device *ixp23xx_devices[] __initdata = {
436 &ixp23xx_uart,
437};
438
439void __init ixp23xx_sys_init(void)
440{
Lennert Buytenhek8b76a682006-06-22 10:30:56 +0100441 *IXP23XX_EXP_UNIT_FUSE |= 0xf;
Lennert Buytenhekc4713072006-03-28 21:18:54 +0100442 platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
443}