Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
| 4 | Copyright(c) 1999 - 2007 Intel Corporation. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | Linux NICS <linux.nics@intel.com> |
| 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
| 29 | #include <linux/pci.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/sched.h> |
| 32 | |
| 33 | #include "ixgbe_common.h" |
| 34 | #include "ixgbe_phy.h" |
| 35 | |
| 36 | static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw); |
| 37 | |
| 38 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw); |
| 39 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); |
| 40 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); |
| 41 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw); |
| 42 | |
| 43 | static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw); |
| 44 | static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw); |
| 45 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); |
| 46 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr); |
| 47 | |
| 48 | /** |
| 49 | * ixgbe_start_hw - Prepare hardware for TX/RX |
| 50 | * @hw: pointer to hardware structure |
| 51 | * |
| 52 | * Starts the hardware by filling the bus info structure and media type, clears |
| 53 | * all on chip counters, initializes receive address registers, multicast |
| 54 | * table, VLAN filter table, calls routine to set up link and flow control |
| 55 | * settings, and leaves transmit and receive units disabled and uninitialized |
| 56 | **/ |
| 57 | s32 ixgbe_start_hw(struct ixgbe_hw *hw) |
| 58 | { |
| 59 | u32 ctrl_ext; |
| 60 | |
| 61 | /* Set the media type */ |
| 62 | hw->phy.media_type = hw->mac.ops.get_media_type(hw); |
| 63 | |
| 64 | /* Identify the PHY */ |
| 65 | ixgbe_identify_phy(hw); |
| 66 | |
| 67 | /* |
| 68 | * Store MAC address from RAR0, clear receive address registers, and |
| 69 | * clear the multicast table |
| 70 | */ |
| 71 | ixgbe_init_rx_addrs(hw); |
| 72 | |
| 73 | /* Clear the VLAN filter table */ |
| 74 | ixgbe_clear_vfta(hw); |
| 75 | |
| 76 | /* Set up link */ |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 77 | hw->mac.ops.setup_link(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 78 | |
| 79 | /* Clear statistics registers */ |
| 80 | ixgbe_clear_hw_cntrs(hw); |
| 81 | |
| 82 | /* Set No Snoop Disable */ |
| 83 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); |
| 84 | ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; |
| 85 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 86 | IXGBE_WRITE_FLUSH(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 87 | |
| 88 | /* Clear adapter stopped flag */ |
| 89 | hw->adapter_stopped = false; |
| 90 | |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | /** |
| 95 | * ixgbe_init_hw - Generic hardware initialization |
| 96 | * @hw: pointer to hardware structure |
| 97 | * |
| 98 | * Initialize the hardware by reseting the hardware, filling the bus info |
| 99 | * structure and media type, clears all on chip counters, initializes receive |
| 100 | * address registers, multicast table, VLAN filter table, calls routine to set |
| 101 | * up link and flow control settings, and leaves transmit and receive units |
| 102 | * disabled and uninitialized |
| 103 | **/ |
| 104 | s32 ixgbe_init_hw(struct ixgbe_hw *hw) |
| 105 | { |
| 106 | /* Reset the hardware */ |
| 107 | hw->mac.ops.reset(hw); |
| 108 | |
| 109 | /* Start the HW */ |
| 110 | ixgbe_start_hw(hw); |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | |
| 115 | /** |
| 116 | * ixgbe_clear_hw_cntrs - Generic clear hardware counters |
| 117 | * @hw: pointer to hardware structure |
| 118 | * |
| 119 | * Clears all hardware statistics counters by reading them from the hardware |
| 120 | * Statistics counters are clear on read. |
| 121 | **/ |
| 122 | static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) |
| 123 | { |
| 124 | u16 i = 0; |
| 125 | |
| 126 | IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
| 127 | IXGBE_READ_REG(hw, IXGBE_ILLERRC); |
| 128 | IXGBE_READ_REG(hw, IXGBE_ERRBC); |
| 129 | IXGBE_READ_REG(hw, IXGBE_MSPDC); |
| 130 | for (i = 0; i < 8; i++) |
| 131 | IXGBE_READ_REG(hw, IXGBE_MPC(i)); |
| 132 | |
| 133 | IXGBE_READ_REG(hw, IXGBE_MLFC); |
| 134 | IXGBE_READ_REG(hw, IXGBE_MRFC); |
| 135 | IXGBE_READ_REG(hw, IXGBE_RLEC); |
| 136 | IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
| 137 | IXGBE_READ_REG(hw, IXGBE_LXONRXC); |
| 138 | IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
| 139 | IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); |
| 140 | |
| 141 | for (i = 0; i < 8; i++) { |
| 142 | IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
| 143 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); |
| 144 | IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); |
| 145 | IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); |
| 146 | } |
| 147 | |
| 148 | IXGBE_READ_REG(hw, IXGBE_PRC64); |
| 149 | IXGBE_READ_REG(hw, IXGBE_PRC127); |
| 150 | IXGBE_READ_REG(hw, IXGBE_PRC255); |
| 151 | IXGBE_READ_REG(hw, IXGBE_PRC511); |
| 152 | IXGBE_READ_REG(hw, IXGBE_PRC1023); |
| 153 | IXGBE_READ_REG(hw, IXGBE_PRC1522); |
| 154 | IXGBE_READ_REG(hw, IXGBE_GPRC); |
| 155 | IXGBE_READ_REG(hw, IXGBE_BPRC); |
| 156 | IXGBE_READ_REG(hw, IXGBE_MPRC); |
| 157 | IXGBE_READ_REG(hw, IXGBE_GPTC); |
| 158 | IXGBE_READ_REG(hw, IXGBE_GORCL); |
| 159 | IXGBE_READ_REG(hw, IXGBE_GORCH); |
| 160 | IXGBE_READ_REG(hw, IXGBE_GOTCL); |
| 161 | IXGBE_READ_REG(hw, IXGBE_GOTCH); |
| 162 | for (i = 0; i < 8; i++) |
| 163 | IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
| 164 | IXGBE_READ_REG(hw, IXGBE_RUC); |
| 165 | IXGBE_READ_REG(hw, IXGBE_RFC); |
| 166 | IXGBE_READ_REG(hw, IXGBE_ROC); |
| 167 | IXGBE_READ_REG(hw, IXGBE_RJC); |
| 168 | IXGBE_READ_REG(hw, IXGBE_MNGPRC); |
| 169 | IXGBE_READ_REG(hw, IXGBE_MNGPDC); |
| 170 | IXGBE_READ_REG(hw, IXGBE_MNGPTC); |
| 171 | IXGBE_READ_REG(hw, IXGBE_TORL); |
| 172 | IXGBE_READ_REG(hw, IXGBE_TORH); |
| 173 | IXGBE_READ_REG(hw, IXGBE_TPR); |
| 174 | IXGBE_READ_REG(hw, IXGBE_TPT); |
| 175 | IXGBE_READ_REG(hw, IXGBE_PTC64); |
| 176 | IXGBE_READ_REG(hw, IXGBE_PTC127); |
| 177 | IXGBE_READ_REG(hw, IXGBE_PTC255); |
| 178 | IXGBE_READ_REG(hw, IXGBE_PTC511); |
| 179 | IXGBE_READ_REG(hw, IXGBE_PTC1023); |
| 180 | IXGBE_READ_REG(hw, IXGBE_PTC1522); |
| 181 | IXGBE_READ_REG(hw, IXGBE_MPTC); |
| 182 | IXGBE_READ_REG(hw, IXGBE_BPTC); |
| 183 | for (i = 0; i < 16; i++) { |
| 184 | IXGBE_READ_REG(hw, IXGBE_QPRC(i)); |
| 185 | IXGBE_READ_REG(hw, IXGBE_QBRC(i)); |
| 186 | IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
| 187 | IXGBE_READ_REG(hw, IXGBE_QBTC(i)); |
| 188 | } |
| 189 | |
| 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | /** |
| 194 | * ixgbe_get_mac_addr - Generic get MAC address |
| 195 | * @hw: pointer to hardware structure |
| 196 | * @mac_addr: Adapter MAC address |
| 197 | * |
| 198 | * Reads the adapter's MAC address from first Receive Address Register (RAR0) |
| 199 | * A reset of the adapter must be performed prior to calling this function |
| 200 | * in order for the MAC address to have been loaded from the EEPROM into RAR0 |
| 201 | **/ |
| 202 | s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) |
| 203 | { |
| 204 | u32 rar_high; |
| 205 | u32 rar_low; |
| 206 | u16 i; |
| 207 | |
| 208 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); |
| 209 | rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); |
| 210 | |
| 211 | for (i = 0; i < 4; i++) |
| 212 | mac_addr[i] = (u8)(rar_low >> (i*8)); |
| 213 | |
| 214 | for (i = 0; i < 2; i++) |
| 215 | mac_addr[i+4] = (u8)(rar_high >> (i*8)); |
| 216 | |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num) |
| 221 | { |
| 222 | s32 ret_val; |
| 223 | u16 data; |
| 224 | |
| 225 | ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM0_PTR, &data); |
| 226 | if (ret_val) { |
| 227 | hw_dbg(hw, "NVM Read Error\n"); |
| 228 | return ret_val; |
| 229 | } |
| 230 | *part_num = (u32)(data << 16); |
| 231 | |
| 232 | ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM1_PTR, &data); |
| 233 | if (ret_val) { |
| 234 | hw_dbg(hw, "NVM Read Error\n"); |
| 235 | return ret_val; |
| 236 | } |
| 237 | *part_num |= data; |
| 238 | |
| 239 | return 0; |
| 240 | } |
| 241 | |
| 242 | /** |
| 243 | * ixgbe_stop_adapter - Generic stop TX/RX units |
| 244 | * @hw: pointer to hardware structure |
| 245 | * |
| 246 | * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, |
| 247 | * disables transmit and receive units. The adapter_stopped flag is used by |
| 248 | * the shared code and drivers to determine if the adapter is in a stopped |
| 249 | * state and should not touch the hardware. |
| 250 | **/ |
| 251 | s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) |
| 252 | { |
| 253 | u32 number_of_queues; |
| 254 | u32 reg_val; |
| 255 | u16 i; |
| 256 | |
| 257 | /* |
| 258 | * Set the adapter_stopped flag so other driver functions stop touching |
| 259 | * the hardware |
| 260 | */ |
| 261 | hw->adapter_stopped = true; |
| 262 | |
| 263 | /* Disable the receive unit */ |
| 264 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
| 265 | reg_val &= ~(IXGBE_RXCTRL_RXEN); |
| 266 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); |
| 267 | msleep(2); |
| 268 | |
| 269 | /* Clear interrupt mask to stop from interrupts being generated */ |
| 270 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); |
| 271 | |
| 272 | /* Clear any pending interrupts */ |
| 273 | IXGBE_READ_REG(hw, IXGBE_EICR); |
| 274 | |
| 275 | /* Disable the transmit unit. Each queue must be disabled. */ |
| 276 | number_of_queues = hw->mac.num_tx_queues; |
| 277 | for (i = 0; i < number_of_queues; i++) { |
| 278 | reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); |
| 279 | if (reg_val & IXGBE_TXDCTL_ENABLE) { |
| 280 | reg_val &= ~IXGBE_TXDCTL_ENABLE; |
| 281 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); |
| 282 | } |
| 283 | } |
| 284 | |
| 285 | return 0; |
| 286 | } |
| 287 | |
| 288 | /** |
| 289 | * ixgbe_led_on - Turns on the software controllable LEDs. |
| 290 | * @hw: pointer to hardware structure |
| 291 | * @index: led number to turn on |
| 292 | **/ |
| 293 | s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) |
| 294 | { |
| 295 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); |
| 296 | |
| 297 | /* To turn on the LED, set mode to ON. */ |
| 298 | led_reg &= ~IXGBE_LED_MODE_MASK(index); |
| 299 | led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); |
| 300 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 301 | IXGBE_WRITE_FLUSH(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 302 | |
| 303 | return 0; |
| 304 | } |
| 305 | |
| 306 | /** |
| 307 | * ixgbe_led_off - Turns off the software controllable LEDs. |
| 308 | * @hw: pointer to hardware structure |
| 309 | * @index: led number to turn off |
| 310 | **/ |
| 311 | s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) |
| 312 | { |
| 313 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); |
| 314 | |
| 315 | /* To turn off the LED, set mode to OFF. */ |
| 316 | led_reg &= ~IXGBE_LED_MODE_MASK(index); |
| 317 | led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); |
| 318 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 319 | IXGBE_WRITE_FLUSH(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 320 | |
| 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | |
| 325 | /** |
| 326 | * ixgbe_init_eeprom - Initialize EEPROM params |
| 327 | * @hw: pointer to hardware structure |
| 328 | * |
| 329 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the |
| 330 | * ixgbe_hw struct in order to set up EEPROM access. |
| 331 | **/ |
| 332 | s32 ixgbe_init_eeprom(struct ixgbe_hw *hw) |
| 333 | { |
| 334 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; |
| 335 | u32 eec; |
| 336 | u16 eeprom_size; |
| 337 | |
| 338 | if (eeprom->type == ixgbe_eeprom_uninitialized) { |
| 339 | eeprom->type = ixgbe_eeprom_none; |
| 340 | |
| 341 | /* |
| 342 | * Check for EEPROM present first. |
| 343 | * If not present leave as none |
| 344 | */ |
| 345 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); |
| 346 | if (eec & IXGBE_EEC_PRES) { |
| 347 | eeprom->type = ixgbe_eeprom_spi; |
| 348 | |
| 349 | /* |
| 350 | * SPI EEPROM is assumed here. This code would need to |
| 351 | * change if a future EEPROM is not SPI. |
| 352 | */ |
| 353 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> |
| 354 | IXGBE_EEC_SIZE_SHIFT); |
| 355 | eeprom->word_size = 1 << (eeprom_size + |
| 356 | IXGBE_EEPROM_WORD_SIZE_SHIFT); |
| 357 | } |
| 358 | |
| 359 | if (eec & IXGBE_EEC_ADDR_SIZE) |
| 360 | eeprom->address_bits = 16; |
| 361 | else |
| 362 | eeprom->address_bits = 8; |
| 363 | hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: " |
| 364 | "%d\n", eeprom->type, eeprom->word_size, |
| 365 | eeprom->address_bits); |
| 366 | } |
| 367 | |
| 368 | return 0; |
| 369 | } |
| 370 | |
| 371 | /** |
| 372 | * ixgbe_read_eeprom - Read EEPROM word using EERD |
| 373 | * @hw: pointer to hardware structure |
| 374 | * @offset: offset of word in the EEPROM to read |
| 375 | * @data: word read from the EEPROM |
| 376 | * |
| 377 | * Reads a 16 bit word from the EEPROM using the EERD register. |
| 378 | **/ |
| 379 | s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) |
| 380 | { |
| 381 | u32 eerd; |
| 382 | s32 status; |
| 383 | |
| 384 | eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) + |
| 385 | IXGBE_EEPROM_READ_REG_START; |
| 386 | |
| 387 | IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); |
| 388 | status = ixgbe_poll_eeprom_eerd_done(hw); |
| 389 | |
| 390 | if (status == 0) |
| 391 | *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> |
| 392 | IXGBE_EEPROM_READ_REG_DATA); |
| 393 | else |
| 394 | hw_dbg(hw, "Eeprom read timed out\n"); |
| 395 | |
| 396 | return status; |
| 397 | } |
| 398 | |
| 399 | /** |
| 400 | * ixgbe_poll_eeprom_eerd_done - Poll EERD status |
| 401 | * @hw: pointer to hardware structure |
| 402 | * |
| 403 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. |
| 404 | **/ |
| 405 | static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw) |
| 406 | { |
| 407 | u32 i; |
| 408 | u32 reg; |
| 409 | s32 status = IXGBE_ERR_EEPROM; |
| 410 | |
| 411 | for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) { |
| 412 | reg = IXGBE_READ_REG(hw, IXGBE_EERD); |
| 413 | if (reg & IXGBE_EEPROM_READ_REG_DONE) { |
| 414 | status = 0; |
| 415 | break; |
| 416 | } |
| 417 | udelay(5); |
| 418 | } |
| 419 | return status; |
| 420 | } |
| 421 | |
| 422 | /** |
| 423 | * ixgbe_get_eeprom_semaphore - Get hardware semaphore |
| 424 | * @hw: pointer to hardware structure |
| 425 | * |
| 426 | * Sets the hardware semaphores so EEPROM access can occur for bit-bang method |
| 427 | **/ |
| 428 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) |
| 429 | { |
| 430 | s32 status = IXGBE_ERR_EEPROM; |
| 431 | u32 timeout; |
| 432 | u32 i; |
| 433 | u32 swsm; |
| 434 | |
| 435 | /* Set timeout value based on size of EEPROM */ |
| 436 | timeout = hw->eeprom.word_size + 1; |
| 437 | |
| 438 | /* Get SMBI software semaphore between device drivers first */ |
| 439 | for (i = 0; i < timeout; i++) { |
| 440 | /* |
| 441 | * If the SMBI bit is 0 when we read it, then the bit will be |
| 442 | * set and we have the semaphore |
| 443 | */ |
| 444 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
| 445 | if (!(swsm & IXGBE_SWSM_SMBI)) { |
| 446 | status = 0; |
| 447 | break; |
| 448 | } |
| 449 | msleep(1); |
| 450 | } |
| 451 | |
| 452 | /* Now get the semaphore between SW/FW through the SWESMBI bit */ |
| 453 | if (status == 0) { |
| 454 | for (i = 0; i < timeout; i++) { |
| 455 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
| 456 | |
| 457 | /* Set the SW EEPROM semaphore bit to request access */ |
| 458 | swsm |= IXGBE_SWSM_SWESMBI; |
| 459 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); |
| 460 | |
| 461 | /* |
| 462 | * If we set the bit successfully then we got the |
| 463 | * semaphore. |
| 464 | */ |
| 465 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
| 466 | if (swsm & IXGBE_SWSM_SWESMBI) |
| 467 | break; |
| 468 | |
| 469 | udelay(50); |
| 470 | } |
| 471 | |
| 472 | /* |
| 473 | * Release semaphores and return error if SW EEPROM semaphore |
| 474 | * was not granted because we don't have access to the EEPROM |
| 475 | */ |
| 476 | if (i >= timeout) { |
| 477 | hw_dbg(hw, "Driver can't access the Eeprom - Semaphore " |
| 478 | "not granted.\n"); |
| 479 | ixgbe_release_eeprom_semaphore(hw); |
| 480 | status = IXGBE_ERR_EEPROM; |
| 481 | } |
| 482 | } |
| 483 | |
| 484 | return status; |
| 485 | } |
| 486 | |
| 487 | /** |
| 488 | * ixgbe_release_eeprom_semaphore - Release hardware semaphore |
| 489 | * @hw: pointer to hardware structure |
| 490 | * |
| 491 | * This function clears hardware semaphore bits. |
| 492 | **/ |
| 493 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) |
| 494 | { |
| 495 | u32 swsm; |
| 496 | |
| 497 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); |
| 498 | |
| 499 | /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ |
| 500 | swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); |
| 501 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 502 | IXGBE_WRITE_FLUSH(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | /** |
| 506 | * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum |
| 507 | * @hw: pointer to hardware structure |
| 508 | **/ |
| 509 | static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw) |
| 510 | { |
| 511 | u16 i; |
| 512 | u16 j; |
| 513 | u16 checksum = 0; |
| 514 | u16 length = 0; |
| 515 | u16 pointer = 0; |
| 516 | u16 word = 0; |
| 517 | |
| 518 | /* Include 0x0-0x3F in the checksum */ |
| 519 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { |
| 520 | if (ixgbe_read_eeprom(hw, i, &word) != 0) { |
| 521 | hw_dbg(hw, "EEPROM read failed\n"); |
| 522 | break; |
| 523 | } |
| 524 | checksum += word; |
| 525 | } |
| 526 | |
| 527 | /* Include all data from pointers except for the fw pointer */ |
| 528 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { |
| 529 | ixgbe_read_eeprom(hw, i, &pointer); |
| 530 | |
| 531 | /* Make sure the pointer seems valid */ |
| 532 | if (pointer != 0xFFFF && pointer != 0) { |
| 533 | ixgbe_read_eeprom(hw, pointer, &length); |
| 534 | |
| 535 | if (length != 0xFFFF && length != 0) { |
| 536 | for (j = pointer+1; j <= pointer+length; j++) { |
| 537 | ixgbe_read_eeprom(hw, j, &word); |
| 538 | checksum += word; |
| 539 | } |
| 540 | } |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; |
| 545 | |
| 546 | return checksum; |
| 547 | } |
| 548 | |
| 549 | /** |
| 550 | * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum |
| 551 | * @hw: pointer to hardware structure |
| 552 | * @checksum_val: calculated checksum |
| 553 | * |
| 554 | * Performs checksum calculation and validates the EEPROM checksum. If the |
| 555 | * caller does not need checksum_val, the value can be NULL. |
| 556 | **/ |
| 557 | s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) |
| 558 | { |
| 559 | s32 status; |
| 560 | u16 checksum; |
| 561 | u16 read_checksum = 0; |
| 562 | |
| 563 | /* |
| 564 | * Read the first word from the EEPROM. If this times out or fails, do |
| 565 | * not continue or we could be in for a very long wait while every |
| 566 | * EEPROM read fails |
| 567 | */ |
| 568 | status = ixgbe_read_eeprom(hw, 0, &checksum); |
| 569 | |
| 570 | if (status == 0) { |
| 571 | checksum = ixgbe_calc_eeprom_checksum(hw); |
| 572 | |
| 573 | ixgbe_read_eeprom(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); |
| 574 | |
| 575 | /* |
| 576 | * Verify read checksum from EEPROM is the same as |
| 577 | * calculated checksum |
| 578 | */ |
| 579 | if (read_checksum != checksum) |
| 580 | status = IXGBE_ERR_EEPROM_CHECKSUM; |
| 581 | |
| 582 | /* If the user cares, return the calculated checksum */ |
| 583 | if (checksum_val) |
| 584 | *checksum_val = checksum; |
| 585 | } else { |
| 586 | hw_dbg(hw, "EEPROM read failed\n"); |
| 587 | } |
| 588 | |
| 589 | return status; |
| 590 | } |
| 591 | |
| 592 | /** |
| 593 | * ixgbe_validate_mac_addr - Validate MAC address |
| 594 | * @mac_addr: pointer to MAC address. |
| 595 | * |
| 596 | * Tests a MAC address to ensure it is a valid Individual Address |
| 597 | **/ |
| 598 | s32 ixgbe_validate_mac_addr(u8 *mac_addr) |
| 599 | { |
| 600 | s32 status = 0; |
| 601 | |
| 602 | /* Make sure it is not a multicast address */ |
| 603 | if (IXGBE_IS_MULTICAST(mac_addr)) |
| 604 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
| 605 | /* Not a broadcast address */ |
| 606 | else if (IXGBE_IS_BROADCAST(mac_addr)) |
| 607 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
| 608 | /* Reject the zero address */ |
| 609 | else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && |
| 610 | mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) |
| 611 | status = IXGBE_ERR_INVALID_MAC_ADDR; |
| 612 | |
| 613 | return status; |
| 614 | } |
| 615 | |
| 616 | /** |
| 617 | * ixgbe_set_rar - Set RX address register |
| 618 | * @hw: pointer to hardware structure |
| 619 | * @addr: Address to put into receive address register |
| 620 | * @index: Receive address register to write |
| 621 | * @vind: Vind to set RAR to |
| 622 | * @enable_addr: set flag that address is active |
| 623 | * |
| 624 | * Puts an ethernet address into a receive address register. |
| 625 | **/ |
| 626 | s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind, |
| 627 | u32 enable_addr) |
| 628 | { |
| 629 | u32 rar_low, rar_high; |
| 630 | |
| 631 | /* |
| 632 | * HW expects these in little endian so we reverse the byte order from |
| 633 | * network order (big endian) to little endian |
| 634 | */ |
| 635 | rar_low = ((u32)addr[0] | |
| 636 | ((u32)addr[1] << 8) | |
| 637 | ((u32)addr[2] << 16) | |
| 638 | ((u32)addr[3] << 24)); |
| 639 | |
| 640 | rar_high = ((u32)addr[4] | |
| 641 | ((u32)addr[5] << 8) | |
| 642 | ((vind << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK)); |
| 643 | |
| 644 | if (enable_addr != 0) |
| 645 | rar_high |= IXGBE_RAH_AV; |
| 646 | |
| 647 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); |
| 648 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); |
| 649 | |
| 650 | return 0; |
| 651 | } |
| 652 | |
| 653 | /** |
| 654 | * ixgbe_init_rx_addrs - Initializes receive address filters. |
| 655 | * @hw: pointer to hardware structure |
| 656 | * |
| 657 | * Places the MAC address in receive address register 0 and clears the rest |
| 658 | * of the receive addresss registers. Clears the multicast table. Assumes |
| 659 | * the receiver is in reset when the routine is called. |
| 660 | **/ |
| 661 | static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) |
| 662 | { |
| 663 | u32 i; |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 664 | u32 rar_entries = hw->mac.num_rar_entries; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 665 | |
| 666 | /* |
| 667 | * If the current mac address is valid, assume it is a software override |
| 668 | * to the permanent address. |
| 669 | * Otherwise, use the permanent address from the eeprom. |
| 670 | */ |
| 671 | if (ixgbe_validate_mac_addr(hw->mac.addr) == |
| 672 | IXGBE_ERR_INVALID_MAC_ADDR) { |
| 673 | /* Get the MAC address from the RAR0 for later reference */ |
| 674 | ixgbe_get_mac_addr(hw, hw->mac.addr); |
| 675 | |
| 676 | hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ", |
| 677 | hw->mac.addr[0], hw->mac.addr[1], |
| 678 | hw->mac.addr[2]); |
| 679 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
| 680 | hw->mac.addr[4], hw->mac.addr[5]); |
| 681 | } else { |
| 682 | /* Setup the receive address. */ |
| 683 | hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); |
| 684 | hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ", |
| 685 | hw->mac.addr[0], hw->mac.addr[1], |
| 686 | hw->mac.addr[2]); |
| 687 | hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3], |
| 688 | hw->mac.addr[4], hw->mac.addr[5]); |
| 689 | |
| 690 | ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
| 691 | } |
| 692 | |
| 693 | hw->addr_ctrl.rar_used_count = 1; |
| 694 | |
| 695 | /* Zero out the other receive addresses. */ |
| 696 | hw_dbg(hw, "Clearing RAR[1-15]\n"); |
| 697 | for (i = 1; i < rar_entries; i++) { |
| 698 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); |
| 699 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); |
| 700 | } |
| 701 | |
| 702 | /* Clear the MTA */ |
| 703 | hw->addr_ctrl.mc_addr_in_rar_count = 0; |
| 704 | hw->addr_ctrl.mta_in_use = 0; |
| 705 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); |
| 706 | |
| 707 | hw_dbg(hw, " Clearing MTA\n"); |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 708 | for (i = 0; i < hw->mac.mcft_size; i++) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 709 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
| 710 | |
| 711 | return 0; |
| 712 | } |
| 713 | |
| 714 | /** |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 715 | * ixgbe_add_uc_addr - Adds a secondary unicast address. |
| 716 | * @hw: pointer to hardware structure |
| 717 | * @addr: new address |
| 718 | * |
| 719 | * Adds it to unused receive address register or goes into promiscuous mode. |
| 720 | **/ |
| 721 | void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr) |
| 722 | { |
| 723 | u32 rar_entries = hw->mac.num_rar_entries; |
| 724 | u32 rar; |
| 725 | |
| 726 | hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", |
| 727 | addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); |
| 728 | |
| 729 | /* |
| 730 | * Place this address in the RAR if there is room, |
| 731 | * else put the controller into promiscuous mode |
| 732 | */ |
| 733 | if (hw->addr_ctrl.rar_used_count < rar_entries) { |
| 734 | rar = hw->addr_ctrl.rar_used_count - |
| 735 | hw->addr_ctrl.mc_addr_in_rar_count; |
| 736 | ixgbe_set_rar(hw, rar, addr, 0, IXGBE_RAH_AV); |
| 737 | hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar); |
| 738 | hw->addr_ctrl.rar_used_count++; |
| 739 | } else { |
| 740 | hw->addr_ctrl.overflow_promisc++; |
| 741 | } |
| 742 | |
| 743 | hw_dbg(hw, "ixgbe_add_uc_addr Complete\n"); |
| 744 | } |
| 745 | |
| 746 | /** |
| 747 | * ixgbe_update_uc_addr_list - Updates MAC list of secondary addresses |
| 748 | * @hw: pointer to hardware structure |
| 749 | * @addr_list: the list of new addresses |
| 750 | * @addr_count: number of addresses |
| 751 | * @next: iterator function to walk the address list |
| 752 | * |
| 753 | * The given list replaces any existing list. Clears the secondary addrs from |
| 754 | * receive address registers. Uses unused receive address registers for the |
| 755 | * first secondary addresses, and falls back to promiscuous mode as needed. |
| 756 | * |
| 757 | * Drivers using secondary unicast addresses must set user_set_promisc when |
| 758 | * manually putting the device into promiscuous mode. |
| 759 | **/ |
| 760 | s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, |
| 761 | u32 addr_count, ixgbe_mc_addr_itr next) |
| 762 | { |
| 763 | u8 *addr; |
| 764 | u32 i; |
| 765 | u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; |
| 766 | u32 uc_addr_in_use; |
| 767 | u32 fctrl; |
| 768 | u32 vmdq; |
| 769 | |
| 770 | /* |
| 771 | * Clear accounting of old secondary address list, |
| 772 | * don't count RAR[0] |
| 773 | */ |
| 774 | uc_addr_in_use = hw->addr_ctrl.rar_used_count - |
| 775 | hw->addr_ctrl.mc_addr_in_rar_count - 1; |
| 776 | hw->addr_ctrl.rar_used_count -= uc_addr_in_use; |
| 777 | hw->addr_ctrl.overflow_promisc = 0; |
| 778 | |
| 779 | /* Zero out the other receive addresses */ |
| 780 | hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use); |
| 781 | for (i = 1; i <= uc_addr_in_use; i++) { |
| 782 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); |
| 783 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); |
| 784 | } |
| 785 | |
| 786 | /* Add the new addresses */ |
| 787 | for (i = 0; i < addr_count; i++) { |
| 788 | hw_dbg(hw, " Adding the secondary addresses:\n"); |
| 789 | addr = next(hw, &addr_list, &vmdq); |
| 790 | ixgbe_add_uc_addr(hw, addr); |
| 791 | } |
| 792 | |
| 793 | if (hw->addr_ctrl.overflow_promisc) { |
| 794 | /* enable promisc if not already in overflow or set by user */ |
| 795 | if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { |
| 796 | hw_dbg(hw, " Entering address overflow promisc mode\n"); |
| 797 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
| 798 | fctrl |= IXGBE_FCTRL_UPE; |
| 799 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
| 800 | } |
| 801 | } else { |
| 802 | /* only disable if set by overflow, not by user */ |
| 803 | if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { |
| 804 | hw_dbg(hw, " Leaving address overflow promisc mode\n"); |
| 805 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
| 806 | fctrl &= ~IXGBE_FCTRL_UPE; |
| 807 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
| 808 | } |
| 809 | } |
| 810 | |
| 811 | hw_dbg(hw, "ixgbe_update_uc_addr_list Complete\n"); |
| 812 | return 0; |
| 813 | } |
| 814 | |
| 815 | /** |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 816 | * ixgbe_mta_vector - Determines bit-vector in multicast table to set |
| 817 | * @hw: pointer to hardware structure |
| 818 | * @mc_addr: the multicast address |
| 819 | * |
| 820 | * Extracts the 12 bits, from a multicast address, to determine which |
| 821 | * bit-vector to set in the multicast table. The hardware uses 12 bits, from |
| 822 | * incoming rx multicast addresses, to determine the bit-vector to check in |
| 823 | * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set |
| 824 | * by the MO field of the MCSTCTRL. The MO field is set during initalization |
| 825 | * to mc_filter_type. |
| 826 | **/ |
| 827 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) |
| 828 | { |
| 829 | u32 vector = 0; |
| 830 | |
| 831 | switch (hw->mac.mc_filter_type) { |
| 832 | case 0: /* use bits [47:36] of the address */ |
| 833 | vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); |
| 834 | break; |
| 835 | case 1: /* use bits [46:35] of the address */ |
| 836 | vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); |
| 837 | break; |
| 838 | case 2: /* use bits [45:34] of the address */ |
| 839 | vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); |
| 840 | break; |
| 841 | case 3: /* use bits [43:32] of the address */ |
| 842 | vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); |
| 843 | break; |
| 844 | default: /* Invalid mc_filter_type */ |
| 845 | hw_dbg(hw, "MC filter type param set incorrectly\n"); |
| 846 | break; |
| 847 | } |
| 848 | |
| 849 | /* vector can only be 12-bits or boundary will be exceeded */ |
| 850 | vector &= 0xFFF; |
| 851 | return vector; |
| 852 | } |
| 853 | |
| 854 | /** |
| 855 | * ixgbe_set_mta - Set bit-vector in multicast table |
| 856 | * @hw: pointer to hardware structure |
| 857 | * @hash_value: Multicast address hash value |
| 858 | * |
| 859 | * Sets the bit-vector in the multicast table. |
| 860 | **/ |
| 861 | static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) |
| 862 | { |
| 863 | u32 vector; |
| 864 | u32 vector_bit; |
| 865 | u32 vector_reg; |
| 866 | u32 mta_reg; |
| 867 | |
| 868 | hw->addr_ctrl.mta_in_use++; |
| 869 | |
| 870 | vector = ixgbe_mta_vector(hw, mc_addr); |
| 871 | hw_dbg(hw, " bit-vector = 0x%03X\n", vector); |
| 872 | |
| 873 | /* |
| 874 | * The MTA is a register array of 128 32-bit registers. It is treated |
| 875 | * like an array of 4096 bits. We want to set bit |
| 876 | * BitArray[vector_value]. So we figure out what register the bit is |
| 877 | * in, read it, OR in the new bit, then write back the new value. The |
| 878 | * register is determined by the upper 7 bits of the vector value and |
| 879 | * the bit within that register are determined by the lower 5 bits of |
| 880 | * the value. |
| 881 | */ |
| 882 | vector_reg = (vector >> 5) & 0x7F; |
| 883 | vector_bit = vector & 0x1F; |
| 884 | mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); |
| 885 | mta_reg |= (1 << vector_bit); |
| 886 | IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); |
| 887 | } |
| 888 | |
| 889 | /** |
| 890 | * ixgbe_add_mc_addr - Adds a multicast address. |
| 891 | * @hw: pointer to hardware structure |
| 892 | * @mc_addr: new multicast address |
| 893 | * |
| 894 | * Adds it to unused receive address register or to the multicast table. |
| 895 | **/ |
| 896 | static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr) |
| 897 | { |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 898 | u32 rar_entries = hw->mac.num_rar_entries; |
Jesse Brandeburg | ce94bf4 | 2008-09-11 19:55:14 -0700 | [diff] [blame^] | 899 | u32 rar; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 900 | |
| 901 | hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n", |
| 902 | mc_addr[0], mc_addr[1], mc_addr[2], |
| 903 | mc_addr[3], mc_addr[4], mc_addr[5]); |
| 904 | |
| 905 | /* |
| 906 | * Place this multicast address in the RAR if there is room, |
| 907 | * else put it in the MTA |
| 908 | */ |
| 909 | if (hw->addr_ctrl.rar_used_count < rar_entries) { |
Jesse Brandeburg | ce94bf4 | 2008-09-11 19:55:14 -0700 | [diff] [blame^] | 910 | rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1; |
| 911 | ixgbe_set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 912 | hw_dbg(hw, "Added a multicast address to RAR[%d]\n", |
| 913 | hw->addr_ctrl.rar_used_count); |
| 914 | hw->addr_ctrl.rar_used_count++; |
| 915 | hw->addr_ctrl.mc_addr_in_rar_count++; |
| 916 | } else { |
| 917 | ixgbe_set_mta(hw, mc_addr); |
| 918 | } |
| 919 | |
| 920 | hw_dbg(hw, "ixgbe_add_mc_addr Complete\n"); |
| 921 | } |
| 922 | |
| 923 | /** |
| 924 | * ixgbe_update_mc_addr_list - Updates MAC list of multicast addresses |
| 925 | * @hw: pointer to hardware structure |
| 926 | * @mc_addr_list: the list of new multicast addresses |
| 927 | * @mc_addr_count: number of addresses |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 928 | * @next: iterator function to walk the multicast address list |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 929 | * |
| 930 | * The given list replaces any existing list. Clears the MC addrs from receive |
| 931 | * address registers and the multicast table. Uses unsed receive address |
| 932 | * registers for the first multicast addresses, and hashes the rest into the |
| 933 | * multicast table. |
| 934 | **/ |
| 935 | s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 936 | u32 mc_addr_count, ixgbe_mc_addr_itr next) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 937 | { |
| 938 | u32 i; |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 939 | u32 rar_entries = hw->mac.num_rar_entries; |
| 940 | u32 vmdq; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 941 | |
| 942 | /* |
| 943 | * Set the new number of MC addresses that we are being requested to |
| 944 | * use. |
| 945 | */ |
| 946 | hw->addr_ctrl.num_mc_addrs = mc_addr_count; |
| 947 | hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count; |
| 948 | hw->addr_ctrl.mc_addr_in_rar_count = 0; |
| 949 | hw->addr_ctrl.mta_in_use = 0; |
| 950 | |
| 951 | /* Zero out the other receive addresses. */ |
| 952 | hw_dbg(hw, "Clearing RAR[1-15]\n"); |
| 953 | for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) { |
| 954 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); |
| 955 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); |
| 956 | } |
| 957 | |
| 958 | /* Clear the MTA */ |
| 959 | hw_dbg(hw, " Clearing MTA\n"); |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 960 | for (i = 0; i < hw->mac.mcft_size; i++) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 961 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
| 962 | |
| 963 | /* Add the new addresses */ |
| 964 | for (i = 0; i < mc_addr_count; i++) { |
| 965 | hw_dbg(hw, " Adding the multicast addresses:\n"); |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 966 | ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 967 | } |
| 968 | |
| 969 | /* Enable mta */ |
| 970 | if (hw->addr_ctrl.mta_in_use > 0) |
| 971 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, |
| 972 | IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); |
| 973 | |
| 974 | hw_dbg(hw, "ixgbe_update_mc_addr_list Complete\n"); |
| 975 | return 0; |
| 976 | } |
| 977 | |
| 978 | /** |
| 979 | * ixgbe_clear_vfta - Clear VLAN filter table |
| 980 | * @hw: pointer to hardware structure |
| 981 | * |
| 982 | * Clears the VLAN filer table, and the VMDq index associated with the filter |
| 983 | **/ |
| 984 | static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) |
| 985 | { |
| 986 | u32 offset; |
| 987 | u32 vlanbyte; |
| 988 | |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 989 | for (offset = 0; offset < hw->mac.vft_size; offset++) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 990 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); |
| 991 | |
| 992 | for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) |
Christopher Leech | 2c5645c | 2008-08-26 04:27:02 -0700 | [diff] [blame] | 993 | for (offset = 0; offset < hw->mac.vft_size; offset++) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 994 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), |
| 995 | 0); |
| 996 | |
| 997 | return 0; |
| 998 | } |
| 999 | |
| 1000 | /** |
| 1001 | * ixgbe_set_vfta - Set VLAN filter table |
| 1002 | * @hw: pointer to hardware structure |
| 1003 | * @vlan: VLAN id to write to VLAN filter |
| 1004 | * @vind: VMDq output index that maps queue to VLAN id in VFTA |
| 1005 | * @vlan_on: boolean flag to turn on/off VLAN in VFTA |
| 1006 | * |
| 1007 | * Turn on/off specified VLAN in the VLAN filter table. |
| 1008 | **/ |
| 1009 | s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, |
| 1010 | bool vlan_on) |
| 1011 | { |
| 1012 | u32 VftaIndex; |
| 1013 | u32 BitOffset; |
| 1014 | u32 VftaReg; |
| 1015 | u32 VftaByte; |
| 1016 | |
| 1017 | /* Determine 32-bit word position in array */ |
| 1018 | VftaIndex = (vlan >> 5) & 0x7F; /* upper seven bits */ |
| 1019 | |
| 1020 | /* Determine the location of the (VMD) queue index */ |
| 1021 | VftaByte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */ |
| 1022 | BitOffset = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */ |
| 1023 | |
| 1024 | /* Set the nibble for VMD queue index */ |
| 1025 | VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex)); |
| 1026 | VftaReg &= (~(0x0F << BitOffset)); |
| 1027 | VftaReg |= (vind << BitOffset); |
| 1028 | IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg); |
| 1029 | |
| 1030 | /* Determine the location of the bit for this VLAN id */ |
| 1031 | BitOffset = vlan & 0x1F; /* lower five bits */ |
| 1032 | |
| 1033 | VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex)); |
| 1034 | if (vlan_on) |
| 1035 | /* Turn on this VLAN id */ |
| 1036 | VftaReg |= (1 << BitOffset); |
| 1037 | else |
| 1038 | /* Turn off this VLAN id */ |
| 1039 | VftaReg &= ~(1 << BitOffset); |
| 1040 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg); |
| 1041 | |
| 1042 | return 0; |
| 1043 | } |
| 1044 | |
| 1045 | /** |
| 1046 | * ixgbe_setup_fc - Configure flow control settings |
| 1047 | * @hw: pointer to hardware structure |
| 1048 | * @packetbuf_num: packet buffer number (0-7) |
| 1049 | * |
| 1050 | * Configures the flow control settings based on SW configuration. |
| 1051 | * This function is used for 802.3x flow control configuration only. |
| 1052 | **/ |
| 1053 | s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) |
| 1054 | { |
| 1055 | u32 frctl_reg; |
| 1056 | u32 rmcs_reg; |
| 1057 | |
| 1058 | if (packetbuf_num < 0 || packetbuf_num > 7) |
Joe Perches | 8c5863a | 2007-11-19 17:48:23 -0800 | [diff] [blame] | 1059 | hw_dbg(hw, "Invalid packet buffer number [%d], expected range " |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1060 | "is 0-7\n", packetbuf_num); |
| 1061 | |
| 1062 | frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
| 1063 | frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE); |
| 1064 | |
| 1065 | rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS); |
| 1066 | rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X); |
| 1067 | |
| 1068 | /* |
Jesse Brandeburg | 2b9ade9 | 2008-08-26 04:27:10 -0700 | [diff] [blame] | 1069 | * 10 gig parts do not have a word in the EEPROM to determine the |
| 1070 | * default flow control setting, so we explicitly set it to full. |
| 1071 | */ |
| 1072 | if (hw->fc.type == ixgbe_fc_default) |
| 1073 | hw->fc.type = ixgbe_fc_full; |
| 1074 | |
| 1075 | /* |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1076 | * We want to save off the original Flow Control configuration just in |
| 1077 | * case we get disconnected and then reconnected into a different hub |
| 1078 | * or switch with different Flow Control capabilities. |
| 1079 | */ |
| 1080 | hw->fc.type = hw->fc.original_type; |
| 1081 | |
| 1082 | /* |
| 1083 | * The possible values of the "flow_control" parameter are: |
| 1084 | * 0: Flow control is completely disabled |
| 1085 | * 1: Rx flow control is enabled (we can receive pause frames but not |
| 1086 | * send pause frames). |
| 1087 | * 2: Tx flow control is enabled (we can send pause frames but we do not |
| 1088 | * support receiving pause frames) |
| 1089 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
| 1090 | * other: Invalid. |
| 1091 | */ |
| 1092 | switch (hw->fc.type) { |
| 1093 | case ixgbe_fc_none: |
| 1094 | break; |
| 1095 | case ixgbe_fc_rx_pause: |
| 1096 | /* |
| 1097 | * RX Flow control is enabled, |
| 1098 | * and TX Flow control is disabled. |
| 1099 | */ |
| 1100 | frctl_reg |= IXGBE_FCTRL_RFCE; |
| 1101 | break; |
| 1102 | case ixgbe_fc_tx_pause: |
| 1103 | /* |
| 1104 | * TX Flow control is enabled, and RX Flow control is disabled, |
| 1105 | * by a software over-ride. |
| 1106 | */ |
| 1107 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; |
| 1108 | break; |
| 1109 | case ixgbe_fc_full: |
| 1110 | /* |
| 1111 | * Flow control (both RX and TX) is enabled by a software |
| 1112 | * over-ride. |
| 1113 | */ |
| 1114 | frctl_reg |= IXGBE_FCTRL_RFCE; |
| 1115 | rmcs_reg |= IXGBE_RMCS_TFCE_802_3X; |
| 1116 | break; |
| 1117 | default: |
| 1118 | /* We should never get here. The value should be 0-3. */ |
| 1119 | hw_dbg(hw, "Flow control param set incorrectly\n"); |
| 1120 | break; |
| 1121 | } |
| 1122 | |
| 1123 | /* Enable 802.3x based flow control settings. */ |
| 1124 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg); |
| 1125 | IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); |
| 1126 | |
| 1127 | /* |
Jesse Brandeburg | 2b9ade9 | 2008-08-26 04:27:10 -0700 | [diff] [blame] | 1128 | * Check for invalid software configuration, zeros are completely |
| 1129 | * invalid for all parameters used past this point, and if we enable |
| 1130 | * flow control with zero water marks, we blast flow control packets. |
| 1131 | */ |
| 1132 | if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { |
| 1133 | hw_dbg(hw, "Flow control structure initialized incorrectly\n"); |
| 1134 | return IXGBE_ERR_INVALID_LINK_SETTINGS; |
| 1135 | } |
| 1136 | |
| 1137 | /* |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1138 | * We need to set up the Receive Threshold high and low water |
| 1139 | * marks as well as (optionally) enabling the transmission of |
| 1140 | * XON frames. |
| 1141 | */ |
| 1142 | if (hw->fc.type & ixgbe_fc_tx_pause) { |
| 1143 | if (hw->fc.send_xon) { |
| 1144 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), |
| 1145 | (hw->fc.low_water | IXGBE_FCRTL_XONE)); |
| 1146 | } else { |
| 1147 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), |
| 1148 | hw->fc.low_water); |
| 1149 | } |
| 1150 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), |
| 1151 | (hw->fc.high_water)|IXGBE_FCRTH_FCEN); |
| 1152 | } |
| 1153 | |
| 1154 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time); |
| 1155 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); |
| 1156 | |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
| 1160 | /** |
| 1161 | * ixgbe_disable_pcie_master - Disable PCI-express master access |
| 1162 | * @hw: pointer to hardware structure |
| 1163 | * |
| 1164 | * Disables PCI-Express master access and verifies there are no pending |
| 1165 | * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable |
| 1166 | * bit hasn't caused the master requests to be disabled, else 0 |
| 1167 | * is returned signifying master requests disabled. |
| 1168 | **/ |
| 1169 | s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) |
| 1170 | { |
| 1171 | u32 ctrl; |
| 1172 | s32 i; |
| 1173 | s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
| 1174 | |
| 1175 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 1176 | ctrl |= IXGBE_CTRL_GIO_DIS; |
| 1177 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); |
| 1178 | |
| 1179 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { |
| 1180 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) { |
| 1181 | status = 0; |
| 1182 | break; |
| 1183 | } |
| 1184 | udelay(100); |
| 1185 | } |
| 1186 | |
| 1187 | return status; |
| 1188 | } |
| 1189 | |
| 1190 | |
| 1191 | /** |
| 1192 | * ixgbe_acquire_swfw_sync - Aquire SWFW semaphore |
| 1193 | * @hw: pointer to hardware structure |
| 1194 | * @mask: Mask to specify wich semaphore to acquire |
| 1195 | * |
| 1196 | * Aquires the SWFW semaphore throught the GSSR register for the specified |
| 1197 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
| 1198 | **/ |
| 1199 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) |
| 1200 | { |
| 1201 | u32 gssr; |
| 1202 | u32 swmask = mask; |
| 1203 | u32 fwmask = mask << 5; |
| 1204 | s32 timeout = 200; |
| 1205 | |
| 1206 | while (timeout) { |
| 1207 | if (ixgbe_get_eeprom_semaphore(hw)) |
| 1208 | return -IXGBE_ERR_SWFW_SYNC; |
| 1209 | |
| 1210 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); |
| 1211 | if (!(gssr & (fwmask | swmask))) |
| 1212 | break; |
| 1213 | |
| 1214 | /* |
| 1215 | * Firmware currently using resource (fwmask) or other software |
| 1216 | * thread currently using resource (swmask) |
| 1217 | */ |
| 1218 | ixgbe_release_eeprom_semaphore(hw); |
| 1219 | msleep(5); |
| 1220 | timeout--; |
| 1221 | } |
| 1222 | |
| 1223 | if (!timeout) { |
| 1224 | hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n"); |
| 1225 | return -IXGBE_ERR_SWFW_SYNC; |
| 1226 | } |
| 1227 | |
| 1228 | gssr |= swmask; |
| 1229 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); |
| 1230 | |
| 1231 | ixgbe_release_eeprom_semaphore(hw); |
| 1232 | return 0; |
| 1233 | } |
| 1234 | |
| 1235 | /** |
| 1236 | * ixgbe_release_swfw_sync - Release SWFW semaphore |
| 1237 | * @hw: pointer to hardware structure |
| 1238 | * @mask: Mask to specify wich semaphore to release |
| 1239 | * |
| 1240 | * Releases the SWFW semaphore throught the GSSR register for the specified |
| 1241 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
| 1242 | **/ |
| 1243 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) |
| 1244 | { |
| 1245 | u32 gssr; |
| 1246 | u32 swmask = mask; |
| 1247 | |
| 1248 | ixgbe_get_eeprom_semaphore(hw); |
| 1249 | |
| 1250 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); |
| 1251 | gssr &= ~swmask; |
| 1252 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); |
| 1253 | |
| 1254 | ixgbe_release_eeprom_semaphore(hw); |
| 1255 | } |
| 1256 | |
| 1257 | /** |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 1258 | * ixgbe_read_analog_reg8 - Reads 8 bit Atlas analog register |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1259 | * @hw: pointer to hardware structure |
| 1260 | * @reg: analog register to read |
| 1261 | * @val: read value |
| 1262 | * |
| 1263 | * Performs write operation to analog register specified. |
| 1264 | **/ |
| 1265 | s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) |
| 1266 | { |
| 1267 | u32 atlas_ctl; |
| 1268 | |
| 1269 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, |
| 1270 | IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); |
| 1271 | IXGBE_WRITE_FLUSH(hw); |
| 1272 | udelay(10); |
| 1273 | atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); |
| 1274 | *val = (u8)atlas_ctl; |
| 1275 | |
| 1276 | return 0; |
| 1277 | } |
| 1278 | |
| 1279 | /** |
Auke Kok | 3957d63 | 2007-10-31 15:22:10 -0700 | [diff] [blame] | 1280 | * ixgbe_write_analog_reg8 - Writes 8 bit Atlas analog register |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1281 | * @hw: pointer to hardware structure |
| 1282 | * @reg: atlas register to write |
| 1283 | * @val: value to write |
| 1284 | * |
| 1285 | * Performs write operation to Atlas analog register specified. |
| 1286 | **/ |
| 1287 | s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) |
| 1288 | { |
| 1289 | u32 atlas_ctl; |
| 1290 | |
| 1291 | atlas_ctl = (reg << 8) | val; |
| 1292 | IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl); |
| 1293 | IXGBE_WRITE_FLUSH(hw); |
| 1294 | udelay(10); |
| 1295 | |
| 1296 | return 0; |
| 1297 | } |
| 1298 | |