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Sascha Hauera245cce2012-03-15 10:04:37 +01001/*
Axel Lin261995d2012-07-01 08:29:28 +08002 * drivers/pwm/pwm-vt8500.c
Sascha Hauera245cce2012-03-15 10:04:37 +01003 *
Tony Prisk63e1ed22012-10-27 14:49:57 +13004 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
Sascha Hauera245cce2012-03-15 10:04:37 +01006 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/err.h>
22#include <linux/io.h>
23#include <linux/pwm.h>
24#include <linux/delay.h>
Tony Prisk63e1ed22012-10-27 14:49:57 +130025#include <linux/clk.h>
Sascha Hauera245cce2012-03-15 10:04:37 +010026
27#include <asm/div64.h>
28
Tony Prisk63e1ed22012-10-27 14:49:57 +130029#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/of_address.h>
32
33/*
34 * SoC architecture allocates register space for 4 PWMs but only
35 * 2 are currently implemented.
36 */
37#define VT8500_NR_PWMS 2
Sascha Hauera245cce2012-03-15 10:04:37 +010038
Tony Prisk8ab432c2013-01-03 08:44:15 +130039#define REG_CTRL(pwm) (((pwm) << 4) + 0x00)
40#define REG_SCALAR(pwm) (((pwm) << 4) + 0x04)
41#define REG_PERIOD(pwm) (((pwm) << 4) + 0x08)
42#define REG_DUTY(pwm) (((pwm) << 4) + 0x0C)
43#define REG_STATUS 0x40
44
45#define CTRL_ENABLE BIT(0)
46#define CTRL_INVERT BIT(1)
47#define CTRL_AUTOLOAD BIT(2)
48#define CTRL_STOP_IMM BIT(3)
49#define CTRL_LOAD_PRESCALE BIT(4)
50#define CTRL_LOAD_PERIOD BIT(5)
51
52#define STATUS_CTRL_UPDATE BIT(0)
53#define STATUS_SCALAR_UPDATE BIT(1)
54#define STATUS_PERIOD_UPDATE BIT(2)
55#define STATUS_DUTY_UPDATE BIT(3)
56#define STATUS_ALL_UPDATE 0x0F
57
Sascha Hauera245cce2012-03-15 10:04:37 +010058struct vt8500_chip {
59 struct pwm_chip chip;
60 void __iomem *base;
Tony Prisk63e1ed22012-10-27 14:49:57 +130061 struct clk *clk;
Sascha Hauera245cce2012-03-15 10:04:37 +010062};
63
64#define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip)
65
66#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
Tony Prisk8ab432c2013-01-03 08:44:15 +130067static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
Sascha Hauera245cce2012-03-15 10:04:37 +010068{
69 int loops = msecs_to_loops(10);
Tony Prisk8ab432c2013-01-03 08:44:15 +130070 u32 mask = bitmask << (nr << 8);
71
72 while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
Sascha Hauera245cce2012-03-15 10:04:37 +010073 cpu_relax();
74
75 if (unlikely(!loops))
Tony Prisk8ab432c2013-01-03 08:44:15 +130076 dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
77 mask);
Sascha Hauera245cce2012-03-15 10:04:37 +010078}
79
80static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
81 int duty_ns, int period_ns)
82{
83 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
84 unsigned long long c;
85 unsigned long period_cycles, prescale, pv, dc;
Tony Prisk422470a2012-11-20 06:44:46 +130086 int err;
Tony Prisk8ab432c2013-01-03 08:44:15 +130087 u32 val;
Tony Prisk422470a2012-11-20 06:44:46 +130088
89 err = clk_enable(vt8500->clk);
90 if (err < 0) {
91 dev_err(chip->dev, "failed to enable clock\n");
92 return err;
93 }
Sascha Hauera245cce2012-03-15 10:04:37 +010094
Tony Prisk63e1ed22012-10-27 14:49:57 +130095 c = clk_get_rate(vt8500->clk);
Sascha Hauera245cce2012-03-15 10:04:37 +010096 c = c * period_ns;
97 do_div(c, 1000000000);
98 period_cycles = c;
99
100 if (period_cycles < 1)
101 period_cycles = 1;
102 prescale = (period_cycles - 1) / 4096;
103 pv = period_cycles / (prescale + 1) - 1;
104 if (pv > 4095)
105 pv = 4095;
106
Tony Prisk422470a2012-11-20 06:44:46 +1300107 if (prescale > 1023) {
108 clk_disable(vt8500->clk);
Sascha Hauera245cce2012-03-15 10:04:37 +0100109 return -EINVAL;
Tony Prisk422470a2012-11-20 06:44:46 +1300110 }
Sascha Hauera245cce2012-03-15 10:04:37 +0100111
112 c = (unsigned long long)pv * duty_ns;
113 do_div(c, period_ns);
114 dc = c;
115
Tony Prisk8ab432c2013-01-03 08:44:15 +1300116 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
117 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
Sascha Hauera245cce2012-03-15 10:04:37 +0100118
Tony Prisk8ab432c2013-01-03 08:44:15 +1300119 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
120 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
Sascha Hauera245cce2012-03-15 10:04:37 +0100121
Tony Prisk8ab432c2013-01-03 08:44:15 +1300122 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
123 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
124
125 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
126 val |= CTRL_AUTOLOAD;
127 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
128 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
Sascha Hauera245cce2012-03-15 10:04:37 +0100129
Tony Prisk422470a2012-11-20 06:44:46 +1300130 clk_disable(vt8500->clk);
Sascha Hauera245cce2012-03-15 10:04:37 +0100131 return 0;
132}
133
134static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
135{
136 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
Tony Prisk8ab432c2013-01-03 08:44:15 +1300137 int err;
138 u32 val;
Sascha Hauera245cce2012-03-15 10:04:37 +0100139
Tony Prisk63e1ed22012-10-27 14:49:57 +1300140 err = clk_enable(vt8500->clk);
Tony Prisk2f9569f2012-11-20 06:44:45 +1300141 if (err < 0) {
Tony Prisk63e1ed22012-10-27 14:49:57 +1300142 dev_err(chip->dev, "failed to enable clock\n");
143 return err;
Tony Prisk422470a2012-11-20 06:44:46 +1300144 }
Tony Prisk63e1ed22012-10-27 14:49:57 +1300145
Tony Prisk8ab432c2013-01-03 08:44:15 +1300146 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
147 val |= CTRL_ENABLE;
148 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
149 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
150
Sascha Hauera245cce2012-03-15 10:04:37 +0100151 return 0;
152}
153
154static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
155{
156 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
Tony Prisk8ab432c2013-01-03 08:44:15 +1300157 u32 val;
Sascha Hauera245cce2012-03-15 10:04:37 +0100158
Tony Prisk8ab432c2013-01-03 08:44:15 +1300159 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
160 val &= ~CTRL_ENABLE;
161 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
162 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
Tony Prisk63e1ed22012-10-27 14:49:57 +1300163
164 clk_disable(vt8500->clk);
Sascha Hauera245cce2012-03-15 10:04:37 +0100165}
166
Tony Prisk3ccb1c12013-01-03 08:44:16 +1300167static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
168 struct pwm_device *pwm,
169 enum pwm_polarity polarity)
170{
171 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
172 u32 val;
173
174 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
175
176 if (polarity == PWM_POLARITY_INVERSED)
177 val |= CTRL_INVERT;
178 else
179 val &= ~CTRL_INVERT;
180
181 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
182 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
183
184 return 0;
185}
186
Sascha Hauera245cce2012-03-15 10:04:37 +0100187static struct pwm_ops vt8500_pwm_ops = {
188 .enable = vt8500_pwm_enable,
189 .disable = vt8500_pwm_disable,
190 .config = vt8500_pwm_config,
Tony Prisk3ccb1c12013-01-03 08:44:16 +1300191 .set_polarity = vt8500_pwm_set_polarity,
Sascha Hauera245cce2012-03-15 10:04:37 +0100192 .owner = THIS_MODULE,
193};
194
Tony Prisk63e1ed22012-10-27 14:49:57 +1300195static const struct of_device_id vt8500_pwm_dt_ids[] = {
196 { .compatible = "via,vt8500-pwm", },
197 { /* Sentinel */ }
198};
199MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
200
201static int vt8500_pwm_probe(struct platform_device *pdev)
Sascha Hauera245cce2012-03-15 10:04:37 +0100202{
203 struct vt8500_chip *chip;
204 struct resource *r;
Tony Prisk63e1ed22012-10-27 14:49:57 +1300205 struct device_node *np = pdev->dev.of_node;
Sascha Hauera245cce2012-03-15 10:04:37 +0100206 int ret;
207
Tony Prisk63e1ed22012-10-27 14:49:57 +1300208 if (!np) {
209 dev_err(&pdev->dev, "invalid devicetree node\n");
210 return -EINVAL;
211 }
212
Axel Lin261995d2012-07-01 08:29:28 +0800213 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
Sascha Hauera245cce2012-03-15 10:04:37 +0100214 if (chip == NULL) {
215 dev_err(&pdev->dev, "failed to allocate memory\n");
216 return -ENOMEM;
217 }
218
219 chip->chip.dev = &pdev->dev;
220 chip->chip.ops = &vt8500_pwm_ops;
Tony Prisk3ccb1c12013-01-03 08:44:16 +1300221 chip->chip.of_xlate = of_pwm_xlate_with_flags;
222 chip->chip.of_pwm_n_cells = 3;
Sascha Hauera245cce2012-03-15 10:04:37 +0100223 chip->chip.base = -1;
224 chip->chip.npwm = VT8500_NR_PWMS;
225
Tony Prisk63e1ed22012-10-27 14:49:57 +1300226 chip->clk = devm_clk_get(&pdev->dev, NULL);
227 if (IS_ERR(chip->clk)) {
228 dev_err(&pdev->dev, "clock source not specified\n");
229 return PTR_ERR(chip->clk);
230 }
231
Sascha Hauera245cce2012-03-15 10:04:37 +0100232 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
233 if (r == NULL) {
234 dev_err(&pdev->dev, "no memory resource defined\n");
Axel Lin261995d2012-07-01 08:29:28 +0800235 return -ENODEV;
Sascha Hauera245cce2012-03-15 10:04:37 +0100236 }
237
Thierry Reding6d4294d2013-01-21 11:09:16 +0100238 chip->base = devm_ioremap_resource(&pdev->dev, r);
239 if (IS_ERR(chip->base))
240 return PTR_ERR(chip->base);
Sascha Hauera245cce2012-03-15 10:04:37 +0100241
Tony Prisk63e1ed22012-10-27 14:49:57 +1300242 ret = clk_prepare(chip->clk);
243 if (ret < 0) {
244 dev_err(&pdev->dev, "failed to prepare clock\n");
Axel Lin261995d2012-07-01 08:29:28 +0800245 return ret;
Tony Prisk63e1ed22012-10-27 14:49:57 +1300246 }
247
248 ret = pwmchip_add(&chip->chip);
249 if (ret < 0) {
250 dev_err(&pdev->dev, "failed to add PWM chip\n");
251 return ret;
252 }
Sascha Hauera245cce2012-03-15 10:04:37 +0100253
254 platform_set_drvdata(pdev, chip);
255 return ret;
Sascha Hauera245cce2012-03-15 10:04:37 +0100256}
257
Tony Prisk63e1ed22012-10-27 14:49:57 +1300258static int vt8500_pwm_remove(struct platform_device *pdev)
Sascha Hauera245cce2012-03-15 10:04:37 +0100259{
260 struct vt8500_chip *chip;
Sascha Hauera245cce2012-03-15 10:04:37 +0100261
262 chip = platform_get_drvdata(pdev);
263 if (chip == NULL)
264 return -ENODEV;
265
Tony Prisk63e1ed22012-10-27 14:49:57 +1300266 clk_unprepare(chip->clk);
267
Axel Lin261995d2012-07-01 08:29:28 +0800268 return pwmchip_remove(&chip->chip);
Sascha Hauera245cce2012-03-15 10:04:37 +0100269}
270
Tony Prisk63e1ed22012-10-27 14:49:57 +1300271static struct platform_driver vt8500_pwm_driver = {
272 .probe = vt8500_pwm_probe,
273 .remove = vt8500_pwm_remove,
Sascha Hauera245cce2012-03-15 10:04:37 +0100274 .driver = {
275 .name = "vt8500-pwm",
276 .owner = THIS_MODULE,
Tony Prisk63e1ed22012-10-27 14:49:57 +1300277 .of_match_table = vt8500_pwm_dt_ids,
Sascha Hauera245cce2012-03-15 10:04:37 +0100278 },
Sascha Hauera245cce2012-03-15 10:04:37 +0100279};
Tony Prisk63e1ed22012-10-27 14:49:57 +1300280module_platform_driver(vt8500_pwm_driver);
Sascha Hauera245cce2012-03-15 10:04:37 +0100281
Tony Prisk63e1ed22012-10-27 14:49:57 +1300282MODULE_DESCRIPTION("VT8500 PWM Driver");
283MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
284MODULE_LICENSE("GPL v2");