Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel(R) Gigabit Ethernet Linux driver |
Akeem G. Abodunrin | 4b9ea46 | 2013-01-08 18:31:12 +0000 | [diff] [blame] | 4 | Copyright(c) 2007-2013 Intel Corporation. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/if_ether.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/pci.h> |
| 31 | #include <linux/netdevice.h> |
Tobias Klauser | 58d14d4 | 2011-07-03 23:50:15 +0000 | [diff] [blame] | 32 | #include <linux/etherdevice.h> |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 33 | |
| 34 | #include "e1000_mac.h" |
| 35 | |
| 36 | #include "igb.h" |
| 37 | |
| 38 | static s32 igb_set_default_fc(struct e1000_hw *hw); |
| 39 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 40 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 41 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 42 | * igb_get_bus_info_pcie - Get PCIe bus information |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 43 | * @hw: pointer to the HW structure |
| 44 | * |
| 45 | * Determines and stores the system bus information for a particular |
| 46 | * network interface. The following bus information is determined and stored: |
| 47 | * bus speed, bus width, type (PCIe), and PCIe function. |
| 48 | **/ |
| 49 | s32 igb_get_bus_info_pcie(struct e1000_hw *hw) |
| 50 | { |
| 51 | struct e1000_bus_info *bus = &hw->bus; |
| 52 | s32 ret_val; |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 53 | u32 reg; |
| 54 | u16 pcie_link_status; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 55 | |
| 56 | bus->type = e1000_bus_type_pci_express; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 57 | |
| 58 | ret_val = igb_read_pcie_cap_reg(hw, |
Alexander Duyck | ff846f5 | 2010-04-27 01:02:40 +0000 | [diff] [blame] | 59 | PCI_EXP_LNKSTA, |
| 60 | &pcie_link_status); |
| 61 | if (ret_val) { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 62 | bus->width = e1000_bus_width_unknown; |
Alexander Duyck | ff846f5 | 2010-04-27 01:02:40 +0000 | [diff] [blame] | 63 | bus->speed = e1000_bus_speed_unknown; |
| 64 | } else { |
| 65 | switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) { |
| 66 | case PCI_EXP_LNKSTA_CLS_2_5GB: |
| 67 | bus->speed = e1000_bus_speed_2500; |
| 68 | break; |
| 69 | case PCI_EXP_LNKSTA_CLS_5_0GB: |
| 70 | bus->speed = e1000_bus_speed_5000; |
| 71 | break; |
| 72 | default: |
| 73 | bus->speed = e1000_bus_speed_unknown; |
| 74 | break; |
| 75 | } |
| 76 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 77 | bus->width = (enum e1000_bus_width)((pcie_link_status & |
Alexander Duyck | ff846f5 | 2010-04-27 01:02:40 +0000 | [diff] [blame] | 78 | PCI_EXP_LNKSTA_NLW) >> |
| 79 | PCI_EXP_LNKSTA_NLW_SHIFT); |
| 80 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 81 | |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 82 | reg = rd32(E1000_STATUS); |
| 83 | bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 89 | * igb_clear_vfta - Clear VLAN filter table |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 90 | * @hw: pointer to the HW structure |
| 91 | * |
| 92 | * Clears the register array which contains the VLAN filter table by |
| 93 | * setting all the values to 0. |
| 94 | **/ |
| 95 | void igb_clear_vfta(struct e1000_hw *hw) |
| 96 | { |
| 97 | u32 offset; |
| 98 | |
| 99 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
| 100 | array_wr32(E1000_VFTA, offset, 0); |
| 101 | wrfl(); |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 106 | * igb_write_vfta - Write value to VLAN filter table |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 107 | * @hw: pointer to the HW structure |
| 108 | * @offset: register offset in VLAN filter table |
| 109 | * @value: register value written to VLAN filter table |
| 110 | * |
| 111 | * Writes value at the given offset in the register array which stores |
| 112 | * the VLAN filter table. |
| 113 | **/ |
Alexander Duyck | ff6f63d | 2009-04-09 22:49:02 +0000 | [diff] [blame] | 114 | static void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 115 | { |
| 116 | array_wr32(E1000_VFTA, offset, value); |
| 117 | wrfl(); |
| 118 | } |
| 119 | |
Carolyn Wyborny | 1128c75 | 2011-10-14 00:13:49 +0000 | [diff] [blame] | 120 | /* Due to a hw errata, if the host tries to configure the VFTA register |
| 121 | * while performing queries from the BMC or DMA, then the VFTA in some |
| 122 | * cases won't be written. |
| 123 | */ |
| 124 | |
| 125 | /** |
| 126 | * igb_clear_vfta_i350 - Clear VLAN filter table |
| 127 | * @hw: pointer to the HW structure |
| 128 | * |
| 129 | * Clears the register array which contains the VLAN filter table by |
| 130 | * setting all the values to 0. |
| 131 | **/ |
| 132 | void igb_clear_vfta_i350(struct e1000_hw *hw) |
| 133 | { |
| 134 | u32 offset; |
| 135 | int i; |
| 136 | |
| 137 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
| 138 | for (i = 0; i < 10; i++) |
| 139 | array_wr32(E1000_VFTA, offset, 0); |
| 140 | |
| 141 | wrfl(); |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | /** |
| 146 | * igb_write_vfta_i350 - Write value to VLAN filter table |
| 147 | * @hw: pointer to the HW structure |
| 148 | * @offset: register offset in VLAN filter table |
| 149 | * @value: register value written to VLAN filter table |
| 150 | * |
| 151 | * Writes value at the given offset in the register array which stores |
| 152 | * the VLAN filter table. |
| 153 | **/ |
Stephen Hemminger | c50b52a | 2012-01-18 22:13:26 +0000 | [diff] [blame] | 154 | static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) |
Carolyn Wyborny | 1128c75 | 2011-10-14 00:13:49 +0000 | [diff] [blame] | 155 | { |
| 156 | int i; |
| 157 | |
| 158 | for (i = 0; i < 10; i++) |
| 159 | array_wr32(E1000_VFTA, offset, value); |
| 160 | |
| 161 | wrfl(); |
| 162 | } |
| 163 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 164 | /** |
Alexander Duyck | 5ac1665 | 2009-07-23 18:09:12 +0000 | [diff] [blame] | 165 | * igb_init_rx_addrs - Initialize receive address's |
| 166 | * @hw: pointer to the HW structure |
| 167 | * @rar_count: receive address registers |
| 168 | * |
| 169 | * Setups the receive address registers by setting the base receive address |
| 170 | * register to the devices MAC address and clearing all the other receive |
| 171 | * address registers to 0. |
| 172 | **/ |
| 173 | void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) |
| 174 | { |
| 175 | u32 i; |
| 176 | u8 mac_addr[ETH_ALEN] = {0}; |
| 177 | |
| 178 | /* Setup the receive address */ |
| 179 | hw_dbg("Programming MAC Address into RAR[0]\n"); |
| 180 | |
| 181 | hw->mac.ops.rar_set(hw, hw->mac.addr, 0); |
| 182 | |
| 183 | /* Zero out the other (rar_entry_count - 1) receive addresses */ |
| 184 | hw_dbg("Clearing RAR[1-%u]\n", rar_count-1); |
| 185 | for (i = 1; i < rar_count; i++) |
| 186 | hw->mac.ops.rar_set(hw, mac_addr, i); |
| 187 | } |
| 188 | |
| 189 | /** |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 190 | * igb_vfta_set - enable or disable vlan in VLAN filter table |
| 191 | * @hw: pointer to the HW structure |
| 192 | * @vid: VLAN id to add or remove |
| 193 | * @add: if true add filter, if false remove |
| 194 | * |
| 195 | * Sets or clears a bit in the VLAN filter table array based on VLAN id |
| 196 | * and if we are adding or removing the filter |
| 197 | **/ |
Alexander Duyck | cad6d05 | 2009-03-13 20:41:37 +0000 | [diff] [blame] | 198 | s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add) |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 199 | { |
| 200 | u32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; |
Alexander Duyck | 75f4f38 | 2009-03-13 20:41:55 +0000 | [diff] [blame] | 201 | u32 mask = 1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK); |
Carolyn Wyborny | 1128c75 | 2011-10-14 00:13:49 +0000 | [diff] [blame] | 202 | u32 vfta; |
| 203 | struct igb_adapter *adapter = hw->back; |
Alexander Duyck | cad6d05 | 2009-03-13 20:41:37 +0000 | [diff] [blame] | 204 | s32 ret_val = 0; |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 205 | |
Carolyn Wyborny | 1128c75 | 2011-10-14 00:13:49 +0000 | [diff] [blame] | 206 | vfta = adapter->shadow_vfta[index]; |
| 207 | |
Alexander Duyck | cad6d05 | 2009-03-13 20:41:37 +0000 | [diff] [blame] | 208 | /* bit was set/cleared before we started */ |
| 209 | if ((!!(vfta & mask)) == add) { |
| 210 | ret_val = -E1000_ERR_CONFIG; |
| 211 | } else { |
| 212 | if (add) |
| 213 | vfta |= mask; |
| 214 | else |
| 215 | vfta &= ~mask; |
| 216 | } |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame^] | 217 | if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) |
Carolyn Wyborny | 1128c75 | 2011-10-14 00:13:49 +0000 | [diff] [blame] | 218 | igb_write_vfta_i350(hw, index, vfta); |
| 219 | else |
| 220 | igb_write_vfta(hw, index, vfta); |
| 221 | adapter->shadow_vfta[index] = vfta; |
Alexander Duyck | cad6d05 | 2009-03-13 20:41:37 +0000 | [diff] [blame] | 222 | |
| 223 | return ret_val; |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 227 | * igb_check_alt_mac_addr - Check for alternate MAC addr |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 228 | * @hw: pointer to the HW structure |
| 229 | * |
| 230 | * Checks the nvm for an alternate MAC address. An alternate MAC address |
| 231 | * can be setup by pre-boot software and must be treated like a permanent |
| 232 | * address and must override the actual permanent MAC address. If an |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 233 | * alternate MAC address is found it is saved in the hw struct and |
| 234 | * programmed into RAR0 and the function returns success, otherwise the |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 235 | * function returns an error. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 236 | **/ |
| 237 | s32 igb_check_alt_mac_addr(struct e1000_hw *hw) |
| 238 | { |
| 239 | u32 i; |
| 240 | s32 ret_val = 0; |
| 241 | u16 offset, nvm_alt_mac_addr_offset, nvm_data; |
| 242 | u8 alt_mac_addr[ETH_ALEN]; |
| 243 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 244 | /* Alternate MAC address is handled by the option ROM for 82580 |
Carolyn Wyborny | 65189d2 | 2011-10-13 17:28:39 +0000 | [diff] [blame] | 245 | * and newer. SW support not required. |
| 246 | */ |
| 247 | if (hw->mac.type >= e1000_82580) |
| 248 | goto out; |
| 249 | |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 250 | ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 251 | &nvm_alt_mac_addr_offset); |
| 252 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 253 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 254 | goto out; |
| 255 | } |
| 256 | |
Akeem G. Abodunrin | 6538ee6 | 2011-09-02 23:08:55 +0000 | [diff] [blame] | 257 | if ((nvm_alt_mac_addr_offset == 0xFFFF) || |
| 258 | (nvm_alt_mac_addr_offset == 0x0000)) |
Alexander Duyck | 2289663 | 2009-10-05 06:34:25 +0000 | [diff] [blame] | 259 | /* There is no Alternate MAC Address */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 260 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 261 | |
| 262 | if (hw->bus.func == E1000_FUNC_1) |
Alexander Duyck | 2289663 | 2009-10-05 06:34:25 +0000 | [diff] [blame] | 263 | nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; |
Akeem G. Abodunrin | 45b5846 | 2011-09-02 23:09:30 +0000 | [diff] [blame] | 264 | if (hw->bus.func == E1000_FUNC_2) |
| 265 | nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; |
| 266 | |
| 267 | if (hw->bus.func == E1000_FUNC_3) |
| 268 | nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 269 | for (i = 0; i < ETH_ALEN; i += 2) { |
| 270 | offset = nvm_alt_mac_addr_offset + (i >> 1); |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 271 | ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 272 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 273 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 274 | goto out; |
| 275 | } |
| 276 | |
| 277 | alt_mac_addr[i] = (u8)(nvm_data & 0xFF); |
| 278 | alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); |
| 279 | } |
| 280 | |
| 281 | /* if multicast bit is set, the alternate address will not be used */ |
Tobias Klauser | 58d14d4 | 2011-07-03 23:50:15 +0000 | [diff] [blame] | 282 | if (is_multicast_ether_addr(alt_mac_addr)) { |
Alexander Duyck | 2289663 | 2009-10-05 06:34:25 +0000 | [diff] [blame] | 283 | hw_dbg("Ignoring Alternate Mac Address with MC bit set\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 284 | goto out; |
| 285 | } |
| 286 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 287 | /* We have a valid alternate MAC address, and we want to treat it the |
Alexander Duyck | 2289663 | 2009-10-05 06:34:25 +0000 | [diff] [blame] | 288 | * same as the normal permanent MAC address stored by the HW into the |
| 289 | * RAR. Do this by mapping this address into RAR0. |
| 290 | */ |
| 291 | hw->mac.ops.rar_set(hw, alt_mac_addr, 0); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 292 | |
| 293 | out: |
| 294 | return ret_val; |
| 295 | } |
| 296 | |
| 297 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 298 | * igb_rar_set - Set receive address register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 299 | * @hw: pointer to the HW structure |
| 300 | * @addr: pointer to the receive address |
| 301 | * @index: receive address array register |
| 302 | * |
| 303 | * Sets the receive address array register at index to the address passed |
| 304 | * in by addr. |
| 305 | **/ |
| 306 | void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
| 307 | { |
| 308 | u32 rar_low, rar_high; |
| 309 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 310 | /* HW expects these in little endian so we reverse the byte order |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 311 | * from network order (big endian) to little endian |
| 312 | */ |
| 313 | rar_low = ((u32) addr[0] | |
| 314 | ((u32) addr[1] << 8) | |
| 315 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
| 316 | |
| 317 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
| 318 | |
Alexander Duyck | 8675737 | 2009-02-06 23:21:51 +0000 | [diff] [blame] | 319 | /* If MAC address zero, no need to set the AV bit */ |
| 320 | if (rar_low || rar_high) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 321 | rar_high |= E1000_RAH_AV; |
| 322 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 323 | /* Some bridges will combine consecutive 32-bit writes into |
Alexander Duyck | 6deac6f | 2009-10-05 06:36:01 +0000 | [diff] [blame] | 324 | * a single burst write, which will malfunction on some parts. |
| 325 | * The flushes avoid this. |
| 326 | */ |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 327 | wr32(E1000_RAL(index), rar_low); |
Alexander Duyck | 6deac6f | 2009-10-05 06:36:01 +0000 | [diff] [blame] | 328 | wrfl(); |
Alexander Duyck | 5e8427e | 2008-12-10 01:09:53 -0800 | [diff] [blame] | 329 | wr32(E1000_RAH(index), rar_high); |
Alexander Duyck | 6deac6f | 2009-10-05 06:36:01 +0000 | [diff] [blame] | 330 | wrfl(); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 334 | * igb_mta_set - Set multicast filter table address |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 335 | * @hw: pointer to the HW structure |
| 336 | * @hash_value: determines the MTA register and bit to set |
| 337 | * |
| 338 | * The multicast table address is a register array of 32-bit registers. |
| 339 | * The hash_value is used to determine what register the bit is in, the |
| 340 | * current value is read, the new bit is OR'd in and the new value is |
| 341 | * written back into the register. |
| 342 | **/ |
Alexander Duyck | 549bdd8 | 2008-08-04 15:00:06 -0700 | [diff] [blame] | 343 | void igb_mta_set(struct e1000_hw *hw, u32 hash_value) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 344 | { |
| 345 | u32 hash_bit, hash_reg, mta; |
| 346 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 347 | /* The MTA is a register array of 32-bit registers. It is |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 348 | * treated like an array of (32*mta_reg_count) bits. We want to |
| 349 | * set bit BitArray[hash_value]. So we figure out what register |
| 350 | * the bit is in, read it, OR in the new bit, then write |
| 351 | * back the new value. The (hw->mac.mta_reg_count - 1) serves as a |
| 352 | * mask to bits 31:5 of the hash value which gives us the |
| 353 | * register we're modifying. The hash bit within that register |
| 354 | * is determined by the lower 5 bits of the hash value. |
| 355 | */ |
| 356 | hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); |
| 357 | hash_bit = hash_value & 0x1F; |
| 358 | |
| 359 | mta = array_rd32(E1000_MTA, hash_reg); |
| 360 | |
| 361 | mta |= (1 << hash_bit); |
| 362 | |
| 363 | array_wr32(E1000_MTA, hash_reg, mta); |
| 364 | wrfl(); |
| 365 | } |
| 366 | |
| 367 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 368 | * igb_hash_mc_addr - Generate a multicast hash value |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 369 | * @hw: pointer to the HW structure |
| 370 | * @mc_addr: pointer to a multicast address |
| 371 | * |
| 372 | * Generates a multicast address hash value which is used to determine |
| 373 | * the multicast filter table array address and new table value. See |
| 374 | * igb_mta_set() |
| 375 | **/ |
Alexander Duyck | 44c852e | 2009-09-17 14:52:29 +0000 | [diff] [blame] | 376 | static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 377 | { |
| 378 | u32 hash_value, hash_mask; |
| 379 | u8 bit_shift = 0; |
| 380 | |
| 381 | /* Register count multiplied by bits per register */ |
| 382 | hash_mask = (hw->mac.mta_reg_count * 32) - 1; |
| 383 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 384 | /* For a mc_filter_type of 0, bit_shift is the number of left-shifts |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 385 | * where 0xFF would still fall within the hash mask. |
| 386 | */ |
| 387 | while (hash_mask >> bit_shift != 0xFF) |
| 388 | bit_shift++; |
| 389 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 390 | /* The portion of the address that is used for the hash table |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 391 | * is determined by the mc_filter_type setting. |
| 392 | * The algorithm is such that there is a total of 8 bits of shifting. |
| 393 | * The bit_shift for a mc_filter_type of 0 represents the number of |
| 394 | * left-shifts where the MSB of mc_addr[5] would still fall within |
| 395 | * the hash_mask. Case 0 does this exactly. Since there are a total |
| 396 | * of 8 bits of shifting, then mc_addr[4] will shift right the |
| 397 | * remaining number of bits. Thus 8 - bit_shift. The rest of the |
| 398 | * cases are a variation of this algorithm...essentially raising the |
| 399 | * number of bits to shift mc_addr[5] left, while still keeping the |
| 400 | * 8-bit shifting total. |
| 401 | * |
| 402 | * For example, given the following Destination MAC Address and an |
| 403 | * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), |
| 404 | * we can see that the bit_shift for case 0 is 4. These are the hash |
| 405 | * values resulting from each mc_filter_type... |
| 406 | * [0] [1] [2] [3] [4] [5] |
| 407 | * 01 AA 00 12 34 56 |
| 408 | * LSB MSB |
| 409 | * |
| 410 | * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 |
| 411 | * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 |
| 412 | * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 |
| 413 | * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 |
| 414 | */ |
| 415 | switch (hw->mac.mc_filter_type) { |
| 416 | default: |
| 417 | case 0: |
| 418 | break; |
| 419 | case 1: |
| 420 | bit_shift += 1; |
| 421 | break; |
| 422 | case 2: |
| 423 | bit_shift += 2; |
| 424 | break; |
| 425 | case 3: |
| 426 | bit_shift += 4; |
| 427 | break; |
| 428 | } |
| 429 | |
| 430 | hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | |
| 431 | (((u16) mc_addr[5]) << bit_shift))); |
| 432 | |
| 433 | return hash_value; |
| 434 | } |
| 435 | |
| 436 | /** |
Alexander Duyck | 44c852e | 2009-09-17 14:52:29 +0000 | [diff] [blame] | 437 | * igb_update_mc_addr_list - Update Multicast addresses |
| 438 | * @hw: pointer to the HW structure |
| 439 | * @mc_addr_list: array of multicast addresses to program |
| 440 | * @mc_addr_count: number of multicast addresses to program |
| 441 | * |
| 442 | * Updates entire Multicast Table Array. |
| 443 | * The caller must have a packed mc_addr_list of multicast addresses. |
| 444 | **/ |
| 445 | void igb_update_mc_addr_list(struct e1000_hw *hw, |
| 446 | u8 *mc_addr_list, u32 mc_addr_count) |
| 447 | { |
| 448 | u32 hash_value, hash_bit, hash_reg; |
| 449 | int i; |
| 450 | |
| 451 | /* clear mta_shadow */ |
| 452 | memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); |
| 453 | |
| 454 | /* update mta_shadow from mc_addr_list */ |
| 455 | for (i = 0; (u32) i < mc_addr_count; i++) { |
| 456 | hash_value = igb_hash_mc_addr(hw, mc_addr_list); |
| 457 | |
| 458 | hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); |
| 459 | hash_bit = hash_value & 0x1F; |
| 460 | |
| 461 | hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); |
| 462 | mc_addr_list += (ETH_ALEN); |
| 463 | } |
| 464 | |
| 465 | /* replace the entire MTA table */ |
| 466 | for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) |
| 467 | array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]); |
| 468 | wrfl(); |
| 469 | } |
| 470 | |
| 471 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 472 | * igb_clear_hw_cntrs_base - Clear base hardware counters |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 473 | * @hw: pointer to the HW structure |
| 474 | * |
| 475 | * Clears the base hardware counters by reading the counter registers. |
| 476 | **/ |
| 477 | void igb_clear_hw_cntrs_base(struct e1000_hw *hw) |
| 478 | { |
Alexander Duyck | cc9073b | 2009-10-05 06:31:25 +0000 | [diff] [blame] | 479 | rd32(E1000_CRCERRS); |
| 480 | rd32(E1000_SYMERRS); |
| 481 | rd32(E1000_MPC); |
| 482 | rd32(E1000_SCC); |
| 483 | rd32(E1000_ECOL); |
| 484 | rd32(E1000_MCC); |
| 485 | rd32(E1000_LATECOL); |
| 486 | rd32(E1000_COLC); |
| 487 | rd32(E1000_DC); |
| 488 | rd32(E1000_SEC); |
| 489 | rd32(E1000_RLEC); |
| 490 | rd32(E1000_XONRXC); |
| 491 | rd32(E1000_XONTXC); |
| 492 | rd32(E1000_XOFFRXC); |
| 493 | rd32(E1000_XOFFTXC); |
| 494 | rd32(E1000_FCRUC); |
| 495 | rd32(E1000_GPRC); |
| 496 | rd32(E1000_BPRC); |
| 497 | rd32(E1000_MPRC); |
| 498 | rd32(E1000_GPTC); |
| 499 | rd32(E1000_GORCL); |
| 500 | rd32(E1000_GORCH); |
| 501 | rd32(E1000_GOTCL); |
| 502 | rd32(E1000_GOTCH); |
| 503 | rd32(E1000_RNBC); |
| 504 | rd32(E1000_RUC); |
| 505 | rd32(E1000_RFC); |
| 506 | rd32(E1000_ROC); |
| 507 | rd32(E1000_RJC); |
| 508 | rd32(E1000_TORL); |
| 509 | rd32(E1000_TORH); |
| 510 | rd32(E1000_TOTL); |
| 511 | rd32(E1000_TOTH); |
| 512 | rd32(E1000_TPR); |
| 513 | rd32(E1000_TPT); |
| 514 | rd32(E1000_MPTC); |
| 515 | rd32(E1000_BPTC); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 519 | * igb_check_for_copper_link - Check for link (Copper) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 520 | * @hw: pointer to the HW structure |
| 521 | * |
| 522 | * Checks to see of the link status of the hardware has changed. If a |
| 523 | * change in link status has been detected, then we read the PHY registers |
| 524 | * to get the current speed/duplex if link exists. |
| 525 | **/ |
| 526 | s32 igb_check_for_copper_link(struct e1000_hw *hw) |
| 527 | { |
| 528 | struct e1000_mac_info *mac = &hw->mac; |
| 529 | s32 ret_val; |
| 530 | bool link; |
| 531 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 532 | /* We only want to go out to the PHY registers to see if Auto-Neg |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 533 | * has completed and/or if our link status has changed. The |
| 534 | * get_link_status flag is set upon receiving a Link Status |
| 535 | * Change or Rx Sequence Error interrupt. |
| 536 | */ |
| 537 | if (!mac->get_link_status) { |
| 538 | ret_val = 0; |
| 539 | goto out; |
| 540 | } |
| 541 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 542 | /* First we want to see if the MII Status Register reports |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 543 | * link. If so, then we want to get the current speed/duplex |
| 544 | * of the PHY. |
| 545 | */ |
| 546 | ret_val = igb_phy_has_link(hw, 1, 0, &link); |
| 547 | if (ret_val) |
| 548 | goto out; |
| 549 | |
| 550 | if (!link) |
| 551 | goto out; /* No link detected */ |
| 552 | |
| 553 | mac->get_link_status = false; |
| 554 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 555 | /* Check if there was DownShift, must be checked |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 556 | * immediately after link-up |
| 557 | */ |
| 558 | igb_check_downshift(hw); |
| 559 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 560 | /* If we are forcing speed/duplex, then we simply return since |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 561 | * we have already determined whether we have link or not. |
| 562 | */ |
| 563 | if (!mac->autoneg) { |
| 564 | ret_val = -E1000_ERR_CONFIG; |
| 565 | goto out; |
| 566 | } |
| 567 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 568 | /* Auto-Neg is enabled. Auto Speed Detection takes care |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 569 | * of MAC speed/duplex configuration. So we only need to |
| 570 | * configure Collision Distance in the MAC. |
| 571 | */ |
| 572 | igb_config_collision_dist(hw); |
| 573 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 574 | /* Configure Flow Control now that Auto-Neg has completed. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 575 | * First, we need to restore the desired flow control |
| 576 | * settings because we may have had to re-autoneg with a |
| 577 | * different link partner. |
| 578 | */ |
| 579 | ret_val = igb_config_fc_after_link_up(hw); |
| 580 | if (ret_val) |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 581 | hw_dbg("Error configuring flow control\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 582 | |
| 583 | out: |
| 584 | return ret_val; |
| 585 | } |
| 586 | |
| 587 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 588 | * igb_setup_link - Setup flow control and link settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 589 | * @hw: pointer to the HW structure |
| 590 | * |
| 591 | * Determines which flow control settings to use, then configures flow |
| 592 | * control. Calls the appropriate media-specific link configuration |
| 593 | * function. Assuming the adapter has a valid link partner, a valid link |
| 594 | * should be established. Assumes the hardware has previously been reset |
| 595 | * and the transmitter and receiver are not enabled. |
| 596 | **/ |
| 597 | s32 igb_setup_link(struct e1000_hw *hw) |
| 598 | { |
| 599 | s32 ret_val = 0; |
| 600 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 601 | /* In the case of the phy reset being blocked, we already have a link. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 602 | * We do not need to set it up again. |
| 603 | */ |
| 604 | if (igb_check_reset_block(hw)) |
| 605 | goto out; |
| 606 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 607 | /* If requested flow control is set to default, set flow control |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 608 | * based on the EEPROM flow control settings. |
| 609 | */ |
| 610 | if (hw->fc.requested_mode == e1000_fc_default) { |
| 611 | ret_val = igb_set_default_fc(hw); |
| 612 | if (ret_val) |
| 613 | goto out; |
| 614 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 615 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 616 | /* We want to save off the original Flow Control configuration just |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 617 | * in case we get disconnected and then reconnected into a different |
| 618 | * hub or switch with different Flow Control capabilities. |
| 619 | */ |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 620 | hw->fc.current_mode = hw->fc.requested_mode; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 621 | |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 622 | hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 623 | |
| 624 | /* Call the necessary media_type subroutine to configure the link. */ |
| 625 | ret_val = hw->mac.ops.setup_physical_interface(hw); |
| 626 | if (ret_val) |
| 627 | goto out; |
| 628 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 629 | /* Initialize the flow control address, type, and PAUSE timer |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 630 | * registers to their default values. This is done even if flow |
| 631 | * control is disabled, because it does not hurt anything to |
| 632 | * initialize these registers. |
| 633 | */ |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 634 | hw_dbg("Initializing the Flow Control address, type and timer regs\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 635 | wr32(E1000_FCT, FLOW_CONTROL_TYPE); |
| 636 | wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
| 637 | wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); |
| 638 | |
| 639 | wr32(E1000_FCTTV, hw->fc.pause_time); |
| 640 | |
| 641 | ret_val = igb_set_fc_watermarks(hw); |
| 642 | |
| 643 | out: |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 644 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 645 | return ret_val; |
| 646 | } |
| 647 | |
| 648 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 649 | * igb_config_collision_dist - Configure collision distance |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 650 | * @hw: pointer to the HW structure |
| 651 | * |
| 652 | * Configures the collision distance to the default value and is used |
| 653 | * during link setup. Currently no func pointer exists and all |
| 654 | * implementations are handled in the generic version of this function. |
| 655 | **/ |
| 656 | void igb_config_collision_dist(struct e1000_hw *hw) |
| 657 | { |
| 658 | u32 tctl; |
| 659 | |
| 660 | tctl = rd32(E1000_TCTL); |
| 661 | |
| 662 | tctl &= ~E1000_TCTL_COLD; |
| 663 | tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; |
| 664 | |
| 665 | wr32(E1000_TCTL, tctl); |
| 666 | wrfl(); |
| 667 | } |
| 668 | |
| 669 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 670 | * igb_set_fc_watermarks - Set flow control high/low watermarks |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 671 | * @hw: pointer to the HW structure |
| 672 | * |
| 673 | * Sets the flow control high/low threshold (watermark) registers. If |
| 674 | * flow control XON frame transmission is enabled, then set XON frame |
| 675 | * tansmission as well. |
| 676 | **/ |
| 677 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw) |
| 678 | { |
| 679 | s32 ret_val = 0; |
| 680 | u32 fcrtl = 0, fcrth = 0; |
| 681 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 682 | /* Set the flow control receive threshold registers. Normally, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 683 | * these registers will be set to a default threshold that may be |
| 684 | * adjusted later by the driver's runtime code. However, if the |
| 685 | * ability to transmit pause frames is not enabled, then these |
| 686 | * registers will be set to 0. |
| 687 | */ |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 688 | if (hw->fc.current_mode & e1000_fc_tx_pause) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 689 | /* We need to set up the Receive Threshold high and low water |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 690 | * marks as well as (optionally) enabling the transmission of |
| 691 | * XON frames. |
| 692 | */ |
| 693 | fcrtl = hw->fc.low_water; |
| 694 | if (hw->fc.send_xon) |
| 695 | fcrtl |= E1000_FCRTL_XONE; |
| 696 | |
| 697 | fcrth = hw->fc.high_water; |
| 698 | } |
| 699 | wr32(E1000_FCRTL, fcrtl); |
| 700 | wr32(E1000_FCRTH, fcrth); |
| 701 | |
| 702 | return ret_val; |
| 703 | } |
| 704 | |
| 705 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 706 | * igb_set_default_fc - Set flow control default values |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 707 | * @hw: pointer to the HW structure |
| 708 | * |
| 709 | * Read the EEPROM for the default values for flow control and store the |
| 710 | * values. |
| 711 | **/ |
| 712 | static s32 igb_set_default_fc(struct e1000_hw *hw) |
| 713 | { |
| 714 | s32 ret_val = 0; |
| 715 | u16 nvm_data; |
| 716 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 717 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 718 | * that determine the hardware's default PAUSE (flow control) mode, |
| 719 | * a bit that determines whether the HW defaults to enabling or |
| 720 | * disabling auto-negotiation, and the direction of the |
| 721 | * SW defined pins. If there is no SW over-ride of the flow |
| 722 | * control setting, then the variable hw->fc will |
| 723 | * be initialized based on a value in the EEPROM. |
| 724 | */ |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 725 | ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 726 | |
| 727 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 728 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 729 | goto out; |
| 730 | } |
| 731 | |
| 732 | if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 733 | hw->fc.requested_mode = e1000_fc_none; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 734 | else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == |
| 735 | NVM_WORD0F_ASM_DIR) |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 736 | hw->fc.requested_mode = e1000_fc_tx_pause; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 737 | else |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 738 | hw->fc.requested_mode = e1000_fc_full; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 739 | |
| 740 | out: |
| 741 | return ret_val; |
| 742 | } |
| 743 | |
| 744 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 745 | * igb_force_mac_fc - Force the MAC's flow control settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 746 | * @hw: pointer to the HW structure |
| 747 | * |
| 748 | * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the |
| 749 | * device control register to reflect the adapter settings. TFCE and RFCE |
| 750 | * need to be explicitly set by software when a copper PHY is used because |
| 751 | * autonegotiation is managed by the PHY rather than the MAC. Software must |
| 752 | * also configure these bits when link is forced on a fiber connection. |
| 753 | **/ |
| 754 | s32 igb_force_mac_fc(struct e1000_hw *hw) |
| 755 | { |
| 756 | u32 ctrl; |
| 757 | s32 ret_val = 0; |
| 758 | |
| 759 | ctrl = rd32(E1000_CTRL); |
| 760 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 761 | /* Because we didn't get link via the internal auto-negotiation |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 762 | * mechanism (we either forced link or we got link via PHY |
| 763 | * auto-neg), we have to manually enable/disable transmit an |
| 764 | * receive flow control. |
| 765 | * |
| 766 | * The "Case" statement below enables/disable flow control |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 767 | * according to the "hw->fc.current_mode" parameter. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 768 | * |
| 769 | * The possible values of the "fc" parameter are: |
| 770 | * 0: Flow control is completely disabled |
| 771 | * 1: Rx flow control is enabled (we can receive pause |
| 772 | * frames but not send pause frames). |
| 773 | * 2: Tx flow control is enabled (we can send pause frames |
| 774 | * frames but we do not receive pause frames). |
| 775 | * 3: Both Rx and TX flow control (symmetric) is enabled. |
| 776 | * other: No other values should be possible at this point. |
| 777 | */ |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 778 | hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 779 | |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 780 | switch (hw->fc.current_mode) { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 781 | case e1000_fc_none: |
| 782 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
| 783 | break; |
| 784 | case e1000_fc_rx_pause: |
| 785 | ctrl &= (~E1000_CTRL_TFCE); |
| 786 | ctrl |= E1000_CTRL_RFCE; |
| 787 | break; |
| 788 | case e1000_fc_tx_pause: |
| 789 | ctrl &= (~E1000_CTRL_RFCE); |
| 790 | ctrl |= E1000_CTRL_TFCE; |
| 791 | break; |
| 792 | case e1000_fc_full: |
| 793 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
| 794 | break; |
| 795 | default: |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 796 | hw_dbg("Flow control param set incorrectly\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 797 | ret_val = -E1000_ERR_CONFIG; |
| 798 | goto out; |
| 799 | } |
| 800 | |
| 801 | wr32(E1000_CTRL, ctrl); |
| 802 | |
| 803 | out: |
| 804 | return ret_val; |
| 805 | } |
| 806 | |
| 807 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 808 | * igb_config_fc_after_link_up - Configures flow control after link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 809 | * @hw: pointer to the HW structure |
| 810 | * |
| 811 | * Checks the status of auto-negotiation after link up to ensure that the |
| 812 | * speed and duplex were not forced. If the link needed to be forced, then |
| 813 | * flow control needs to be forced also. If auto-negotiation is enabled |
| 814 | * and did not fail, then we configure flow control based on our link |
| 815 | * partner. |
| 816 | **/ |
| 817 | s32 igb_config_fc_after_link_up(struct e1000_hw *hw) |
| 818 | { |
| 819 | struct e1000_mac_info *mac = &hw->mac; |
| 820 | s32 ret_val = 0; |
Carolyn Wyborny | daf56e4 | 2012-10-23 12:54:33 +0000 | [diff] [blame] | 821 | u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 822 | u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; |
| 823 | u16 speed, duplex; |
| 824 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 825 | /* Check for the case where we have fiber media and auto-neg failed |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 826 | * so we had to force link. In this case, we need to force the |
| 827 | * configuration of the MAC to match the "fc" parameter. |
| 828 | */ |
| 829 | if (mac->autoneg_failed) { |
Alexander Duyck | dcc3ae9 | 2009-07-23 18:07:20 +0000 | [diff] [blame] | 830 | if (hw->phy.media_type == e1000_media_type_internal_serdes) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 831 | ret_val = igb_force_mac_fc(hw); |
| 832 | } else { |
| 833 | if (hw->phy.media_type == e1000_media_type_copper) |
| 834 | ret_val = igb_force_mac_fc(hw); |
| 835 | } |
| 836 | |
| 837 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 838 | hw_dbg("Error forcing flow control settings\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 839 | goto out; |
| 840 | } |
| 841 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 842 | /* Check for the case where we have copper media and auto-neg is |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 843 | * enabled. In this case, we need to check and see if Auto-Neg |
| 844 | * has completed, and if so, how the PHY and link partner has |
| 845 | * flow control configured. |
| 846 | */ |
| 847 | if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 848 | /* Read the MII Status Register and check to see if AutoNeg |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 849 | * has completed. We read this twice because this reg has |
| 850 | * some "sticky" (latched) bits. |
| 851 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 852 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 853 | &mii_status_reg); |
| 854 | if (ret_val) |
| 855 | goto out; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 856 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 857 | &mii_status_reg); |
| 858 | if (ret_val) |
| 859 | goto out; |
| 860 | |
| 861 | if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 862 | hw_dbg("Copper PHY and Auto Neg " |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 863 | "has not completed.\n"); |
| 864 | goto out; |
| 865 | } |
| 866 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 867 | /* The AutoNeg process has completed, so we now need to |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 868 | * read both the Auto Negotiation Advertisement |
| 869 | * Register (Address 4) and the Auto_Negotiation Base |
| 870 | * Page Ability Register (Address 5) to determine how |
| 871 | * flow control was negotiated. |
| 872 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 873 | ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 874 | &mii_nway_adv_reg); |
| 875 | if (ret_val) |
| 876 | goto out; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 877 | ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 878 | &mii_nway_lp_ability_reg); |
| 879 | if (ret_val) |
| 880 | goto out; |
| 881 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 882 | /* Two bits in the Auto Negotiation Advertisement Register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 883 | * (Address 4) and two bits in the Auto Negotiation Base |
| 884 | * Page Ability Register (Address 5) determine flow control |
| 885 | * for both the PHY and the link partner. The following |
| 886 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
| 887 | * 1999, describes these PAUSE resolution bits and how flow |
| 888 | * control is determined based upon these settings. |
| 889 | * NOTE: DC = Don't Care |
| 890 | * |
| 891 | * LOCAL DEVICE | LINK PARTNER |
| 892 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 893 | *-------|---------|-------|---------|-------------------- |
| 894 | * 0 | 0 | DC | DC | e1000_fc_none |
| 895 | * 0 | 1 | 0 | DC | e1000_fc_none |
| 896 | * 0 | 1 | 1 | 0 | e1000_fc_none |
| 897 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 898 | * 1 | 0 | 0 | DC | e1000_fc_none |
| 899 | * 1 | DC | 1 | DC | e1000_fc_full |
| 900 | * 1 | 1 | 0 | 0 | e1000_fc_none |
| 901 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 902 | * |
| 903 | * Are both PAUSE bits set to 1? If so, this implies |
| 904 | * Symmetric Flow Control is enabled at both ends. The |
| 905 | * ASM_DIR bits are irrelevant per the spec. |
| 906 | * |
| 907 | * For Symmetric Flow Control: |
| 908 | * |
| 909 | * LOCAL DEVICE | LINK PARTNER |
| 910 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 911 | *-------|---------|-------|---------|-------------------- |
| 912 | * 1 | DC | 1 | DC | E1000_fc_full |
| 913 | * |
| 914 | */ |
| 915 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 916 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 917 | /* Now we need to check if the user selected RX ONLY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 918 | * of pause frames. In this case, we had to advertise |
| 919 | * FULL flow control because we could not advertise RX |
| 920 | * ONLY. Hence, we must now check to see if we need to |
| 921 | * turn OFF the TRANSMISSION of PAUSE frames. |
| 922 | */ |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 923 | if (hw->fc.requested_mode == e1000_fc_full) { |
| 924 | hw->fc.current_mode = e1000_fc_full; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 925 | hw_dbg("Flow Control = FULL.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 926 | } else { |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 927 | hw->fc.current_mode = e1000_fc_rx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 928 | hw_dbg("Flow Control = " |
| 929 | "RX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 930 | } |
| 931 | } |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 932 | /* For receiving PAUSE frames ONLY. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 933 | * |
| 934 | * LOCAL DEVICE | LINK PARTNER |
| 935 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 936 | *-------|---------|-------|---------|-------------------- |
| 937 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 938 | */ |
| 939 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 940 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 941 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 942 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 943 | hw->fc.current_mode = e1000_fc_tx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 944 | hw_dbg("Flow Control = TX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 945 | } |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 946 | /* For transmitting PAUSE frames ONLY. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 947 | * |
| 948 | * LOCAL DEVICE | LINK PARTNER |
| 949 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 950 | *-------|---------|-------|---------|-------------------- |
| 951 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 952 | */ |
| 953 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 954 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 955 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 956 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 957 | hw->fc.current_mode = e1000_fc_rx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 958 | hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 959 | } |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 960 | /* Per the IEEE spec, at this point flow control should be |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 961 | * disabled. However, we want to consider that we could |
| 962 | * be connected to a legacy switch that doesn't advertise |
| 963 | * desired flow control, but can be forced on the link |
| 964 | * partner. So if we advertised no flow control, that is |
| 965 | * what we will resolve to. If we advertised some kind of |
| 966 | * receive capability (Rx Pause Only or Full Flow Control) |
| 967 | * and the link partner advertised none, we will configure |
| 968 | * ourselves to enable Rx Flow Control only. We can do |
| 969 | * this safely for two reasons: If the link partner really |
| 970 | * didn't want flow control enabled, and we enable Rx, no |
| 971 | * harm done since we won't be receiving any PAUSE frames |
| 972 | * anyway. If the intent on the link partner was to have |
| 973 | * flow control enabled, then by us enabling RX only, we |
| 974 | * can at least receive pause frames and process them. |
| 975 | * This is a good idea because in most cases, since we are |
| 976 | * predominantly a server NIC, more times than not we will |
| 977 | * be asked to delay transmission of packets than asking |
| 978 | * our link partner to pause transmission of frames. |
| 979 | */ |
Akeem G. Abodunrin | 5c17a20 | 2013-01-29 10:15:31 +0000 | [diff] [blame] | 980 | else if ((hw->fc.requested_mode == e1000_fc_none) || |
| 981 | (hw->fc.requested_mode == e1000_fc_tx_pause) || |
| 982 | (hw->fc.strict_ieee)) { |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 983 | hw->fc.current_mode = e1000_fc_none; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 984 | hw_dbg("Flow Control = NONE.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 985 | } else { |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 986 | hw->fc.current_mode = e1000_fc_rx_pause; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 987 | hw_dbg("Flow Control = RX PAUSE frames only.\r\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 988 | } |
| 989 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 990 | /* Now we need to do one last check... If we auto- |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 991 | * negotiated to HALF DUPLEX, flow control should not be |
| 992 | * enabled per IEEE 802.3 spec. |
| 993 | */ |
| 994 | ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); |
| 995 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 996 | hw_dbg("Error getting link speed and duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 997 | goto out; |
| 998 | } |
| 999 | |
| 1000 | if (duplex == HALF_DUPLEX) |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 1001 | hw->fc.current_mode = e1000_fc_none; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1002 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1003 | /* Now we call a subroutine to actually force the MAC |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1004 | * controller to use the correct flow control settings. |
| 1005 | */ |
| 1006 | ret_val = igb_force_mac_fc(hw); |
| 1007 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1008 | hw_dbg("Error forcing flow control settings\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1009 | goto out; |
| 1010 | } |
| 1011 | } |
Carolyn Wyborny | daf56e4 | 2012-10-23 12:54:33 +0000 | [diff] [blame] | 1012 | /* Check for the case where we have SerDes media and auto-neg is |
| 1013 | * enabled. In this case, we need to check and see if Auto-Neg |
| 1014 | * has completed, and if so, how the PHY and link partner has |
| 1015 | * flow control configured. |
| 1016 | */ |
| 1017 | if ((hw->phy.media_type == e1000_media_type_internal_serdes) |
| 1018 | && mac->autoneg) { |
| 1019 | /* Read the PCS_LSTS and check to see if AutoNeg |
| 1020 | * has completed. |
| 1021 | */ |
| 1022 | pcs_status_reg = rd32(E1000_PCS_LSTAT); |
| 1023 | |
| 1024 | if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { |
| 1025 | hw_dbg("PCS Auto Neg has not completed.\n"); |
| 1026 | return ret_val; |
| 1027 | } |
| 1028 | |
| 1029 | /* The AutoNeg process has completed, so we now need to |
| 1030 | * read both the Auto Negotiation Advertisement |
| 1031 | * Register (PCS_ANADV) and the Auto_Negotiation Base |
| 1032 | * Page Ability Register (PCS_LPAB) to determine how |
| 1033 | * flow control was negotiated. |
| 1034 | */ |
| 1035 | pcs_adv_reg = rd32(E1000_PCS_ANADV); |
| 1036 | pcs_lp_ability_reg = rd32(E1000_PCS_LPAB); |
| 1037 | |
| 1038 | /* Two bits in the Auto Negotiation Advertisement Register |
| 1039 | * (PCS_ANADV) and two bits in the Auto Negotiation Base |
| 1040 | * Page Ability Register (PCS_LPAB) determine flow control |
| 1041 | * for both the PHY and the link partner. The following |
| 1042 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
| 1043 | * 1999, describes these PAUSE resolution bits and how flow |
| 1044 | * control is determined based upon these settings. |
| 1045 | * NOTE: DC = Don't Care |
| 1046 | * |
| 1047 | * LOCAL DEVICE | LINK PARTNER |
| 1048 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 1049 | *-------|---------|-------|---------|-------------------- |
| 1050 | * 0 | 0 | DC | DC | e1000_fc_none |
| 1051 | * 0 | 1 | 0 | DC | e1000_fc_none |
| 1052 | * 0 | 1 | 1 | 0 | e1000_fc_none |
| 1053 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 1054 | * 1 | 0 | 0 | DC | e1000_fc_none |
| 1055 | * 1 | DC | 1 | DC | e1000_fc_full |
| 1056 | * 1 | 1 | 0 | 0 | e1000_fc_none |
| 1057 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 1058 | * |
| 1059 | * Are both PAUSE bits set to 1? If so, this implies |
| 1060 | * Symmetric Flow Control is enabled at both ends. The |
| 1061 | * ASM_DIR bits are irrelevant per the spec. |
| 1062 | * |
| 1063 | * For Symmetric Flow Control: |
| 1064 | * |
| 1065 | * LOCAL DEVICE | LINK PARTNER |
| 1066 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 1067 | *-------|---------|-------|---------|-------------------- |
| 1068 | * 1 | DC | 1 | DC | e1000_fc_full |
| 1069 | * |
| 1070 | */ |
| 1071 | if ((pcs_adv_reg & E1000_TXCW_PAUSE) && |
| 1072 | (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { |
| 1073 | /* Now we need to check if the user selected Rx ONLY |
| 1074 | * of pause frames. In this case, we had to advertise |
| 1075 | * FULL flow control because we could not advertise Rx |
| 1076 | * ONLY. Hence, we must now check to see if we need to |
| 1077 | * turn OFF the TRANSMISSION of PAUSE frames. |
| 1078 | */ |
| 1079 | if (hw->fc.requested_mode == e1000_fc_full) { |
| 1080 | hw->fc.current_mode = e1000_fc_full; |
| 1081 | hw_dbg("Flow Control = FULL.\n"); |
| 1082 | } else { |
| 1083 | hw->fc.current_mode = e1000_fc_rx_pause; |
| 1084 | hw_dbg("Flow Control = Rx PAUSE frames only.\n"); |
| 1085 | } |
| 1086 | } |
| 1087 | /* For receiving PAUSE frames ONLY. |
| 1088 | * |
| 1089 | * LOCAL DEVICE | LINK PARTNER |
| 1090 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 1091 | *-------|---------|-------|---------|-------------------- |
| 1092 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 1093 | */ |
| 1094 | else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && |
| 1095 | (pcs_adv_reg & E1000_TXCW_ASM_DIR) && |
| 1096 | (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && |
| 1097 | (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { |
| 1098 | hw->fc.current_mode = e1000_fc_tx_pause; |
| 1099 | hw_dbg("Flow Control = Tx PAUSE frames only.\n"); |
| 1100 | } |
| 1101 | /* For transmitting PAUSE frames ONLY. |
| 1102 | * |
| 1103 | * LOCAL DEVICE | LINK PARTNER |
| 1104 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 1105 | *-------|---------|-------|---------|-------------------- |
| 1106 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 1107 | */ |
| 1108 | else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && |
| 1109 | (pcs_adv_reg & E1000_TXCW_ASM_DIR) && |
| 1110 | !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && |
| 1111 | (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { |
| 1112 | hw->fc.current_mode = e1000_fc_rx_pause; |
| 1113 | hw_dbg("Flow Control = Rx PAUSE frames only.\n"); |
| 1114 | } else { |
| 1115 | /* Per the IEEE spec, at this point flow control |
| 1116 | * should be disabled. |
| 1117 | */ |
| 1118 | hw->fc.current_mode = e1000_fc_none; |
| 1119 | hw_dbg("Flow Control = NONE.\n"); |
| 1120 | } |
| 1121 | |
| 1122 | /* Now we call a subroutine to actually force the MAC |
| 1123 | * controller to use the correct flow control settings. |
| 1124 | */ |
| 1125 | pcs_ctrl_reg = rd32(E1000_PCS_LCTL); |
| 1126 | pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; |
| 1127 | wr32(E1000_PCS_LCTL, pcs_ctrl_reg); |
| 1128 | |
| 1129 | ret_val = igb_force_mac_fc(hw); |
| 1130 | if (ret_val) { |
| 1131 | hw_dbg("Error forcing flow control settings\n"); |
| 1132 | return ret_val; |
| 1133 | } |
| 1134 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1135 | |
| 1136 | out: |
| 1137 | return ret_val; |
| 1138 | } |
| 1139 | |
| 1140 | /** |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1141 | * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1142 | * @hw: pointer to the HW structure |
| 1143 | * @speed: stores the current speed |
| 1144 | * @duplex: stores the current duplex |
| 1145 | * |
| 1146 | * Read the status register for the current speed/duplex and store the current |
| 1147 | * speed and duplex for copper connections. |
| 1148 | **/ |
| 1149 | s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, |
| 1150 | u16 *duplex) |
| 1151 | { |
| 1152 | u32 status; |
| 1153 | |
| 1154 | status = rd32(E1000_STATUS); |
| 1155 | if (status & E1000_STATUS_SPEED_1000) { |
| 1156 | *speed = SPEED_1000; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1157 | hw_dbg("1000 Mbs, "); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1158 | } else if (status & E1000_STATUS_SPEED_100) { |
| 1159 | *speed = SPEED_100; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1160 | hw_dbg("100 Mbs, "); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1161 | } else { |
| 1162 | *speed = SPEED_10; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1163 | hw_dbg("10 Mbs, "); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1164 | } |
| 1165 | |
| 1166 | if (status & E1000_STATUS_FD) { |
| 1167 | *duplex = FULL_DUPLEX; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1168 | hw_dbg("Full Duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1169 | } else { |
| 1170 | *duplex = HALF_DUPLEX; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1171 | hw_dbg("Half Duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1172 | } |
| 1173 | |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame^] | 1174 | /* Check if it is an I354 2.5Gb backplane connection. */ |
| 1175 | if (hw->mac.type == e1000_i354) { |
| 1176 | if ((status & E1000_STATUS_2P5_SKU) && |
| 1177 | !(status & E1000_STATUS_2P5_SKU_OVER)) { |
| 1178 | *speed = SPEED_2500; |
| 1179 | *duplex = FULL_DUPLEX; |
| 1180 | hw_dbg("2500 Mbs, "); |
| 1181 | hw_dbg("Full Duplex\n"); |
| 1182 | } |
| 1183 | } |
| 1184 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1185 | return 0; |
| 1186 | } |
| 1187 | |
| 1188 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1189 | * igb_get_hw_semaphore - Acquire hardware semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1190 | * @hw: pointer to the HW structure |
| 1191 | * |
| 1192 | * Acquire the HW semaphore to access the PHY or NVM |
| 1193 | **/ |
| 1194 | s32 igb_get_hw_semaphore(struct e1000_hw *hw) |
| 1195 | { |
| 1196 | u32 swsm; |
| 1197 | s32 ret_val = 0; |
| 1198 | s32 timeout = hw->nvm.word_size + 1; |
| 1199 | s32 i = 0; |
| 1200 | |
| 1201 | /* Get the SW semaphore */ |
| 1202 | while (i < timeout) { |
| 1203 | swsm = rd32(E1000_SWSM); |
| 1204 | if (!(swsm & E1000_SWSM_SMBI)) |
| 1205 | break; |
| 1206 | |
| 1207 | udelay(50); |
| 1208 | i++; |
| 1209 | } |
| 1210 | |
| 1211 | if (i == timeout) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1212 | hw_dbg("Driver can't access device - SMBI bit is set.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1213 | ret_val = -E1000_ERR_NVM; |
| 1214 | goto out; |
| 1215 | } |
| 1216 | |
| 1217 | /* Get the FW semaphore. */ |
| 1218 | for (i = 0; i < timeout; i++) { |
| 1219 | swsm = rd32(E1000_SWSM); |
| 1220 | wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI); |
| 1221 | |
| 1222 | /* Semaphore acquired if bit latched */ |
| 1223 | if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) |
| 1224 | break; |
| 1225 | |
| 1226 | udelay(50); |
| 1227 | } |
| 1228 | |
| 1229 | if (i == timeout) { |
| 1230 | /* Release semaphores */ |
| 1231 | igb_put_hw_semaphore(hw); |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1232 | hw_dbg("Driver can't access the NVM\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1233 | ret_val = -E1000_ERR_NVM; |
| 1234 | goto out; |
| 1235 | } |
| 1236 | |
| 1237 | out: |
| 1238 | return ret_val; |
| 1239 | } |
| 1240 | |
| 1241 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1242 | * igb_put_hw_semaphore - Release hardware semaphore |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1243 | * @hw: pointer to the HW structure |
| 1244 | * |
| 1245 | * Release hardware semaphore used to access the PHY or NVM |
| 1246 | **/ |
| 1247 | void igb_put_hw_semaphore(struct e1000_hw *hw) |
| 1248 | { |
| 1249 | u32 swsm; |
| 1250 | |
| 1251 | swsm = rd32(E1000_SWSM); |
| 1252 | |
| 1253 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
| 1254 | |
| 1255 | wr32(E1000_SWSM, swsm); |
| 1256 | } |
| 1257 | |
| 1258 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1259 | * igb_get_auto_rd_done - Check for auto read completion |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1260 | * @hw: pointer to the HW structure |
| 1261 | * |
| 1262 | * Check EEPROM for Auto Read done bit. |
| 1263 | **/ |
| 1264 | s32 igb_get_auto_rd_done(struct e1000_hw *hw) |
| 1265 | { |
| 1266 | s32 i = 0; |
| 1267 | s32 ret_val = 0; |
| 1268 | |
| 1269 | |
| 1270 | while (i < AUTO_READ_DONE_TIMEOUT) { |
| 1271 | if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD) |
| 1272 | break; |
| 1273 | msleep(1); |
| 1274 | i++; |
| 1275 | } |
| 1276 | |
| 1277 | if (i == AUTO_READ_DONE_TIMEOUT) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1278 | hw_dbg("Auto read by HW from NVM has not completed.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1279 | ret_val = -E1000_ERR_RESET; |
| 1280 | goto out; |
| 1281 | } |
| 1282 | |
| 1283 | out: |
| 1284 | return ret_val; |
| 1285 | } |
| 1286 | |
| 1287 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1288 | * igb_valid_led_default - Verify a valid default LED config |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1289 | * @hw: pointer to the HW structure |
| 1290 | * @data: pointer to the NVM (EEPROM) |
| 1291 | * |
| 1292 | * Read the EEPROM for the current default LED configuration. If the |
| 1293 | * LED configuration is not valid, set to a valid LED configuration. |
| 1294 | **/ |
| 1295 | static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data) |
| 1296 | { |
| 1297 | s32 ret_val; |
| 1298 | |
Alexander Duyck | 312c75a | 2009-02-06 23:17:47 +0000 | [diff] [blame] | 1299 | ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1300 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1301 | hw_dbg("NVM Read Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1302 | goto out; |
| 1303 | } |
| 1304 | |
Alexander Duyck | 099e1cb | 2009-07-23 18:07:40 +0000 | [diff] [blame] | 1305 | if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { |
| 1306 | switch(hw->phy.media_type) { |
| 1307 | case e1000_media_type_internal_serdes: |
| 1308 | *data = ID_LED_DEFAULT_82575_SERDES; |
| 1309 | break; |
| 1310 | case e1000_media_type_copper: |
| 1311 | default: |
| 1312 | *data = ID_LED_DEFAULT; |
| 1313 | break; |
| 1314 | } |
| 1315 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1316 | out: |
| 1317 | return ret_val; |
| 1318 | } |
| 1319 | |
| 1320 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1321 | * igb_id_led_init - |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1322 | * @hw: pointer to the HW structure |
| 1323 | * |
| 1324 | **/ |
| 1325 | s32 igb_id_led_init(struct e1000_hw *hw) |
| 1326 | { |
| 1327 | struct e1000_mac_info *mac = &hw->mac; |
| 1328 | s32 ret_val; |
| 1329 | const u32 ledctl_mask = 0x000000FF; |
| 1330 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
| 1331 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
| 1332 | u16 data, i, temp; |
| 1333 | const u16 led_mask = 0x0F; |
| 1334 | |
| 1335 | ret_val = igb_valid_led_default(hw, &data); |
| 1336 | if (ret_val) |
| 1337 | goto out; |
| 1338 | |
| 1339 | mac->ledctl_default = rd32(E1000_LEDCTL); |
| 1340 | mac->ledctl_mode1 = mac->ledctl_default; |
| 1341 | mac->ledctl_mode2 = mac->ledctl_default; |
| 1342 | |
| 1343 | for (i = 0; i < 4; i++) { |
| 1344 | temp = (data >> (i << 2)) & led_mask; |
| 1345 | switch (temp) { |
| 1346 | case ID_LED_ON1_DEF2: |
| 1347 | case ID_LED_ON1_ON2: |
| 1348 | case ID_LED_ON1_OFF2: |
| 1349 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1350 | mac->ledctl_mode1 |= ledctl_on << (i << 3); |
| 1351 | break; |
| 1352 | case ID_LED_OFF1_DEF2: |
| 1353 | case ID_LED_OFF1_ON2: |
| 1354 | case ID_LED_OFF1_OFF2: |
| 1355 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1356 | mac->ledctl_mode1 |= ledctl_off << (i << 3); |
| 1357 | break; |
| 1358 | default: |
| 1359 | /* Do nothing */ |
| 1360 | break; |
| 1361 | } |
| 1362 | switch (temp) { |
| 1363 | case ID_LED_DEF1_ON2: |
| 1364 | case ID_LED_ON1_ON2: |
| 1365 | case ID_LED_OFF1_ON2: |
| 1366 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1367 | mac->ledctl_mode2 |= ledctl_on << (i << 3); |
| 1368 | break; |
| 1369 | case ID_LED_DEF1_OFF2: |
| 1370 | case ID_LED_ON1_OFF2: |
| 1371 | case ID_LED_OFF1_OFF2: |
| 1372 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1373 | mac->ledctl_mode2 |= ledctl_off << (i << 3); |
| 1374 | break; |
| 1375 | default: |
| 1376 | /* Do nothing */ |
| 1377 | break; |
| 1378 | } |
| 1379 | } |
| 1380 | |
| 1381 | out: |
| 1382 | return ret_val; |
| 1383 | } |
| 1384 | |
| 1385 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1386 | * igb_cleanup_led - Set LED config to default operation |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1387 | * @hw: pointer to the HW structure |
| 1388 | * |
| 1389 | * Remove the current LED configuration and set the LED configuration |
| 1390 | * to the default value, saved from the EEPROM. |
| 1391 | **/ |
| 1392 | s32 igb_cleanup_led(struct e1000_hw *hw) |
| 1393 | { |
| 1394 | wr32(E1000_LEDCTL, hw->mac.ledctl_default); |
| 1395 | return 0; |
| 1396 | } |
| 1397 | |
| 1398 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1399 | * igb_blink_led - Blink LED |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1400 | * @hw: pointer to the HW structure |
| 1401 | * |
| 1402 | * Blink the led's which are set to be on. |
| 1403 | **/ |
| 1404 | s32 igb_blink_led(struct e1000_hw *hw) |
| 1405 | { |
| 1406 | u32 ledctl_blink = 0; |
| 1407 | u32 i; |
| 1408 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1409 | /* set the blink bit for each LED that's "on" (0x0E) |
Alexander Duyck | dcc3ae9 | 2009-07-23 18:07:20 +0000 | [diff] [blame] | 1410 | * in ledctl_mode2 |
| 1411 | */ |
| 1412 | ledctl_blink = hw->mac.ledctl_mode2; |
| 1413 | for (i = 0; i < 4; i++) |
| 1414 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == |
| 1415 | E1000_LEDCTL_MODE_LED_ON) |
| 1416 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << |
| 1417 | (i * 8)); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1418 | |
| 1419 | wr32(E1000_LEDCTL, ledctl_blink); |
| 1420 | |
| 1421 | return 0; |
| 1422 | } |
| 1423 | |
| 1424 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1425 | * igb_led_off - Turn LED off |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1426 | * @hw: pointer to the HW structure |
| 1427 | * |
| 1428 | * Turn LED off. |
| 1429 | **/ |
| 1430 | s32 igb_led_off(struct e1000_hw *hw) |
| 1431 | { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1432 | switch (hw->phy.media_type) { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1433 | case e1000_media_type_copper: |
| 1434 | wr32(E1000_LEDCTL, hw->mac.ledctl_mode1); |
| 1435 | break; |
| 1436 | default: |
| 1437 | break; |
| 1438 | } |
| 1439 | |
| 1440 | return 0; |
| 1441 | } |
| 1442 | |
| 1443 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1444 | * igb_disable_pcie_master - Disables PCI-express master access |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1445 | * @hw: pointer to the HW structure |
| 1446 | * |
| 1447 | * Returns 0 (0) if successful, else returns -10 |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1448 | * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1449 | * the master requests to be disabled. |
| 1450 | * |
| 1451 | * Disables PCI-Express master access and verifies there are no pending |
| 1452 | * requests. |
| 1453 | **/ |
| 1454 | s32 igb_disable_pcie_master(struct e1000_hw *hw) |
| 1455 | { |
| 1456 | u32 ctrl; |
| 1457 | s32 timeout = MASTER_DISABLE_TIMEOUT; |
| 1458 | s32 ret_val = 0; |
| 1459 | |
| 1460 | if (hw->bus.type != e1000_bus_type_pci_express) |
| 1461 | goto out; |
| 1462 | |
| 1463 | ctrl = rd32(E1000_CTRL); |
| 1464 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
| 1465 | wr32(E1000_CTRL, ctrl); |
| 1466 | |
| 1467 | while (timeout) { |
| 1468 | if (!(rd32(E1000_STATUS) & |
| 1469 | E1000_STATUS_GIO_MASTER_ENABLE)) |
| 1470 | break; |
| 1471 | udelay(100); |
| 1472 | timeout--; |
| 1473 | } |
| 1474 | |
| 1475 | if (!timeout) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1476 | hw_dbg("Master requests are pending.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1477 | ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; |
| 1478 | goto out; |
| 1479 | } |
| 1480 | |
| 1481 | out: |
| 1482 | return ret_val; |
| 1483 | } |
| 1484 | |
| 1485 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1486 | * igb_validate_mdi_setting - Verify MDI/MDIx settings |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1487 | * @hw: pointer to the HW structure |
| 1488 | * |
| 1489 | * Verify that when not using auto-negotitation that MDI/MDIx is correctly |
| 1490 | * set, which is forced to MDI mode only. |
| 1491 | **/ |
| 1492 | s32 igb_validate_mdi_setting(struct e1000_hw *hw) |
| 1493 | { |
| 1494 | s32 ret_val = 0; |
| 1495 | |
Matthew Vick | 9f0b851 | 2012-10-16 07:44:45 +0000 | [diff] [blame] | 1496 | /* All MDI settings are supported on 82580 and newer. */ |
| 1497 | if (hw->mac.type >= e1000_82580) |
| 1498 | goto out; |
| 1499 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1500 | if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1501 | hw_dbg("Invalid MDI setting detected\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1502 | hw->phy.mdix = 1; |
| 1503 | ret_val = -E1000_ERR_CONFIG; |
| 1504 | goto out; |
| 1505 | } |
| 1506 | |
| 1507 | out: |
| 1508 | return ret_val; |
| 1509 | } |
| 1510 | |
| 1511 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1512 | * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1513 | * @hw: pointer to the HW structure |
| 1514 | * @reg: 32bit register offset such as E1000_SCTL |
| 1515 | * @offset: register offset to write to |
| 1516 | * @data: data to write at register offset |
| 1517 | * |
| 1518 | * Writes an address/data control type register. There are several of these |
| 1519 | * and they all have the format address << 8 | data and bit 31 is polled for |
| 1520 | * completion. |
| 1521 | **/ |
| 1522 | s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, |
| 1523 | u32 offset, u8 data) |
| 1524 | { |
| 1525 | u32 i, regvalue = 0; |
| 1526 | s32 ret_val = 0; |
| 1527 | |
| 1528 | /* Set up the address and data */ |
| 1529 | regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); |
| 1530 | wr32(reg, regvalue); |
| 1531 | |
| 1532 | /* Poll the ready bit to see if the MDI read completed */ |
| 1533 | for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { |
| 1534 | udelay(5); |
| 1535 | regvalue = rd32(reg); |
| 1536 | if (regvalue & E1000_GEN_CTL_READY) |
| 1537 | break; |
| 1538 | } |
| 1539 | if (!(regvalue & E1000_GEN_CTL_READY)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1540 | hw_dbg("Reg %08x did not indicate ready\n", reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1541 | ret_val = -E1000_ERR_PHY; |
| 1542 | goto out; |
| 1543 | } |
| 1544 | |
| 1545 | out: |
| 1546 | return ret_val; |
| 1547 | } |
| 1548 | |
| 1549 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1550 | * igb_enable_mng_pass_thru - Enable processing of ARP's |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1551 | * @hw: pointer to the HW structure |
| 1552 | * |
Alexander Duyck | e017b60 | 2010-03-25 17:15:06 +0000 | [diff] [blame] | 1553 | * Verifies the hardware needs to leave interface enabled so that frames can |
| 1554 | * be directed to and from the management interface. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1555 | **/ |
| 1556 | bool igb_enable_mng_pass_thru(struct e1000_hw *hw) |
| 1557 | { |
| 1558 | u32 manc; |
| 1559 | u32 fwsm, factps; |
| 1560 | bool ret_val = false; |
| 1561 | |
| 1562 | if (!hw->mac.asf_firmware_present) |
| 1563 | goto out; |
| 1564 | |
| 1565 | manc = rd32(E1000_MANC); |
| 1566 | |
Alexander Duyck | e017b60 | 2010-03-25 17:15:06 +0000 | [diff] [blame] | 1567 | if (!(manc & E1000_MANC_RCV_TCO_EN)) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1568 | goto out; |
| 1569 | |
| 1570 | if (hw->mac.arc_subsystem_valid) { |
| 1571 | fwsm = rd32(E1000_FWSM); |
| 1572 | factps = rd32(E1000_FACTPS); |
| 1573 | |
| 1574 | if (!(factps & E1000_FACTPS_MNGCG) && |
| 1575 | ((fwsm & E1000_FWSM_MODE_MASK) == |
| 1576 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { |
| 1577 | ret_val = true; |
| 1578 | goto out; |
| 1579 | } |
| 1580 | } else { |
| 1581 | if ((manc & E1000_MANC_SMBUS_EN) && |
| 1582 | !(manc & E1000_MANC_ASF_EN)) { |
| 1583 | ret_val = true; |
| 1584 | goto out; |
| 1585 | } |
| 1586 | } |
| 1587 | |
| 1588 | out: |
| 1589 | return ret_val; |
| 1590 | } |