Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel(R) Gigabit Ethernet Linux driver |
Akeem G. Abodunrin | 4b9ea46 | 2013-01-08 18:31:12 +0000 | [diff] [blame] | 4 | Copyright(c) 2007-2013 Intel Corporation. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/if_ether.h> |
| 29 | #include <linux/delay.h> |
| 30 | |
| 31 | #include "e1000_mac.h" |
| 32 | #include "e1000_phy.h" |
| 33 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 34 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); |
| 35 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 36 | u16 *phy_ctrl); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 37 | static s32 igb_wait_autoneg(struct e1000_hw *hw); |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 38 | static s32 igb_set_master_slave_mode(struct e1000_hw *hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 39 | |
| 40 | /* Cable length tables */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 41 | static const u16 e1000_m88_cable_length_table[] = { |
| 42 | 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; |
Alexander Duyck | 2553bb2 | 2009-10-05 06:35:42 +0000 | [diff] [blame] | 43 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 44 | (sizeof(e1000_m88_cable_length_table) / \ |
| 45 | sizeof(e1000_m88_cable_length_table[0])) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 46 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 47 | static const u16 e1000_igp_2_cable_length_table[] = { |
| 48 | 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
| 49 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, |
| 50 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, |
| 51 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, |
| 52 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, |
| 53 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, |
| 54 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, |
| 55 | 104, 109, 114, 118, 121, 124}; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 56 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 57 | (sizeof(e1000_igp_2_cable_length_table) / \ |
| 58 | sizeof(e1000_igp_2_cable_length_table[0])) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 59 | |
| 60 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 61 | * igb_check_reset_block - Check if PHY reset is blocked |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 62 | * @hw: pointer to the HW structure |
| 63 | * |
| 64 | * Read the PHY management control register and check whether a PHY reset |
| 65 | * is blocked. If a reset is not blocked return 0, otherwise |
| 66 | * return E1000_BLK_PHY_RESET (12). |
| 67 | **/ |
| 68 | s32 igb_check_reset_block(struct e1000_hw *hw) |
| 69 | { |
| 70 | u32 manc; |
| 71 | |
| 72 | manc = rd32(E1000_MANC); |
| 73 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 74 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 78 | * igb_get_phy_id - Retrieve the PHY ID and revision |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 79 | * @hw: pointer to the HW structure |
| 80 | * |
| 81 | * Reads the PHY registers and stores the PHY ID and possibly the PHY |
| 82 | * revision in the hardware structure. |
| 83 | **/ |
| 84 | s32 igb_get_phy_id(struct e1000_hw *hw) |
| 85 | { |
| 86 | struct e1000_phy_info *phy = &hw->phy; |
| 87 | s32 ret_val = 0; |
| 88 | u16 phy_id; |
| 89 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 90 | ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 91 | if (ret_val) |
| 92 | goto out; |
| 93 | |
| 94 | phy->id = (u32)(phy_id << 16); |
| 95 | udelay(20); |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 96 | ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 97 | if (ret_val) |
| 98 | goto out; |
| 99 | |
| 100 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
| 101 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); |
| 102 | |
| 103 | out: |
| 104 | return ret_val; |
| 105 | } |
| 106 | |
| 107 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 108 | * igb_phy_reset_dsp - Reset PHY DSP |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 109 | * @hw: pointer to the HW structure |
| 110 | * |
| 111 | * Reset the digital signal processor. |
| 112 | **/ |
| 113 | static s32 igb_phy_reset_dsp(struct e1000_hw *hw) |
| 114 | { |
Alexander Duyck | 2553bb2 | 2009-10-05 06:35:42 +0000 | [diff] [blame] | 115 | s32 ret_val = 0; |
| 116 | |
| 117 | if (!(hw->phy.ops.write_reg)) |
| 118 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 119 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 120 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 121 | if (ret_val) |
| 122 | goto out; |
| 123 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 124 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 125 | |
| 126 | out: |
| 127 | return ret_val; |
| 128 | } |
| 129 | |
| 130 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 131 | * igb_read_phy_reg_mdic - Read MDI control register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 132 | * @hw: pointer to the HW structure |
| 133 | * @offset: register offset to be read |
| 134 | * @data: pointer to the read data |
| 135 | * |
| 136 | * Reads the MDI control regsiter in the PHY at offset and stores the |
| 137 | * information read to data. |
| 138 | **/ |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 139 | s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 140 | { |
| 141 | struct e1000_phy_info *phy = &hw->phy; |
| 142 | u32 i, mdic = 0; |
| 143 | s32 ret_val = 0; |
| 144 | |
| 145 | if (offset > MAX_PHY_REG_ADDRESS) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 146 | hw_dbg("PHY Address %d is out of range\n", offset); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 147 | ret_val = -E1000_ERR_PARAM; |
| 148 | goto out; |
| 149 | } |
| 150 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 151 | /* Set up Op-code, Phy Address, and register offset in the MDI |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 152 | * Control register. The MAC will take care of interfacing with the |
| 153 | * PHY to retrieve the desired data. |
| 154 | */ |
| 155 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | |
| 156 | (phy->addr << E1000_MDIC_PHY_SHIFT) | |
| 157 | (E1000_MDIC_OP_READ)); |
| 158 | |
| 159 | wr32(E1000_MDIC, mdic); |
| 160 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 161 | /* Poll the ready bit to see if the MDI read completed |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 162 | * Increasing the time out as testing showed failures with |
| 163 | * the lower time out |
| 164 | */ |
| 165 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
| 166 | udelay(50); |
| 167 | mdic = rd32(E1000_MDIC); |
| 168 | if (mdic & E1000_MDIC_READY) |
| 169 | break; |
| 170 | } |
| 171 | if (!(mdic & E1000_MDIC_READY)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 172 | hw_dbg("MDI Read did not complete\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 173 | ret_val = -E1000_ERR_PHY; |
| 174 | goto out; |
| 175 | } |
| 176 | if (mdic & E1000_MDIC_ERROR) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 177 | hw_dbg("MDI Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 178 | ret_val = -E1000_ERR_PHY; |
| 179 | goto out; |
| 180 | } |
| 181 | *data = (u16) mdic; |
| 182 | |
| 183 | out: |
| 184 | return ret_val; |
| 185 | } |
| 186 | |
| 187 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 188 | * igb_write_phy_reg_mdic - Write MDI control register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 189 | * @hw: pointer to the HW structure |
| 190 | * @offset: register offset to write to |
| 191 | * @data: data to write to register at offset |
| 192 | * |
| 193 | * Writes data to MDI control register in the PHY at offset. |
| 194 | **/ |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 195 | s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 196 | { |
| 197 | struct e1000_phy_info *phy = &hw->phy; |
| 198 | u32 i, mdic = 0; |
| 199 | s32 ret_val = 0; |
| 200 | |
| 201 | if (offset > MAX_PHY_REG_ADDRESS) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 202 | hw_dbg("PHY Address %d is out of range\n", offset); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 203 | ret_val = -E1000_ERR_PARAM; |
| 204 | goto out; |
| 205 | } |
| 206 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 207 | /* Set up Op-code, Phy Address, and register offset in the MDI |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 208 | * Control register. The MAC will take care of interfacing with the |
| 209 | * PHY to retrieve the desired data. |
| 210 | */ |
| 211 | mdic = (((u32)data) | |
| 212 | (offset << E1000_MDIC_REG_SHIFT) | |
| 213 | (phy->addr << E1000_MDIC_PHY_SHIFT) | |
| 214 | (E1000_MDIC_OP_WRITE)); |
| 215 | |
| 216 | wr32(E1000_MDIC, mdic); |
| 217 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 218 | /* Poll the ready bit to see if the MDI read completed |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 219 | * Increasing the time out as testing showed failures with |
| 220 | * the lower time out |
| 221 | */ |
| 222 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
| 223 | udelay(50); |
| 224 | mdic = rd32(E1000_MDIC); |
| 225 | if (mdic & E1000_MDIC_READY) |
| 226 | break; |
| 227 | } |
| 228 | if (!(mdic & E1000_MDIC_READY)) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 229 | hw_dbg("MDI Write did not complete\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 230 | ret_val = -E1000_ERR_PHY; |
| 231 | goto out; |
| 232 | } |
| 233 | if (mdic & E1000_MDIC_ERROR) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 234 | hw_dbg("MDI Error\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 235 | ret_val = -E1000_ERR_PHY; |
| 236 | goto out; |
| 237 | } |
| 238 | |
| 239 | out: |
| 240 | return ret_val; |
| 241 | } |
| 242 | |
| 243 | /** |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 244 | * igb_read_phy_reg_i2c - Read PHY register using i2c |
| 245 | * @hw: pointer to the HW structure |
| 246 | * @offset: register offset to be read |
| 247 | * @data: pointer to the read data |
| 248 | * |
| 249 | * Reads the PHY register at offset using the i2c interface and stores the |
| 250 | * retrieved information in data. |
| 251 | **/ |
| 252 | s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) |
| 253 | { |
| 254 | struct e1000_phy_info *phy = &hw->phy; |
| 255 | u32 i, i2ccmd = 0; |
| 256 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 257 | /* Set up Op-code, Phy Address, and register address in the I2CCMD |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 258 | * register. The MAC will take care of interfacing with the |
| 259 | * PHY to retrieve the desired data. |
| 260 | */ |
| 261 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 262 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | |
| 263 | (E1000_I2CCMD_OPCODE_READ)); |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 264 | |
| 265 | wr32(E1000_I2CCMD, i2ccmd); |
| 266 | |
| 267 | /* Poll the ready bit to see if the I2C read completed */ |
| 268 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { |
| 269 | udelay(50); |
| 270 | i2ccmd = rd32(E1000_I2CCMD); |
| 271 | if (i2ccmd & E1000_I2CCMD_READY) |
| 272 | break; |
| 273 | } |
| 274 | if (!(i2ccmd & E1000_I2CCMD_READY)) { |
| 275 | hw_dbg("I2CCMD Read did not complete\n"); |
| 276 | return -E1000_ERR_PHY; |
| 277 | } |
| 278 | if (i2ccmd & E1000_I2CCMD_ERROR) { |
| 279 | hw_dbg("I2CCMD Error bit set\n"); |
| 280 | return -E1000_ERR_PHY; |
| 281 | } |
| 282 | |
| 283 | /* Need to byte-swap the 16-bit value. */ |
| 284 | *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); |
| 285 | |
| 286 | return 0; |
| 287 | } |
| 288 | |
| 289 | /** |
| 290 | * igb_write_phy_reg_i2c - Write PHY register using i2c |
| 291 | * @hw: pointer to the HW structure |
| 292 | * @offset: register offset to write to |
| 293 | * @data: data to write at register offset |
| 294 | * |
| 295 | * Writes the data to PHY register at the offset using the i2c interface. |
| 296 | **/ |
| 297 | s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) |
| 298 | { |
| 299 | struct e1000_phy_info *phy = &hw->phy; |
| 300 | u32 i, i2ccmd = 0; |
| 301 | u16 phy_data_swapped; |
| 302 | |
Akeem G. Abodunrin | 76d0652 | 2011-09-02 23:11:19 +0000 | [diff] [blame] | 303 | /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ |
| 304 | if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { |
| 305 | hw_dbg("PHY I2C Address %d is out of range.\n", |
| 306 | hw->phy.addr); |
| 307 | return -E1000_ERR_CONFIG; |
| 308 | } |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 309 | |
| 310 | /* Swap the data bytes for the I2C interface */ |
| 311 | phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); |
| 312 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 313 | /* Set up Op-code, Phy Address, and register address in the I2CCMD |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 314 | * register. The MAC will take care of interfacing with the |
| 315 | * PHY to retrieve the desired data. |
| 316 | */ |
| 317 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 318 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | |
| 319 | E1000_I2CCMD_OPCODE_WRITE | |
| 320 | phy_data_swapped); |
Alexander Duyck | bf6f7a9 | 2009-10-05 06:32:27 +0000 | [diff] [blame] | 321 | |
| 322 | wr32(E1000_I2CCMD, i2ccmd); |
| 323 | |
| 324 | /* Poll the ready bit to see if the I2C read completed */ |
| 325 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { |
| 326 | udelay(50); |
| 327 | i2ccmd = rd32(E1000_I2CCMD); |
| 328 | if (i2ccmd & E1000_I2CCMD_READY) |
| 329 | break; |
| 330 | } |
| 331 | if (!(i2ccmd & E1000_I2CCMD_READY)) { |
| 332 | hw_dbg("I2CCMD Write did not complete\n"); |
| 333 | return -E1000_ERR_PHY; |
| 334 | } |
| 335 | if (i2ccmd & E1000_I2CCMD_ERROR) { |
| 336 | hw_dbg("I2CCMD Error bit set\n"); |
| 337 | return -E1000_ERR_PHY; |
| 338 | } |
| 339 | |
| 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 344 | * igb_read_phy_reg_igp - Read igp PHY register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 345 | * @hw: pointer to the HW structure |
| 346 | * @offset: register offset to be read |
| 347 | * @data: pointer to the read data |
| 348 | * |
| 349 | * Acquires semaphore, if necessary, then reads the PHY register at offset |
| 350 | * and storing the retrieved information in data. Release any acquired |
| 351 | * semaphores before exiting. |
| 352 | **/ |
| 353 | s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) |
| 354 | { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 355 | s32 ret_val = 0; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 356 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 357 | if (!(hw->phy.ops.acquire)) |
| 358 | goto out; |
| 359 | |
| 360 | ret_val = hw->phy.ops.acquire(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 361 | if (ret_val) |
| 362 | goto out; |
| 363 | |
| 364 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
| 365 | ret_val = igb_write_phy_reg_mdic(hw, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 366 | IGP01E1000_PHY_PAGE_SELECT, |
| 367 | (u16)offset); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 368 | if (ret_val) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 369 | hw->phy.ops.release(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 370 | goto out; |
| 371 | } |
| 372 | } |
| 373 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 374 | ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
| 375 | data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 376 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 377 | hw->phy.ops.release(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 378 | |
| 379 | out: |
| 380 | return ret_val; |
| 381 | } |
| 382 | |
| 383 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 384 | * igb_write_phy_reg_igp - Write igp PHY register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 385 | * @hw: pointer to the HW structure |
| 386 | * @offset: register offset to write to |
| 387 | * @data: data to write at register offset |
| 388 | * |
| 389 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 390 | * at the offset. Release any acquired semaphores before exiting. |
| 391 | **/ |
| 392 | s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) |
| 393 | { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 394 | s32 ret_val = 0; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 395 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 396 | if (!(hw->phy.ops.acquire)) |
| 397 | goto out; |
| 398 | |
| 399 | ret_val = hw->phy.ops.acquire(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 400 | if (ret_val) |
| 401 | goto out; |
| 402 | |
| 403 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
| 404 | ret_val = igb_write_phy_reg_mdic(hw, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 405 | IGP01E1000_PHY_PAGE_SELECT, |
| 406 | (u16)offset); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 407 | if (ret_val) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 408 | hw->phy.ops.release(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 409 | goto out; |
| 410 | } |
| 411 | } |
| 412 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 413 | ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 414 | data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 415 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 416 | hw->phy.ops.release(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 417 | |
| 418 | out: |
| 419 | return ret_val; |
| 420 | } |
| 421 | |
| 422 | /** |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 423 | * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link |
| 424 | * @hw: pointer to the HW structure |
| 425 | * |
| 426 | * Sets up Carrier-sense on Transmit and downshift values. |
| 427 | **/ |
| 428 | s32 igb_copper_link_setup_82580(struct e1000_hw *hw) |
| 429 | { |
| 430 | struct e1000_phy_info *phy = &hw->phy; |
| 431 | s32 ret_val; |
| 432 | u16 phy_data; |
| 433 | |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 434 | if (phy->reset_disable) { |
| 435 | ret_val = 0; |
| 436 | goto out; |
| 437 | } |
| 438 | |
| 439 | if (phy->type == e1000_phy_82580) { |
| 440 | ret_val = hw->phy.ops.reset(hw); |
| 441 | if (ret_val) { |
| 442 | hw_dbg("Error resetting the PHY.\n"); |
| 443 | goto out; |
| 444 | } |
| 445 | } |
| 446 | |
| 447 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
| 448 | ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); |
| 449 | if (ret_val) |
| 450 | goto out; |
| 451 | |
| 452 | phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; |
| 453 | |
| 454 | /* Enable downshift */ |
| 455 | phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; |
| 456 | |
| 457 | ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); |
Jesse Brandeburg | 1b55678 | 2012-07-26 02:31:04 +0000 | [diff] [blame] | 458 | if (ret_val) |
| 459 | goto out; |
| 460 | |
| 461 | /* Set MDI/MDIX mode */ |
| 462 | ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); |
| 463 | if (ret_val) |
| 464 | goto out; |
| 465 | phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 466 | /* Options: |
Jesse Brandeburg | 1b55678 | 2012-07-26 02:31:04 +0000 | [diff] [blame] | 467 | * 0 - Auto (default) |
| 468 | * 1 - MDI mode |
| 469 | * 2 - MDI-X mode |
| 470 | */ |
| 471 | switch (hw->phy.mdix) { |
| 472 | case 1: |
| 473 | break; |
| 474 | case 2: |
| 475 | phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX; |
| 476 | break; |
| 477 | case 0: |
| 478 | default: |
| 479 | phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX; |
| 480 | break; |
| 481 | } |
| 482 | ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 483 | |
| 484 | out: |
| 485 | return ret_val; |
| 486 | } |
| 487 | |
| 488 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 489 | * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 490 | * @hw: pointer to the HW structure |
| 491 | * |
| 492 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock |
| 493 | * and downshift values are set also. |
| 494 | **/ |
| 495 | s32 igb_copper_link_setup_m88(struct e1000_hw *hw) |
| 496 | { |
| 497 | struct e1000_phy_info *phy = &hw->phy; |
| 498 | s32 ret_val; |
| 499 | u16 phy_data; |
| 500 | |
| 501 | if (phy->reset_disable) { |
| 502 | ret_val = 0; |
| 503 | goto out; |
| 504 | } |
| 505 | |
| 506 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 507 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 508 | if (ret_val) |
| 509 | goto out; |
| 510 | |
| 511 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
| 512 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 513 | /* Options: |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 514 | * MDI/MDI-X = 0 (default) |
| 515 | * 0 - Auto for all speeds |
| 516 | * 1 - MDI mode |
| 517 | * 2 - MDI-X mode |
| 518 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
| 519 | */ |
| 520 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 521 | |
| 522 | switch (phy->mdix) { |
| 523 | case 1: |
| 524 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
| 525 | break; |
| 526 | case 2: |
| 527 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
| 528 | break; |
| 529 | case 3: |
| 530 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
| 531 | break; |
| 532 | case 0: |
| 533 | default: |
| 534 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
| 535 | break; |
| 536 | } |
| 537 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 538 | /* Options: |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 539 | * disable_polarity_correction = 0 (default) |
| 540 | * Automatic Correction for Reversed Cable Polarity |
| 541 | * 0 - Disabled |
| 542 | * 1 - Enabled |
| 543 | */ |
| 544 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
| 545 | if (phy->disable_polarity_correction == 1) |
| 546 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
| 547 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 548 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 549 | if (ret_val) |
| 550 | goto out; |
| 551 | |
| 552 | if (phy->revision < E1000_REVISION_4) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 553 | /* Force TX_CLK in the Extended PHY Specific Control Register |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 554 | * to 25MHz clock. |
| 555 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 556 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 557 | &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 558 | if (ret_val) |
| 559 | goto out; |
| 560 | |
| 561 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 562 | |
| 563 | if ((phy->revision == E1000_REVISION_2) && |
| 564 | (phy->id == M88E1111_I_PHY_ID)) { |
| 565 | /* 82573L PHY - set the downshift counter to 5x. */ |
| 566 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; |
| 567 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
| 568 | } else { |
| 569 | /* Configure Master and Slave downshift values */ |
| 570 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
| 571 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
| 572 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
| 573 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
| 574 | } |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 575 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 576 | phy_data); |
| 577 | if (ret_val) |
| 578 | goto out; |
| 579 | } |
| 580 | |
| 581 | /* Commit the changes. */ |
| 582 | ret_val = igb_phy_sw_reset(hw); |
| 583 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 584 | hw_dbg("Error committing the PHY changes\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 585 | goto out; |
| 586 | } |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 587 | if (phy->type == e1000_phy_i210) { |
| 588 | ret_val = igb_set_master_slave_mode(hw); |
| 589 | if (ret_val) |
| 590 | return ret_val; |
| 591 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 592 | |
| 593 | out: |
| 594 | return ret_val; |
| 595 | } |
| 596 | |
| 597 | /** |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 598 | * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link |
| 599 | * @hw: pointer to the HW structure |
| 600 | * |
| 601 | * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. |
| 602 | * Also enables and sets the downshift parameters. |
| 603 | **/ |
| 604 | s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) |
| 605 | { |
| 606 | struct e1000_phy_info *phy = &hw->phy; |
| 607 | s32 ret_val; |
| 608 | u16 phy_data; |
| 609 | |
| 610 | if (phy->reset_disable) { |
| 611 | ret_val = 0; |
| 612 | goto out; |
| 613 | } |
| 614 | |
| 615 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
| 616 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 617 | if (ret_val) |
| 618 | goto out; |
| 619 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 620 | /* Options: |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 621 | * MDI/MDI-X = 0 (default) |
| 622 | * 0 - Auto for all speeds |
| 623 | * 1 - MDI mode |
| 624 | * 2 - MDI-X mode |
| 625 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
| 626 | */ |
| 627 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 628 | |
| 629 | switch (phy->mdix) { |
| 630 | case 1: |
| 631 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
| 632 | break; |
| 633 | case 2: |
| 634 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
| 635 | break; |
| 636 | case 3: |
| 637 | /* M88E1112 does not support this mode) */ |
| 638 | if (phy->id != M88E1112_E_PHY_ID) { |
| 639 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
| 640 | break; |
| 641 | } |
| 642 | case 0: |
| 643 | default: |
| 644 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
| 645 | break; |
| 646 | } |
| 647 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 648 | /* Options: |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 649 | * disable_polarity_correction = 0 (default) |
| 650 | * Automatic Correction for Reversed Cable Polarity |
| 651 | * 0 - Disabled |
| 652 | * 1 - Enabled |
| 653 | */ |
| 654 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
| 655 | if (phy->disable_polarity_correction == 1) |
| 656 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
| 657 | |
| 658 | /* Enable downshift and setting it to X6 */ |
| 659 | phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; |
| 660 | phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; |
| 661 | phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; |
| 662 | |
| 663 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 664 | if (ret_val) |
| 665 | goto out; |
| 666 | |
| 667 | /* Commit the changes. */ |
| 668 | ret_val = igb_phy_sw_reset(hw); |
| 669 | if (ret_val) { |
| 670 | hw_dbg("Error committing the PHY changes\n"); |
| 671 | goto out; |
| 672 | } |
| 673 | |
| 674 | out: |
| 675 | return ret_val; |
| 676 | } |
| 677 | |
| 678 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 679 | * igb_copper_link_setup_igp - Setup igp PHY's for copper link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 680 | * @hw: pointer to the HW structure |
| 681 | * |
| 682 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for |
| 683 | * igp PHY's. |
| 684 | **/ |
| 685 | s32 igb_copper_link_setup_igp(struct e1000_hw *hw) |
| 686 | { |
| 687 | struct e1000_phy_info *phy = &hw->phy; |
| 688 | s32 ret_val; |
| 689 | u16 data; |
| 690 | |
| 691 | if (phy->reset_disable) { |
| 692 | ret_val = 0; |
| 693 | goto out; |
| 694 | } |
| 695 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 696 | ret_val = phy->ops.reset(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 697 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 698 | hw_dbg("Error resetting the PHY.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 699 | goto out; |
| 700 | } |
| 701 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 702 | /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid |
Alexander Duyck | a6a6056 | 2009-03-31 20:38:38 +0000 | [diff] [blame] | 703 | * timeout issues when LFS is enabled. |
| 704 | */ |
| 705 | msleep(100); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 706 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 707 | /* The NVM settings will configure LPLU in D3 for |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 708 | * non-IGP1 PHYs. |
| 709 | */ |
| 710 | if (phy->type == e1000_phy_igp) { |
| 711 | /* disable lplu d3 during driver init */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 712 | if (phy->ops.set_d3_lplu_state) |
| 713 | ret_val = phy->ops.set_d3_lplu_state(hw, false); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 714 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 715 | hw_dbg("Error Disabling LPLU D3\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 716 | goto out; |
| 717 | } |
| 718 | } |
| 719 | |
| 720 | /* disable lplu d0 during driver init */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 721 | ret_val = phy->ops.set_d0_lplu_state(hw, false); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 722 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 723 | hw_dbg("Error Disabling LPLU D0\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 724 | goto out; |
| 725 | } |
| 726 | /* Configure mdi-mdix settings */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 727 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 728 | if (ret_val) |
| 729 | goto out; |
| 730 | |
| 731 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 732 | |
| 733 | switch (phy->mdix) { |
| 734 | case 1: |
| 735 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 736 | break; |
| 737 | case 2: |
| 738 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 739 | break; |
| 740 | case 0: |
| 741 | default: |
| 742 | data |= IGP01E1000_PSCR_AUTO_MDIX; |
| 743 | break; |
| 744 | } |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 745 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 746 | if (ret_val) |
| 747 | goto out; |
| 748 | |
| 749 | /* set auto-master slave resolution settings */ |
| 750 | if (hw->mac.autoneg) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 751 | /* when autonegotiation advertisement is only 1000Mbps then we |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 752 | * should disable SmartSpeed and enable Auto MasterSlave |
| 753 | * resolution as hardware default. |
| 754 | */ |
| 755 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
| 756 | /* Disable SmartSpeed */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 757 | ret_val = phy->ops.read_reg(hw, |
| 758 | IGP01E1000_PHY_PORT_CONFIG, |
| 759 | &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 760 | if (ret_val) |
| 761 | goto out; |
| 762 | |
| 763 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 764 | ret_val = phy->ops.write_reg(hw, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 765 | IGP01E1000_PHY_PORT_CONFIG, |
| 766 | data); |
| 767 | if (ret_val) |
| 768 | goto out; |
| 769 | |
| 770 | /* Set auto Master/Slave resolution process */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 771 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 772 | if (ret_val) |
| 773 | goto out; |
| 774 | |
| 775 | data &= ~CR_1000T_MS_ENABLE; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 776 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 777 | if (ret_val) |
| 778 | goto out; |
| 779 | } |
| 780 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 781 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 782 | if (ret_val) |
| 783 | goto out; |
| 784 | |
| 785 | /* load defaults for future use */ |
| 786 | phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? |
| 787 | ((data & CR_1000T_MS_VALUE) ? |
| 788 | e1000_ms_force_master : |
| 789 | e1000_ms_force_slave) : |
| 790 | e1000_ms_auto; |
| 791 | |
| 792 | switch (phy->ms_type) { |
| 793 | case e1000_ms_force_master: |
| 794 | data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
| 795 | break; |
| 796 | case e1000_ms_force_slave: |
| 797 | data |= CR_1000T_MS_ENABLE; |
| 798 | data &= ~(CR_1000T_MS_VALUE); |
| 799 | break; |
| 800 | case e1000_ms_auto: |
| 801 | data &= ~CR_1000T_MS_ENABLE; |
| 802 | default: |
| 803 | break; |
| 804 | } |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 805 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 806 | if (ret_val) |
| 807 | goto out; |
| 808 | } |
| 809 | |
| 810 | out: |
| 811 | return ret_val; |
| 812 | } |
| 813 | |
| 814 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 815 | * igb_copper_link_autoneg - Setup/Enable autoneg for copper link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 816 | * @hw: pointer to the HW structure |
| 817 | * |
| 818 | * Performs initial bounds checking on autoneg advertisement parameter, then |
| 819 | * configure to advertise the full capability. Setup the PHY to autoneg |
| 820 | * and restart the negotiation process between the link partner. If |
| 821 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
| 822 | **/ |
Alexander Duyck | 81fadd8 | 2009-10-05 06:35:03 +0000 | [diff] [blame] | 823 | static s32 igb_copper_link_autoneg(struct e1000_hw *hw) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 824 | { |
| 825 | struct e1000_phy_info *phy = &hw->phy; |
| 826 | s32 ret_val; |
| 827 | u16 phy_ctrl; |
| 828 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 829 | /* Perform some bounds checking on the autoneg advertisement |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 830 | * parameter. |
| 831 | */ |
| 832 | phy->autoneg_advertised &= phy->autoneg_mask; |
| 833 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 834 | /* If autoneg_advertised is zero, we assume it was not defaulted |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 835 | * by the calling code so we set to advertise full capability. |
| 836 | */ |
| 837 | if (phy->autoneg_advertised == 0) |
| 838 | phy->autoneg_advertised = phy->autoneg_mask; |
| 839 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 840 | hw_dbg("Reconfiguring auto-neg advertisement params\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 841 | ret_val = igb_phy_setup_autoneg(hw); |
| 842 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 843 | hw_dbg("Error Setting up Auto-Negotiation\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 844 | goto out; |
| 845 | } |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 846 | hw_dbg("Restarting Auto-Neg\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 847 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 848 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 849 | * the Auto Neg Restart bit in the PHY control register. |
| 850 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 851 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 852 | if (ret_val) |
| 853 | goto out; |
| 854 | |
| 855 | phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 856 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 857 | if (ret_val) |
| 858 | goto out; |
| 859 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 860 | /* Does the user want to wait for Auto-Neg to complete here, or |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 861 | * check at a later time (for example, callback routine). |
| 862 | */ |
| 863 | if (phy->autoneg_wait_to_complete) { |
| 864 | ret_val = igb_wait_autoneg(hw); |
| 865 | if (ret_val) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 866 | hw_dbg("Error while waiting for " |
| 867 | "autoneg to complete\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 868 | goto out; |
| 869 | } |
| 870 | } |
| 871 | |
| 872 | hw->mac.get_link_status = true; |
| 873 | |
| 874 | out: |
| 875 | return ret_val; |
| 876 | } |
| 877 | |
| 878 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 879 | * igb_phy_setup_autoneg - Configure PHY for auto-negotiation |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 880 | * @hw: pointer to the HW structure |
| 881 | * |
| 882 | * Reads the MII auto-neg advertisement register and/or the 1000T control |
| 883 | * register and if the PHY is already setup for auto-negotiation, then |
| 884 | * return successful. Otherwise, setup advertisement and flow control to |
| 885 | * the appropriate values for the wanted auto-negotiation. |
| 886 | **/ |
| 887 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) |
| 888 | { |
| 889 | struct e1000_phy_info *phy = &hw->phy; |
| 890 | s32 ret_val; |
| 891 | u16 mii_autoneg_adv_reg; |
| 892 | u16 mii_1000t_ctrl_reg = 0; |
| 893 | |
| 894 | phy->autoneg_advertised &= phy->autoneg_mask; |
| 895 | |
| 896 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 897 | ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 898 | if (ret_val) |
| 899 | goto out; |
| 900 | |
| 901 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { |
| 902 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 903 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 904 | &mii_1000t_ctrl_reg); |
| 905 | if (ret_val) |
| 906 | goto out; |
| 907 | } |
| 908 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 909 | /* Need to parse both autoneg_advertised and fc and set up |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 910 | * the appropriate PHY registers. First we will parse for |
| 911 | * autoneg_advertised software override. Since we can advertise |
| 912 | * a plethora of combinations, we need to check each bit |
| 913 | * individually. |
| 914 | */ |
| 915 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 916 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 917 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
| 918 | * the 1000Base-T Control Register (Address 9). |
| 919 | */ |
| 920 | mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | |
| 921 | NWAY_AR_100TX_HD_CAPS | |
| 922 | NWAY_AR_10T_FD_CAPS | |
| 923 | NWAY_AR_10T_HD_CAPS); |
| 924 | mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); |
| 925 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 926 | hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 927 | |
| 928 | /* Do we want to advertise 10 Mb Half Duplex? */ |
| 929 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 930 | hw_dbg("Advertise 10mb Half duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 931 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
| 932 | } |
| 933 | |
| 934 | /* Do we want to advertise 10 Mb Full Duplex? */ |
| 935 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 936 | hw_dbg("Advertise 10mb Full duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 937 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
| 938 | } |
| 939 | |
| 940 | /* Do we want to advertise 100 Mb Half Duplex? */ |
| 941 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 942 | hw_dbg("Advertise 100mb Half duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 943 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
| 944 | } |
| 945 | |
| 946 | /* Do we want to advertise 100 Mb Full Duplex? */ |
| 947 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 948 | hw_dbg("Advertise 100mb Full duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 949 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
| 950 | } |
| 951 | |
| 952 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
| 953 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 954 | hw_dbg("Advertise 1000mb Half duplex request denied!\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 955 | |
| 956 | /* Do we want to advertise 1000 Mb Full Duplex? */ |
| 957 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 958 | hw_dbg("Advertise 1000mb Full duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 959 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
| 960 | } |
| 961 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 962 | /* Check for a software override of the flow control settings, and |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 963 | * setup the PHY advertisement registers accordingly. If |
| 964 | * auto-negotiation is enabled, then software will have to set the |
| 965 | * "PAUSE" bits to the correct value in the Auto-Negotiation |
| 966 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- |
| 967 | * negotiation. |
| 968 | * |
| 969 | * The possible values of the "fc" parameter are: |
| 970 | * 0: Flow control is completely disabled |
| 971 | * 1: Rx flow control is enabled (we can receive pause frames |
| 972 | * but not send pause frames). |
| 973 | * 2: Tx flow control is enabled (we can send pause frames |
| 974 | * but we do not support receiving pause frames). |
| 975 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
| 976 | * other: No software override. The flow control configuration |
| 977 | * in the EEPROM is used. |
| 978 | */ |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 979 | switch (hw->fc.current_mode) { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 980 | case e1000_fc_none: |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 981 | /* Flow control (RX & TX) is completely disabled by a |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 982 | * software over-ride. |
| 983 | */ |
| 984 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 985 | break; |
| 986 | case e1000_fc_rx_pause: |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 987 | /* RX Flow control is enabled, and TX Flow control is |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 988 | * disabled, by a software over-ride. |
| 989 | * |
| 990 | * Since there really isn't a way to advertise that we are |
| 991 | * capable of RX Pause ONLY, we will advertise that we |
| 992 | * support both symmetric and asymmetric RX PAUSE. Later |
| 993 | * (in e1000_config_fc_after_link_up) we will disable the |
| 994 | * hw's ability to send PAUSE frames. |
| 995 | */ |
| 996 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 997 | break; |
| 998 | case e1000_fc_tx_pause: |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 999 | /* TX Flow control is enabled, and RX Flow control is |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1000 | * disabled, by a software over-ride. |
| 1001 | */ |
| 1002 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
| 1003 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
| 1004 | break; |
| 1005 | case e1000_fc_full: |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1006 | /* Flow control (both RX and TX) is enabled by a software |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1007 | * over-ride. |
| 1008 | */ |
| 1009 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 1010 | break; |
| 1011 | default: |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1012 | hw_dbg("Flow control param set incorrectly\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1013 | ret_val = -E1000_ERR_CONFIG; |
| 1014 | goto out; |
| 1015 | } |
| 1016 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1017 | ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1018 | if (ret_val) |
| 1019 | goto out; |
| 1020 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1021 | hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1022 | |
| 1023 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1024 | ret_val = phy->ops.write_reg(hw, |
| 1025 | PHY_1000T_CTRL, |
| 1026 | mii_1000t_ctrl_reg); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1027 | if (ret_val) |
| 1028 | goto out; |
| 1029 | } |
| 1030 | |
| 1031 | out: |
| 1032 | return ret_val; |
| 1033 | } |
| 1034 | |
| 1035 | /** |
Alexander Duyck | 81fadd8 | 2009-10-05 06:35:03 +0000 | [diff] [blame] | 1036 | * igb_setup_copper_link - Configure copper link settings |
| 1037 | * @hw: pointer to the HW structure |
| 1038 | * |
| 1039 | * Calls the appropriate function to configure the link for auto-neg or forced |
| 1040 | * speed and duplex. Then we check for link, once link is established calls |
| 1041 | * to configure collision distance and flow control are called. If link is |
| 1042 | * not established, we return -E1000_ERR_PHY (-2). |
| 1043 | **/ |
| 1044 | s32 igb_setup_copper_link(struct e1000_hw *hw) |
| 1045 | { |
| 1046 | s32 ret_val; |
| 1047 | bool link; |
| 1048 | |
Alexander Duyck | 81fadd8 | 2009-10-05 06:35:03 +0000 | [diff] [blame] | 1049 | if (hw->mac.autoneg) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1050 | /* Setup autoneg and flow control advertisement and perform |
Alexander Duyck | 81fadd8 | 2009-10-05 06:35:03 +0000 | [diff] [blame] | 1051 | * autonegotiation. |
| 1052 | */ |
| 1053 | ret_val = igb_copper_link_autoneg(hw); |
| 1054 | if (ret_val) |
| 1055 | goto out; |
| 1056 | } else { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1057 | /* PHY will be set to 10H, 10F, 100H or 100F |
Alexander Duyck | 81fadd8 | 2009-10-05 06:35:03 +0000 | [diff] [blame] | 1058 | * depending on user settings. |
| 1059 | */ |
| 1060 | hw_dbg("Forcing Speed and Duplex\n"); |
| 1061 | ret_val = hw->phy.ops.force_speed_duplex(hw); |
| 1062 | if (ret_val) { |
| 1063 | hw_dbg("Error Forcing Speed and Duplex\n"); |
| 1064 | goto out; |
| 1065 | } |
| 1066 | } |
| 1067 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1068 | /* Check link status. Wait up to 100 microseconds for link to become |
Alexander Duyck | 81fadd8 | 2009-10-05 06:35:03 +0000 | [diff] [blame] | 1069 | * valid. |
| 1070 | */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1071 | ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); |
Alexander Duyck | 81fadd8 | 2009-10-05 06:35:03 +0000 | [diff] [blame] | 1072 | if (ret_val) |
| 1073 | goto out; |
| 1074 | |
| 1075 | if (link) { |
| 1076 | hw_dbg("Valid link established!!!\n"); |
| 1077 | igb_config_collision_dist(hw); |
| 1078 | ret_val = igb_config_fc_after_link_up(hw); |
| 1079 | } else { |
| 1080 | hw_dbg("Unable to establish link!!!\n"); |
| 1081 | } |
| 1082 | |
| 1083 | out: |
| 1084 | return ret_val; |
| 1085 | } |
| 1086 | |
| 1087 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1088 | * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1089 | * @hw: pointer to the HW structure |
| 1090 | * |
| 1091 | * Calls the PHY setup function to force speed and duplex. Clears the |
| 1092 | * auto-crossover to force MDI manually. Waits for link and returns |
| 1093 | * successful if link up is successful, else -E1000_ERR_PHY (-2). |
| 1094 | **/ |
| 1095 | s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) |
| 1096 | { |
| 1097 | struct e1000_phy_info *phy = &hw->phy; |
| 1098 | s32 ret_val; |
| 1099 | u16 phy_data; |
| 1100 | bool link; |
| 1101 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1102 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1103 | if (ret_val) |
| 1104 | goto out; |
| 1105 | |
| 1106 | igb_phy_force_speed_duplex_setup(hw, &phy_data); |
| 1107 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1108 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1109 | if (ret_val) |
| 1110 | goto out; |
| 1111 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1112 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1113 | * forced whenever speed and duplex are forced. |
| 1114 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1115 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1116 | if (ret_val) |
| 1117 | goto out; |
| 1118 | |
| 1119 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 1120 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 1121 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1122 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1123 | if (ret_val) |
| 1124 | goto out; |
| 1125 | |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1126 | hw_dbg("IGP PSCR: %X\n", phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1127 | |
| 1128 | udelay(1); |
| 1129 | |
| 1130 | if (phy->autoneg_wait_to_complete) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1131 | hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1132 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1133 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1134 | if (ret_val) |
| 1135 | goto out; |
| 1136 | |
| 1137 | if (!link) |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1138 | hw_dbg("Link taking longer than expected.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1139 | |
| 1140 | /* Try once more */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1141 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1142 | if (ret_val) |
| 1143 | goto out; |
| 1144 | } |
| 1145 | |
| 1146 | out: |
| 1147 | return ret_val; |
| 1148 | } |
| 1149 | |
| 1150 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1151 | * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1152 | * @hw: pointer to the HW structure |
| 1153 | * |
| 1154 | * Calls the PHY setup function to force speed and duplex. Clears the |
| 1155 | * auto-crossover to force MDI manually. Resets the PHY to commit the |
| 1156 | * changes. If time expires while waiting for link up, we reset the DSP. |
| 1157 | * After reset, TX_CLK and CRS on TX must be set. Return successful upon |
| 1158 | * successful completion, else return corresponding error code. |
| 1159 | **/ |
| 1160 | s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) |
| 1161 | { |
| 1162 | struct e1000_phy_info *phy = &hw->phy; |
| 1163 | s32 ret_val; |
| 1164 | u16 phy_data; |
| 1165 | bool link; |
| 1166 | |
Matthew Vick | 9f0b851 | 2012-10-16 07:44:45 +0000 | [diff] [blame] | 1167 | /* I210 and I211 devices support Auto-Crossover in forced operation. */ |
| 1168 | if (phy->type != e1000_phy_i210) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1169 | /* Clear Auto-Crossover to force MDI manually. M88E1000 |
Matthew Vick | 9f0b851 | 2012-10-16 07:44:45 +0000 | [diff] [blame] | 1170 | * requires MDI forced whenever speed and duplex are forced. |
| 1171 | */ |
| 1172 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, |
| 1173 | &phy_data); |
| 1174 | if (ret_val) |
| 1175 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1176 | |
Matthew Vick | 9f0b851 | 2012-10-16 07:44:45 +0000 | [diff] [blame] | 1177 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 1178 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, |
| 1179 | phy_data); |
| 1180 | if (ret_val) |
| 1181 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1182 | |
Matthew Vick | 9f0b851 | 2012-10-16 07:44:45 +0000 | [diff] [blame] | 1183 | hw_dbg("M88E1000 PSCR: %X\n", phy_data); |
| 1184 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1185 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1186 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1187 | if (ret_val) |
| 1188 | goto out; |
| 1189 | |
| 1190 | igb_phy_force_speed_duplex_setup(hw, &phy_data); |
| 1191 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1192 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1193 | if (ret_val) |
| 1194 | goto out; |
| 1195 | |
Alexander Duyck | 2553bb2 | 2009-10-05 06:35:42 +0000 | [diff] [blame] | 1196 | /* Reset the phy to commit changes. */ |
| 1197 | ret_val = igb_phy_sw_reset(hw); |
| 1198 | if (ret_val) |
| 1199 | goto out; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1200 | |
| 1201 | if (phy->autoneg_wait_to_complete) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1202 | hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1203 | |
Alexander Duyck | 2553bb2 | 2009-10-05 06:35:42 +0000 | [diff] [blame] | 1204 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1205 | if (ret_val) |
| 1206 | goto out; |
| 1207 | |
| 1208 | if (!link) { |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1209 | bool reset_dsp = true; |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1210 | |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1211 | switch (hw->phy.id) { |
| 1212 | case I347AT4_E_PHY_ID: |
| 1213 | case M88E1112_E_PHY_ID: |
| 1214 | case I210_I_PHY_ID: |
| 1215 | reset_dsp = false; |
| 1216 | break; |
| 1217 | default: |
| 1218 | if (hw->phy.type != e1000_phy_m88) |
| 1219 | reset_dsp = false; |
| 1220 | break; |
| 1221 | } |
| 1222 | if (!reset_dsp) |
| 1223 | hw_dbg("Link taking longer than expected.\n"); |
| 1224 | else { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1225 | /* We didn't get link. |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1226 | * Reset the DSP and cross our fingers. |
| 1227 | */ |
| 1228 | ret_val = phy->ops.write_reg(hw, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1229 | M88E1000_PHY_PAGE_SELECT, |
| 1230 | 0x001d); |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1231 | if (ret_val) |
| 1232 | goto out; |
| 1233 | ret_val = igb_phy_reset_dsp(hw); |
| 1234 | if (ret_val) |
| 1235 | goto out; |
| 1236 | } |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1237 | } |
| 1238 | |
| 1239 | /* Try once more */ |
| 1240 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, |
Alexander Duyck | 2553bb2 | 2009-10-05 06:35:42 +0000 | [diff] [blame] | 1241 | 100000, &link); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1242 | if (ret_val) |
| 1243 | goto out; |
| 1244 | } |
| 1245 | |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1246 | if (hw->phy.type != e1000_phy_m88 || |
| 1247 | hw->phy.id == I347AT4_E_PHY_ID || |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1248 | hw->phy.id == M88E1112_E_PHY_ID || |
| 1249 | hw->phy.id == I210_I_PHY_ID) |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1250 | goto out; |
| 1251 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1252 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1253 | if (ret_val) |
| 1254 | goto out; |
| 1255 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1256 | /* Resetting the phy means we need to re-force TX_CLK in the |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1257 | * Extended PHY Specific Control Register to 25MHz clock from |
| 1258 | * the reset value of 2.5MHz. |
| 1259 | */ |
| 1260 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1261 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1262 | if (ret_val) |
| 1263 | goto out; |
| 1264 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1265 | /* In addition, we must re-enable CRS on Tx for both half and full |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1266 | * duplex. |
| 1267 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1268 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1269 | if (ret_val) |
| 1270 | goto out; |
| 1271 | |
| 1272 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1273 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1274 | |
| 1275 | out: |
| 1276 | return ret_val; |
| 1277 | } |
| 1278 | |
| 1279 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1280 | * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1281 | * @hw: pointer to the HW structure |
| 1282 | * @phy_ctrl: pointer to current value of PHY_CONTROL |
| 1283 | * |
| 1284 | * Forces speed and duplex on the PHY by doing the following: disable flow |
| 1285 | * control, force speed/duplex on the MAC, disable auto speed detection, |
| 1286 | * disable auto-negotiation, configure duplex, configure speed, configure |
| 1287 | * the collision distance, write configuration to CTRL register. The |
| 1288 | * caller must write to the PHY_CONTROL register for these settings to |
| 1289 | * take affect. |
| 1290 | **/ |
| 1291 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1292 | u16 *phy_ctrl) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1293 | { |
| 1294 | struct e1000_mac_info *mac = &hw->mac; |
| 1295 | u32 ctrl; |
| 1296 | |
| 1297 | /* Turn off flow control when forcing speed/duplex */ |
Alexander Duyck | 0cce119 | 2009-07-23 18:10:24 +0000 | [diff] [blame] | 1298 | hw->fc.current_mode = e1000_fc_none; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1299 | |
| 1300 | /* Force speed/duplex on the mac */ |
| 1301 | ctrl = rd32(E1000_CTRL); |
| 1302 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 1303 | ctrl &= ~E1000_CTRL_SPD_SEL; |
| 1304 | |
| 1305 | /* Disable Auto Speed Detection */ |
| 1306 | ctrl &= ~E1000_CTRL_ASDE; |
| 1307 | |
| 1308 | /* Disable autoneg on the phy */ |
| 1309 | *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; |
| 1310 | |
| 1311 | /* Forcing Full or Half Duplex? */ |
| 1312 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { |
| 1313 | ctrl &= ~E1000_CTRL_FD; |
| 1314 | *phy_ctrl &= ~MII_CR_FULL_DUPLEX; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1315 | hw_dbg("Half Duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1316 | } else { |
| 1317 | ctrl |= E1000_CTRL_FD; |
| 1318 | *phy_ctrl |= MII_CR_FULL_DUPLEX; |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1319 | hw_dbg("Full Duplex\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1320 | } |
| 1321 | |
| 1322 | /* Forcing 10mb or 100mb? */ |
| 1323 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { |
| 1324 | ctrl |= E1000_CTRL_SPD_100; |
| 1325 | *phy_ctrl |= MII_CR_SPEED_100; |
| 1326 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1327 | hw_dbg("Forcing 100mb\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1328 | } else { |
| 1329 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
| 1330 | *phy_ctrl |= MII_CR_SPEED_10; |
| 1331 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1332 | hw_dbg("Forcing 10mb\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1333 | } |
| 1334 | |
| 1335 | igb_config_collision_dist(hw); |
| 1336 | |
| 1337 | wr32(E1000_CTRL, ctrl); |
| 1338 | } |
| 1339 | |
| 1340 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1341 | * igb_set_d3_lplu_state - Sets low power link up state for D3 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1342 | * @hw: pointer to the HW structure |
| 1343 | * @active: boolean used to enable/disable lplu |
| 1344 | * |
| 1345 | * Success returns 0, Failure returns 1 |
| 1346 | * |
| 1347 | * The low power link up (lplu) state is set to the power management level D3 |
| 1348 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 |
| 1349 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU |
| 1350 | * is used during Dx states where the power conservation is most important. |
| 1351 | * During driver activity, SmartSpeed should be enabled so performance is |
| 1352 | * maintained. |
| 1353 | **/ |
| 1354 | s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) |
| 1355 | { |
| 1356 | struct e1000_phy_info *phy = &hw->phy; |
Alexander Duyck | 2553bb2 | 2009-10-05 06:35:42 +0000 | [diff] [blame] | 1357 | s32 ret_val = 0; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1358 | u16 data; |
| 1359 | |
Alexander Duyck | 2553bb2 | 2009-10-05 06:35:42 +0000 | [diff] [blame] | 1360 | if (!(hw->phy.ops.read_reg)) |
| 1361 | goto out; |
| 1362 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1363 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1364 | if (ret_val) |
| 1365 | goto out; |
| 1366 | |
| 1367 | if (!active) { |
| 1368 | data &= ~IGP02E1000_PM_D3_LPLU; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1369 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1370 | data); |
| 1371 | if (ret_val) |
| 1372 | goto out; |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1373 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1374 | * during Dx states where the power conservation is most |
| 1375 | * important. During driver activity we should enable |
| 1376 | * SmartSpeed, so performance is maintained. |
| 1377 | */ |
| 1378 | if (phy->smart_speed == e1000_smart_speed_on) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1379 | ret_val = phy->ops.read_reg(hw, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1380 | IGP01E1000_PHY_PORT_CONFIG, |
| 1381 | &data); |
| 1382 | if (ret_val) |
| 1383 | goto out; |
| 1384 | |
| 1385 | data |= IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1386 | ret_val = phy->ops.write_reg(hw, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1387 | IGP01E1000_PHY_PORT_CONFIG, |
| 1388 | data); |
| 1389 | if (ret_val) |
| 1390 | goto out; |
| 1391 | } else if (phy->smart_speed == e1000_smart_speed_off) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1392 | ret_val = phy->ops.read_reg(hw, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1393 | IGP01E1000_PHY_PORT_CONFIG, |
| 1394 | &data); |
| 1395 | if (ret_val) |
| 1396 | goto out; |
| 1397 | |
| 1398 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1399 | ret_val = phy->ops.write_reg(hw, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1400 | IGP01E1000_PHY_PORT_CONFIG, |
| 1401 | data); |
| 1402 | if (ret_val) |
| 1403 | goto out; |
| 1404 | } |
| 1405 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || |
| 1406 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || |
| 1407 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { |
| 1408 | data |= IGP02E1000_PM_D3_LPLU; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1409 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1410 | data); |
| 1411 | if (ret_val) |
| 1412 | goto out; |
| 1413 | |
| 1414 | /* When LPLU is enabled, we should disable SmartSpeed */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1415 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1416 | &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1417 | if (ret_val) |
| 1418 | goto out; |
| 1419 | |
| 1420 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1421 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1422 | data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1423 | } |
| 1424 | |
| 1425 | out: |
| 1426 | return ret_val; |
| 1427 | } |
| 1428 | |
| 1429 | /** |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1430 | * igb_check_downshift - Checks whether a downshift in speed occurred |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1431 | * @hw: pointer to the HW structure |
| 1432 | * |
| 1433 | * Success returns 0, Failure returns 1 |
| 1434 | * |
| 1435 | * A downshift is detected by querying the PHY link health. |
| 1436 | **/ |
| 1437 | s32 igb_check_downshift(struct e1000_hw *hw) |
| 1438 | { |
| 1439 | struct e1000_phy_info *phy = &hw->phy; |
| 1440 | s32 ret_val; |
| 1441 | u16 phy_data, offset, mask; |
| 1442 | |
| 1443 | switch (phy->type) { |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1444 | case e1000_phy_i210: |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1445 | case e1000_phy_m88: |
| 1446 | case e1000_phy_gg82563: |
| 1447 | offset = M88E1000_PHY_SPEC_STATUS; |
| 1448 | mask = M88E1000_PSSR_DOWNSHIFT; |
| 1449 | break; |
| 1450 | case e1000_phy_igp_2: |
| 1451 | case e1000_phy_igp: |
| 1452 | case e1000_phy_igp_3: |
| 1453 | offset = IGP01E1000_PHY_LINK_HEALTH; |
| 1454 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; |
| 1455 | break; |
| 1456 | default: |
| 1457 | /* speed downshift not supported */ |
| 1458 | phy->speed_downgraded = false; |
| 1459 | ret_val = 0; |
| 1460 | goto out; |
| 1461 | } |
| 1462 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1463 | ret_val = phy->ops.read_reg(hw, offset, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1464 | |
| 1465 | if (!ret_val) |
| 1466 | phy->speed_downgraded = (phy_data & mask) ? true : false; |
| 1467 | |
| 1468 | out: |
| 1469 | return ret_val; |
| 1470 | } |
| 1471 | |
| 1472 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1473 | * igb_check_polarity_m88 - Checks the polarity. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1474 | * @hw: pointer to the HW structure |
| 1475 | * |
| 1476 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 1477 | * |
| 1478 | * Polarity is determined based on the PHY specific status register. |
| 1479 | **/ |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1480 | s32 igb_check_polarity_m88(struct e1000_hw *hw) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1481 | { |
| 1482 | struct e1000_phy_info *phy = &hw->phy; |
| 1483 | s32 ret_val; |
| 1484 | u16 data; |
| 1485 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1486 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1487 | |
| 1488 | if (!ret_val) |
| 1489 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) |
| 1490 | ? e1000_rev_polarity_reversed |
| 1491 | : e1000_rev_polarity_normal; |
| 1492 | |
| 1493 | return ret_val; |
| 1494 | } |
| 1495 | |
| 1496 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1497 | * igb_check_polarity_igp - Checks the polarity. |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1498 | * @hw: pointer to the HW structure |
| 1499 | * |
| 1500 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 1501 | * |
| 1502 | * Polarity is determined based on the PHY port status register, and the |
| 1503 | * current speed (since there is no polarity at 100Mbps). |
| 1504 | **/ |
| 1505 | static s32 igb_check_polarity_igp(struct e1000_hw *hw) |
| 1506 | { |
| 1507 | struct e1000_phy_info *phy = &hw->phy; |
| 1508 | s32 ret_val; |
| 1509 | u16 data, offset, mask; |
| 1510 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1511 | /* Polarity is determined based on the speed of |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1512 | * our connection. |
| 1513 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1514 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1515 | if (ret_val) |
| 1516 | goto out; |
| 1517 | |
| 1518 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
| 1519 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
| 1520 | offset = IGP01E1000_PHY_PCS_INIT_REG; |
| 1521 | mask = IGP01E1000_PHY_POLARITY_MASK; |
| 1522 | } else { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1523 | /* This really only applies to 10Mbps since |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1524 | * there is no polarity for 100Mbps (always 0). |
| 1525 | */ |
| 1526 | offset = IGP01E1000_PHY_PORT_STATUS; |
| 1527 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; |
| 1528 | } |
| 1529 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1530 | ret_val = phy->ops.read_reg(hw, offset, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1531 | |
| 1532 | if (!ret_val) |
| 1533 | phy->cable_polarity = (data & mask) |
| 1534 | ? e1000_rev_polarity_reversed |
| 1535 | : e1000_rev_polarity_normal; |
| 1536 | |
| 1537 | out: |
| 1538 | return ret_val; |
| 1539 | } |
| 1540 | |
| 1541 | /** |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1542 | * igb_wait_autoneg - Wait for auto-neg completion |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1543 | * @hw: pointer to the HW structure |
| 1544 | * |
| 1545 | * Waits for auto-negotiation to complete or for the auto-negotiation time |
| 1546 | * limit to expire, which ever happens first. |
| 1547 | **/ |
| 1548 | static s32 igb_wait_autoneg(struct e1000_hw *hw) |
| 1549 | { |
| 1550 | s32 ret_val = 0; |
| 1551 | u16 i, phy_status; |
| 1552 | |
| 1553 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ |
| 1554 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1555 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1556 | if (ret_val) |
| 1557 | break; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1558 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1559 | if (ret_val) |
| 1560 | break; |
| 1561 | if (phy_status & MII_SR_AUTONEG_COMPLETE) |
| 1562 | break; |
| 1563 | msleep(100); |
| 1564 | } |
| 1565 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1566 | /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1567 | * has completed. |
| 1568 | */ |
| 1569 | return ret_val; |
| 1570 | } |
| 1571 | |
| 1572 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1573 | * igb_phy_has_link - Polls PHY for link |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1574 | * @hw: pointer to the HW structure |
| 1575 | * @iterations: number of times to poll for link |
| 1576 | * @usec_interval: delay between polling attempts |
| 1577 | * @success: pointer to whether polling was successful or not |
| 1578 | * |
| 1579 | * Polls the PHY status register for link, 'iterations' number of times. |
| 1580 | **/ |
| 1581 | s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1582 | u32 usec_interval, bool *success) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1583 | { |
| 1584 | s32 ret_val = 0; |
| 1585 | u16 i, phy_status; |
| 1586 | |
| 1587 | for (i = 0; i < iterations; i++) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1588 | /* Some PHYs require the PHY_STATUS register to be read |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1589 | * twice due to the link bit being sticky. No harm doing |
| 1590 | * it across the board. |
| 1591 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1592 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
Alexander Duyck | ab57638 | 2009-10-05 06:35:23 +0000 | [diff] [blame] | 1593 | if (ret_val) { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1594 | /* If the first read fails, another entity may have |
Alexander Duyck | ab57638 | 2009-10-05 06:35:23 +0000 | [diff] [blame] | 1595 | * ownership of the resources, wait and try again to |
| 1596 | * see if they have relinquished the resources yet. |
| 1597 | */ |
| 1598 | udelay(usec_interval); |
| 1599 | } |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1600 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1601 | if (ret_val) |
| 1602 | break; |
| 1603 | if (phy_status & MII_SR_LINK_STATUS) |
| 1604 | break; |
| 1605 | if (usec_interval >= 1000) |
| 1606 | mdelay(usec_interval/1000); |
| 1607 | else |
| 1608 | udelay(usec_interval); |
| 1609 | } |
| 1610 | |
| 1611 | *success = (i < iterations) ? true : false; |
| 1612 | |
| 1613 | return ret_val; |
| 1614 | } |
| 1615 | |
| 1616 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1617 | * igb_get_cable_length_m88 - Determine cable length for m88 PHY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1618 | * @hw: pointer to the HW structure |
| 1619 | * |
| 1620 | * Reads the PHY specific status register to retrieve the cable length |
| 1621 | * information. The cable length is determined by averaging the minimum and |
| 1622 | * maximum values to get the "average" cable length. The m88 PHY has four |
| 1623 | * possible cable length values, which are: |
| 1624 | * Register Value Cable Length |
| 1625 | * 0 < 50 meters |
| 1626 | * 1 50 - 80 meters |
| 1627 | * 2 80 - 110 meters |
| 1628 | * 3 110 - 140 meters |
| 1629 | * 4 > 140 meters |
| 1630 | **/ |
| 1631 | s32 igb_get_cable_length_m88(struct e1000_hw *hw) |
| 1632 | { |
| 1633 | struct e1000_phy_info *phy = &hw->phy; |
| 1634 | s32 ret_val; |
| 1635 | u16 phy_data, index; |
| 1636 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1637 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1638 | if (ret_val) |
| 1639 | goto out; |
| 1640 | |
| 1641 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
| 1642 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
Alexander Duyck | 2553bb2 | 2009-10-05 06:35:42 +0000 | [diff] [blame] | 1643 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { |
| 1644 | ret_val = -E1000_ERR_PHY; |
| 1645 | goto out; |
| 1646 | } |
| 1647 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1648 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
Alexander Duyck | 2553bb2 | 2009-10-05 06:35:42 +0000 | [diff] [blame] | 1649 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1650 | |
| 1651 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
| 1652 | |
| 1653 | out: |
| 1654 | return ret_val; |
| 1655 | } |
| 1656 | |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1657 | s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) |
| 1658 | { |
| 1659 | struct e1000_phy_info *phy = &hw->phy; |
| 1660 | s32 ret_val; |
| 1661 | u16 phy_data, phy_data2, index, default_page, is_cm; |
| 1662 | |
| 1663 | switch (hw->phy.id) { |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 1664 | case I210_I_PHY_ID: |
Carolyn Wyborny | 59f3010 | 2012-10-10 04:42:59 +0000 | [diff] [blame] | 1665 | /* Get cable length from PHY Cable Diagnostics Control Reg */ |
| 1666 | ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + |
| 1667 | (I347AT4_PCDL + phy->addr), |
| 1668 | &phy_data); |
| 1669 | if (ret_val) |
| 1670 | return ret_val; |
| 1671 | |
| 1672 | /* Check if the unit of cable length is meters or cm */ |
| 1673 | ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + |
| 1674 | I347AT4_PCDC, &phy_data2); |
| 1675 | if (ret_val) |
| 1676 | return ret_val; |
| 1677 | |
| 1678 | is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); |
| 1679 | |
| 1680 | /* Populate the phy structure with cable length in meters */ |
| 1681 | phy->min_cable_length = phy_data / (is_cm ? 100 : 1); |
| 1682 | phy->max_cable_length = phy_data / (is_cm ? 100 : 1); |
| 1683 | phy->cable_length = phy_data / (is_cm ? 100 : 1); |
| 1684 | break; |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame^] | 1685 | case M88E1545_E_PHY_ID: |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1686 | case I347AT4_E_PHY_ID: |
| 1687 | /* Remember the original page select and set it to 7 */ |
| 1688 | ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, |
| 1689 | &default_page); |
| 1690 | if (ret_val) |
| 1691 | goto out; |
| 1692 | |
| 1693 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); |
| 1694 | if (ret_val) |
| 1695 | goto out; |
| 1696 | |
| 1697 | /* Get cable length from PHY Cable Diagnostics Control Reg */ |
| 1698 | ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), |
| 1699 | &phy_data); |
| 1700 | if (ret_val) |
| 1701 | goto out; |
| 1702 | |
| 1703 | /* Check if the unit of cable length is meters or cm */ |
| 1704 | ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); |
| 1705 | if (ret_val) |
| 1706 | goto out; |
| 1707 | |
Kantecki, Tomasz | d5a0e36 | 2011-10-17 22:06:59 +0000 | [diff] [blame] | 1708 | is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); |
Joseph Gasparakis | 308fb39 | 2010-09-22 17:56:44 +0000 | [diff] [blame] | 1709 | |
| 1710 | /* Populate the phy structure with cable length in meters */ |
| 1711 | phy->min_cable_length = phy_data / (is_cm ? 100 : 1); |
| 1712 | phy->max_cable_length = phy_data / (is_cm ? 100 : 1); |
| 1713 | phy->cable_length = phy_data / (is_cm ? 100 : 1); |
| 1714 | |
| 1715 | /* Reset the page selec to its original value */ |
| 1716 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, |
| 1717 | default_page); |
| 1718 | if (ret_val) |
| 1719 | goto out; |
| 1720 | break; |
| 1721 | case M88E1112_E_PHY_ID: |
| 1722 | /* Remember the original page select and set it to 5 */ |
| 1723 | ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, |
| 1724 | &default_page); |
| 1725 | if (ret_val) |
| 1726 | goto out; |
| 1727 | |
| 1728 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); |
| 1729 | if (ret_val) |
| 1730 | goto out; |
| 1731 | |
| 1732 | ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, |
| 1733 | &phy_data); |
| 1734 | if (ret_val) |
| 1735 | goto out; |
| 1736 | |
| 1737 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
| 1738 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
| 1739 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { |
| 1740 | ret_val = -E1000_ERR_PHY; |
| 1741 | goto out; |
| 1742 | } |
| 1743 | |
| 1744 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
| 1745 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
| 1746 | |
| 1747 | phy->cable_length = (phy->min_cable_length + |
| 1748 | phy->max_cable_length) / 2; |
| 1749 | |
| 1750 | /* Reset the page select to its original value */ |
| 1751 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, |
| 1752 | default_page); |
| 1753 | if (ret_val) |
| 1754 | goto out; |
| 1755 | |
| 1756 | break; |
| 1757 | default: |
| 1758 | ret_val = -E1000_ERR_PHY; |
| 1759 | goto out; |
| 1760 | } |
| 1761 | |
| 1762 | out: |
| 1763 | return ret_val; |
| 1764 | } |
| 1765 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1766 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1767 | * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1768 | * @hw: pointer to the HW structure |
| 1769 | * |
| 1770 | * The automatic gain control (agc) normalizes the amplitude of the |
| 1771 | * received signal, adjusting for the attenuation produced by the |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1772 | * cable. By reading the AGC registers, which represent the |
| 1773 | * combination of coarse and fine gain value, the value can be put |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1774 | * into a lookup table to obtain the approximate cable length |
| 1775 | * for each channel. |
| 1776 | **/ |
| 1777 | s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) |
| 1778 | { |
| 1779 | struct e1000_phy_info *phy = &hw->phy; |
| 1780 | s32 ret_val = 0; |
| 1781 | u16 phy_data, i, agc_value = 0; |
| 1782 | u16 cur_agc_index, max_agc_index = 0; |
| 1783 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; |
Jeff Kirsher | 6674450 | 2010-12-01 19:59:50 +0000 | [diff] [blame] | 1784 | static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1785 | IGP02E1000_PHY_AGC_A, |
| 1786 | IGP02E1000_PHY_AGC_B, |
| 1787 | IGP02E1000_PHY_AGC_C, |
| 1788 | IGP02E1000_PHY_AGC_D |
Jeff Kirsher | 6674450 | 2010-12-01 19:59:50 +0000 | [diff] [blame] | 1789 | }; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1790 | |
| 1791 | /* Read the AGC registers for all channels */ |
| 1792 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1793 | ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1794 | if (ret_val) |
| 1795 | goto out; |
| 1796 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 1797 | /* Getting bits 15:9, which represent the combination of |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1798 | * coarse and fine gain values. The result is a number |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1799 | * that can be put into the lookup table to obtain the |
| 1800 | * approximate cable length. |
| 1801 | */ |
| 1802 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
| 1803 | IGP02E1000_AGC_LENGTH_MASK; |
| 1804 | |
| 1805 | /* Array index bound check. */ |
| 1806 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || |
| 1807 | (cur_agc_index == 0)) { |
| 1808 | ret_val = -E1000_ERR_PHY; |
| 1809 | goto out; |
| 1810 | } |
| 1811 | |
| 1812 | /* Remove min & max AGC values from calculation. */ |
| 1813 | if (e1000_igp_2_cable_length_table[min_agc_index] > |
| 1814 | e1000_igp_2_cable_length_table[cur_agc_index]) |
| 1815 | min_agc_index = cur_agc_index; |
| 1816 | if (e1000_igp_2_cable_length_table[max_agc_index] < |
| 1817 | e1000_igp_2_cable_length_table[cur_agc_index]) |
| 1818 | max_agc_index = cur_agc_index; |
| 1819 | |
| 1820 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; |
| 1821 | } |
| 1822 | |
| 1823 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
| 1824 | e1000_igp_2_cable_length_table[max_agc_index]); |
| 1825 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
| 1826 | |
| 1827 | /* Calculate cable length with the error range of +/- 10 meters. */ |
| 1828 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
| 1829 | (agc_value - IGP02E1000_AGC_RANGE) : 0; |
| 1830 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; |
| 1831 | |
| 1832 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
| 1833 | |
| 1834 | out: |
| 1835 | return ret_val; |
| 1836 | } |
| 1837 | |
| 1838 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1839 | * igb_get_phy_info_m88 - Retrieve PHY information |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1840 | * @hw: pointer to the HW structure |
| 1841 | * |
| 1842 | * Valid for only copper links. Read the PHY status register (sticky read) |
| 1843 | * to verify that link is up. Read the PHY special control register to |
| 1844 | * determine the polarity and 10base-T extended distance. Read the PHY |
| 1845 | * special status register to determine MDI/MDIx and current speed. If |
| 1846 | * speed is 1000, then determine cable length, local and remote receiver. |
| 1847 | **/ |
| 1848 | s32 igb_get_phy_info_m88(struct e1000_hw *hw) |
| 1849 | { |
| 1850 | struct e1000_phy_info *phy = &hw->phy; |
| 1851 | s32 ret_val; |
| 1852 | u16 phy_data; |
| 1853 | bool link; |
| 1854 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1855 | if (phy->media_type != e1000_media_type_copper) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1856 | hw_dbg("Phy info is only valid for copper media\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1857 | ret_val = -E1000_ERR_CONFIG; |
| 1858 | goto out; |
| 1859 | } |
| 1860 | |
| 1861 | ret_val = igb_phy_has_link(hw, 1, 0, &link); |
| 1862 | if (ret_val) |
| 1863 | goto out; |
| 1864 | |
| 1865 | if (!link) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1866 | hw_dbg("Phy info is only valid if link is up\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1867 | ret_val = -E1000_ERR_CONFIG; |
| 1868 | goto out; |
| 1869 | } |
| 1870 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1871 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1872 | if (ret_val) |
| 1873 | goto out; |
| 1874 | |
| 1875 | phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1876 | ? true : false; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1877 | |
| 1878 | ret_val = igb_check_polarity_m88(hw); |
| 1879 | if (ret_val) |
| 1880 | goto out; |
| 1881 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1882 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1883 | if (ret_val) |
| 1884 | goto out; |
| 1885 | |
| 1886 | phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; |
| 1887 | |
| 1888 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1889 | ret_val = phy->ops.get_cable_length(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1890 | if (ret_val) |
| 1891 | goto out; |
| 1892 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1893 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1894 | if (ret_val) |
| 1895 | goto out; |
| 1896 | |
| 1897 | phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) |
| 1898 | ? e1000_1000t_rx_status_ok |
| 1899 | : e1000_1000t_rx_status_not_ok; |
| 1900 | |
| 1901 | phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) |
| 1902 | ? e1000_1000t_rx_status_ok |
| 1903 | : e1000_1000t_rx_status_not_ok; |
| 1904 | } else { |
| 1905 | /* Set values to "undefined" */ |
| 1906 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 1907 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 1908 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 1909 | } |
| 1910 | |
| 1911 | out: |
| 1912 | return ret_val; |
| 1913 | } |
| 1914 | |
| 1915 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1916 | * igb_get_phy_info_igp - Retrieve igp PHY information |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1917 | * @hw: pointer to the HW structure |
| 1918 | * |
| 1919 | * Read PHY status to determine if link is up. If link is up, then |
| 1920 | * set/determine 10base-T extended distance and polarity correction. Read |
| 1921 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
| 1922 | * determine on the cable length, local and remote receiver. |
| 1923 | **/ |
| 1924 | s32 igb_get_phy_info_igp(struct e1000_hw *hw) |
| 1925 | { |
| 1926 | struct e1000_phy_info *phy = &hw->phy; |
| 1927 | s32 ret_val; |
| 1928 | u16 data; |
| 1929 | bool link; |
| 1930 | |
| 1931 | ret_val = igb_phy_has_link(hw, 1, 0, &link); |
| 1932 | if (ret_val) |
| 1933 | goto out; |
| 1934 | |
| 1935 | if (!link) { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 1936 | hw_dbg("Phy info is only valid if link is up\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1937 | ret_val = -E1000_ERR_CONFIG; |
| 1938 | goto out; |
| 1939 | } |
| 1940 | |
| 1941 | phy->polarity_correction = true; |
| 1942 | |
| 1943 | ret_val = igb_check_polarity_igp(hw); |
| 1944 | if (ret_val) |
| 1945 | goto out; |
| 1946 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1947 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1948 | if (ret_val) |
| 1949 | goto out; |
| 1950 | |
| 1951 | phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; |
| 1952 | |
| 1953 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == |
| 1954 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1955 | ret_val = phy->ops.get_cable_length(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1956 | if (ret_val) |
| 1957 | goto out; |
| 1958 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1959 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1960 | if (ret_val) |
| 1961 | goto out; |
| 1962 | |
| 1963 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) |
| 1964 | ? e1000_1000t_rx_status_ok |
| 1965 | : e1000_1000t_rx_status_not_ok; |
| 1966 | |
| 1967 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) |
| 1968 | ? e1000_1000t_rx_status_ok |
| 1969 | : e1000_1000t_rx_status_not_ok; |
| 1970 | } else { |
| 1971 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 1972 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 1973 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 1974 | } |
| 1975 | |
| 1976 | out: |
| 1977 | return ret_val; |
| 1978 | } |
| 1979 | |
| 1980 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 1981 | * igb_phy_sw_reset - PHY software reset |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1982 | * @hw: pointer to the HW structure |
| 1983 | * |
| 1984 | * Does a software reset of the PHY by reading the PHY control register and |
| 1985 | * setting/write the control register reset bit to the PHY. |
| 1986 | **/ |
| 1987 | s32 igb_phy_sw_reset(struct e1000_hw *hw) |
| 1988 | { |
Alexander Duyck | d314737 | 2009-09-14 08:23:13 +0000 | [diff] [blame] | 1989 | s32 ret_val = 0; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1990 | u16 phy_ctrl; |
| 1991 | |
Alexander Duyck | d314737 | 2009-09-14 08:23:13 +0000 | [diff] [blame] | 1992 | if (!(hw->phy.ops.read_reg)) |
| 1993 | goto out; |
| 1994 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 1995 | ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 1996 | if (ret_val) |
| 1997 | goto out; |
| 1998 | |
| 1999 | phy_ctrl |= MII_CR_RESET; |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2000 | ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2001 | if (ret_val) |
| 2002 | goto out; |
| 2003 | |
| 2004 | udelay(1); |
| 2005 | |
| 2006 | out: |
| 2007 | return ret_val; |
| 2008 | } |
| 2009 | |
| 2010 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 2011 | * igb_phy_hw_reset - PHY hardware reset |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2012 | * @hw: pointer to the HW structure |
| 2013 | * |
| 2014 | * Verify the reset block is not blocking us from resetting. Acquire |
| 2015 | * semaphore (if necessary) and read/set/write the device control reset |
| 2016 | * bit in the PHY. Wait the appropriate delay time for the device to |
| 2017 | * reset and relase the semaphore (if necessary). |
| 2018 | **/ |
| 2019 | s32 igb_phy_hw_reset(struct e1000_hw *hw) |
| 2020 | { |
| 2021 | struct e1000_phy_info *phy = &hw->phy; |
| 2022 | s32 ret_val; |
| 2023 | u32 ctrl; |
| 2024 | |
| 2025 | ret_val = igb_check_reset_block(hw); |
| 2026 | if (ret_val) { |
| 2027 | ret_val = 0; |
| 2028 | goto out; |
| 2029 | } |
| 2030 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2031 | ret_val = phy->ops.acquire(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2032 | if (ret_val) |
| 2033 | goto out; |
| 2034 | |
| 2035 | ctrl = rd32(E1000_CTRL); |
| 2036 | wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); |
| 2037 | wrfl(); |
| 2038 | |
| 2039 | udelay(phy->reset_delay_us); |
| 2040 | |
| 2041 | wr32(E1000_CTRL, ctrl); |
| 2042 | wrfl(); |
| 2043 | |
| 2044 | udelay(150); |
| 2045 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2046 | phy->ops.release(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2047 | |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2048 | ret_val = phy->ops.get_cfg_done(hw); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2049 | |
| 2050 | out: |
| 2051 | return ret_val; |
| 2052 | } |
| 2053 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2054 | /** |
Jeff Kirsher | 733596b | 2008-06-27 10:59:59 -0700 | [diff] [blame] | 2055 | * igb_phy_init_script_igp3 - Inits the IGP3 PHY |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2056 | * @hw: pointer to the HW structure |
| 2057 | * |
| 2058 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. |
| 2059 | **/ |
| 2060 | s32 igb_phy_init_script_igp3(struct e1000_hw *hw) |
| 2061 | { |
Auke Kok | 652fff3 | 2008-06-27 11:00:18 -0700 | [diff] [blame] | 2062 | hw_dbg("Running IGP 3 PHY init script\n"); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2063 | |
| 2064 | /* PHY init IGP 3 */ |
| 2065 | /* Enable rise/fall, 10-mode work in class-A */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2066 | hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2067 | /* Remove all caps from Replica path filter */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2068 | hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2069 | /* Bias trimming for ADC, AFE and Driver (Default) */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2070 | hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2071 | /* Increase Hybrid poly bias */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2072 | hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2073 | /* Add 4% to TX amplitude in Giga mode */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2074 | hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2075 | /* Disable trimming (TTT) */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2076 | hw->phy.ops.write_reg(hw, 0x2011, 0x0000); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2077 | /* Poly DC correction to 94.6% + 2% for all channels */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2078 | hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2079 | /* ABS DC correction to 95.9% */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2080 | hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2081 | /* BG temp curve trim */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2082 | hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2083 | /* Increasing ADC OPAMP stage 1 currents to max */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2084 | hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2085 | /* Force 1000 ( required for enabling PHY regs configuration) */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2086 | hw->phy.ops.write_reg(hw, 0x0000, 0x0140); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2087 | /* Set upd_freq to 6 */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2088 | hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2089 | /* Disable NPDFE */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2090 | hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2091 | /* Disable adaptive fixed FFE (Default) */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2092 | hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2093 | /* Enable FFE hysteresis */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2094 | hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2095 | /* Fixed FFE for short cable lengths */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2096 | hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2097 | /* Fixed FFE for medium cable lengths */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2098 | hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2099 | /* Fixed FFE for long cable lengths */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2100 | hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2101 | /* Enable Adaptive Clip Threshold */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2102 | hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2103 | /* AHT reset limit to 1 */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2104 | hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2105 | /* Set AHT master delay to 127 msec */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2106 | hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2107 | /* Set scan bits for AHT */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2108 | hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2109 | /* Set AHT Preset bits */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2110 | hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2111 | /* Change integ_factor of channel A to 3 */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2112 | hw->phy.ops.write_reg(hw, 0x1895, 0x0003); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2113 | /* Change prop_factor of channels BCD to 8 */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2114 | hw->phy.ops.write_reg(hw, 0x1796, 0x0008); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2115 | /* Change cg_icount + enable integbp for channels BCD */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2116 | hw->phy.ops.write_reg(hw, 0x1798, 0xD008); |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2117 | /* Change cg_icount + enable integbp + change prop_factor_master |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2118 | * to 8 for channel A |
| 2119 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2120 | hw->phy.ops.write_reg(hw, 0x1898, 0xD918); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2121 | /* Disable AHT in Slave mode on channel A */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2122 | hw->phy.ops.write_reg(hw, 0x187A, 0x0800); |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2123 | /* Enable LPLU and disable AN to 1000 in non-D0a states, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2124 | * Enable SPD+B2B |
| 2125 | */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2126 | hw->phy.ops.write_reg(hw, 0x0019, 0x008D); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2127 | /* Enable restart AN on an1000_dis change */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2128 | hw->phy.ops.write_reg(hw, 0x001B, 0x2080); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2129 | /* Enable wh_fifo read clock in 10/100 modes */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2130 | hw->phy.ops.write_reg(hw, 0x0014, 0x0045); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2131 | /* Restart AN, Speed selection is 1000 */ |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 2132 | hw->phy.ops.write_reg(hw, 0x0000, 0x1340); |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 2133 | |
| 2134 | return 0; |
| 2135 | } |
| 2136 | |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2137 | /** |
Nick Nunley | 88a268c | 2010-02-17 01:01:59 +0000 | [diff] [blame] | 2138 | * igb_power_up_phy_copper - Restore copper link in case of PHY power down |
| 2139 | * @hw: pointer to the HW structure |
| 2140 | * |
| 2141 | * In the case of a PHY power down to save power, or to turn off link during a |
| 2142 | * driver unload, restore the link to previous settings. |
| 2143 | **/ |
| 2144 | void igb_power_up_phy_copper(struct e1000_hw *hw) |
| 2145 | { |
| 2146 | u16 mii_reg = 0; |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 2147 | u16 power_reg = 0; |
Nick Nunley | 88a268c | 2010-02-17 01:01:59 +0000 | [diff] [blame] | 2148 | |
| 2149 | /* The PHY will retain its settings across a power down/up cycle */ |
| 2150 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); |
| 2151 | mii_reg &= ~MII_CR_POWER_DOWN; |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 2152 | if (hw->phy.type == e1000_phy_i210) { |
| 2153 | hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); |
| 2154 | power_reg &= ~GS40G_CS_POWER_DOWN; |
| 2155 | hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); |
| 2156 | } |
Nick Nunley | 88a268c | 2010-02-17 01:01:59 +0000 | [diff] [blame] | 2157 | hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); |
| 2158 | } |
| 2159 | |
| 2160 | /** |
| 2161 | * igb_power_down_phy_copper - Power down copper PHY |
| 2162 | * @hw: pointer to the HW structure |
| 2163 | * |
| 2164 | * Power down PHY to save power when interface is down and wake on lan |
| 2165 | * is not enabled. |
| 2166 | **/ |
| 2167 | void igb_power_down_phy_copper(struct e1000_hw *hw) |
| 2168 | { |
| 2169 | u16 mii_reg = 0; |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 2170 | u16 power_reg = 0; |
Nick Nunley | 88a268c | 2010-02-17 01:01:59 +0000 | [diff] [blame] | 2171 | |
| 2172 | /* The PHY will retain its settings across a power down/up cycle */ |
| 2173 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); |
| 2174 | mii_reg |= MII_CR_POWER_DOWN; |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 2175 | |
| 2176 | /* i210 Phy requires an additional bit for power up/down */ |
| 2177 | if (hw->phy.type == e1000_phy_i210) { |
| 2178 | hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); |
| 2179 | power_reg |= GS40G_CS_POWER_DOWN; |
| 2180 | hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); |
| 2181 | } |
Nick Nunley | 88a268c | 2010-02-17 01:01:59 +0000 | [diff] [blame] | 2182 | hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); |
| 2183 | msleep(1); |
| 2184 | } |
| 2185 | |
| 2186 | /** |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2187 | * igb_check_polarity_82580 - Checks the polarity. |
| 2188 | * @hw: pointer to the HW structure |
| 2189 | * |
| 2190 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) |
| 2191 | * |
| 2192 | * Polarity is determined based on the PHY specific status register. |
| 2193 | **/ |
Alexander Duyck | bb2ac47 | 2009-11-19 12:42:01 +0000 | [diff] [blame] | 2194 | static s32 igb_check_polarity_82580(struct e1000_hw *hw) |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2195 | { |
| 2196 | struct e1000_phy_info *phy = &hw->phy; |
| 2197 | s32 ret_val; |
| 2198 | u16 data; |
| 2199 | |
| 2200 | |
| 2201 | ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); |
| 2202 | |
| 2203 | if (!ret_val) |
| 2204 | phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2205 | ? e1000_rev_polarity_reversed |
| 2206 | : e1000_rev_polarity_normal; |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2207 | |
| 2208 | return ret_val; |
| 2209 | } |
| 2210 | |
| 2211 | /** |
| 2212 | * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY |
| 2213 | * @hw: pointer to the HW structure |
| 2214 | * |
| 2215 | * Calls the PHY setup function to force speed and duplex. Clears the |
| 2216 | * auto-crossover to force MDI manually. Waits for link and returns |
| 2217 | * successful if link up is successful, else -E1000_ERR_PHY (-2). |
| 2218 | **/ |
| 2219 | s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) |
| 2220 | { |
| 2221 | struct e1000_phy_info *phy = &hw->phy; |
| 2222 | s32 ret_val; |
| 2223 | u16 phy_data; |
| 2224 | bool link; |
| 2225 | |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2226 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
| 2227 | if (ret_val) |
| 2228 | goto out; |
| 2229 | |
| 2230 | igb_phy_force_speed_duplex_setup(hw, &phy_data); |
| 2231 | |
| 2232 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
| 2233 | if (ret_val) |
| 2234 | goto out; |
| 2235 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2236 | /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2237 | * forced whenever speed and duplex are forced. |
| 2238 | */ |
| 2239 | ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); |
| 2240 | if (ret_val) |
| 2241 | goto out; |
| 2242 | |
Jesse Brandeburg | 1b55678 | 2012-07-26 02:31:04 +0000 | [diff] [blame] | 2243 | phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2244 | |
| 2245 | ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); |
| 2246 | if (ret_val) |
| 2247 | goto out; |
| 2248 | |
| 2249 | hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); |
| 2250 | |
| 2251 | udelay(1); |
| 2252 | |
| 2253 | if (phy->autoneg_wait_to_complete) { |
| 2254 | hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); |
| 2255 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2256 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2257 | if (ret_val) |
| 2258 | goto out; |
| 2259 | |
| 2260 | if (!link) |
| 2261 | hw_dbg("Link taking longer than expected.\n"); |
| 2262 | |
| 2263 | /* Try once more */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2264 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2265 | if (ret_val) |
| 2266 | goto out; |
| 2267 | } |
| 2268 | |
| 2269 | out: |
| 2270 | return ret_val; |
| 2271 | } |
| 2272 | |
| 2273 | /** |
| 2274 | * igb_get_phy_info_82580 - Retrieve I82580 PHY information |
| 2275 | * @hw: pointer to the HW structure |
| 2276 | * |
| 2277 | * Read PHY status to determine if link is up. If link is up, then |
| 2278 | * set/determine 10base-T extended distance and polarity correction. Read |
| 2279 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, |
| 2280 | * determine on the cable length, local and remote receiver. |
| 2281 | **/ |
| 2282 | s32 igb_get_phy_info_82580(struct e1000_hw *hw) |
| 2283 | { |
| 2284 | struct e1000_phy_info *phy = &hw->phy; |
| 2285 | s32 ret_val; |
| 2286 | u16 data; |
| 2287 | bool link; |
| 2288 | |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2289 | ret_val = igb_phy_has_link(hw, 1, 0, &link); |
| 2290 | if (ret_val) |
| 2291 | goto out; |
| 2292 | |
| 2293 | if (!link) { |
| 2294 | hw_dbg("Phy info is only valid if link is up\n"); |
| 2295 | ret_val = -E1000_ERR_CONFIG; |
| 2296 | goto out; |
| 2297 | } |
| 2298 | |
| 2299 | phy->polarity_correction = true; |
| 2300 | |
| 2301 | ret_val = igb_check_polarity_82580(hw); |
| 2302 | if (ret_val) |
| 2303 | goto out; |
| 2304 | |
| 2305 | ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); |
| 2306 | if (ret_val) |
| 2307 | goto out; |
| 2308 | |
| 2309 | phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; |
| 2310 | |
| 2311 | if ((data & I82580_PHY_STATUS2_SPEED_MASK) == |
| 2312 | I82580_PHY_STATUS2_SPEED_1000MBPS) { |
| 2313 | ret_val = hw->phy.ops.get_cable_length(hw); |
| 2314 | if (ret_val) |
| 2315 | goto out; |
| 2316 | |
| 2317 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
| 2318 | if (ret_val) |
| 2319 | goto out; |
| 2320 | |
| 2321 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2322 | ? e1000_1000t_rx_status_ok |
| 2323 | : e1000_1000t_rx_status_not_ok; |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2324 | |
| 2325 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2326 | ? e1000_1000t_rx_status_ok |
| 2327 | : e1000_1000t_rx_status_not_ok; |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2328 | } else { |
| 2329 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; |
| 2330 | phy->local_rx = e1000_1000t_rx_status_undefined; |
| 2331 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
| 2332 | } |
| 2333 | |
| 2334 | out: |
| 2335 | return ret_val; |
| 2336 | } |
| 2337 | |
| 2338 | /** |
| 2339 | * igb_get_cable_length_82580 - Determine cable length for 82580 PHY |
| 2340 | * @hw: pointer to the HW structure |
| 2341 | * |
| 2342 | * Reads the diagnostic status register and verifies result is valid before |
| 2343 | * placing it in the phy_cable_length field. |
| 2344 | **/ |
| 2345 | s32 igb_get_cable_length_82580(struct e1000_hw *hw) |
| 2346 | { |
| 2347 | struct e1000_phy_info *phy = &hw->phy; |
| 2348 | s32 ret_val; |
| 2349 | u16 phy_data, length; |
| 2350 | |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2351 | ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); |
| 2352 | if (ret_val) |
| 2353 | goto out; |
| 2354 | |
| 2355 | length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 2356 | I82580_DSTATUS_CABLE_LENGTH_SHIFT; |
Alexander Duyck | 2909c3f | 2009-11-19 12:41:42 +0000 | [diff] [blame] | 2357 | |
| 2358 | if (length == E1000_CABLE_LENGTH_UNDEFINED) |
| 2359 | ret_val = -E1000_ERR_PHY; |
| 2360 | |
| 2361 | phy->cable_length = length; |
| 2362 | |
| 2363 | out: |
| 2364 | return ret_val; |
| 2365 | } |
Carolyn Wyborny | f96a8a0 | 2012-04-06 23:25:19 +0000 | [diff] [blame] | 2366 | |
| 2367 | /** |
| 2368 | * igb_write_phy_reg_gs40g - Write GS40G PHY register |
| 2369 | * @hw: pointer to the HW structure |
| 2370 | * @offset: lower half is register offset to write to |
| 2371 | * upper half is page to use. |
| 2372 | * @data: data to write at register offset |
| 2373 | * |
| 2374 | * Acquires semaphore, if necessary, then writes the data to PHY register |
| 2375 | * at the offset. Release any acquired semaphores before exiting. |
| 2376 | **/ |
| 2377 | s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) |
| 2378 | { |
| 2379 | s32 ret_val; |
| 2380 | u16 page = offset >> GS40G_PAGE_SHIFT; |
| 2381 | |
| 2382 | offset = offset & GS40G_OFFSET_MASK; |
| 2383 | ret_val = hw->phy.ops.acquire(hw); |
| 2384 | if (ret_val) |
| 2385 | return ret_val; |
| 2386 | |
| 2387 | ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); |
| 2388 | if (ret_val) |
| 2389 | goto release; |
| 2390 | ret_val = igb_write_phy_reg_mdic(hw, offset, data); |
| 2391 | |
| 2392 | release: |
| 2393 | hw->phy.ops.release(hw); |
| 2394 | return ret_val; |
| 2395 | } |
| 2396 | |
| 2397 | /** |
| 2398 | * igb_read_phy_reg_gs40g - Read GS40G PHY register |
| 2399 | * @hw: pointer to the HW structure |
| 2400 | * @offset: lower half is register offset to read to |
| 2401 | * upper half is page to use. |
| 2402 | * @data: data to read at register offset |
| 2403 | * |
| 2404 | * Acquires semaphore, if necessary, then reads the data in the PHY register |
| 2405 | * at the offset. Release any acquired semaphores before exiting. |
| 2406 | **/ |
| 2407 | s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) |
| 2408 | { |
| 2409 | s32 ret_val; |
| 2410 | u16 page = offset >> GS40G_PAGE_SHIFT; |
| 2411 | |
| 2412 | offset = offset & GS40G_OFFSET_MASK; |
| 2413 | ret_val = hw->phy.ops.acquire(hw); |
| 2414 | if (ret_val) |
| 2415 | return ret_val; |
| 2416 | |
| 2417 | ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); |
| 2418 | if (ret_val) |
| 2419 | goto release; |
| 2420 | ret_val = igb_read_phy_reg_mdic(hw, offset, data); |
| 2421 | |
| 2422 | release: |
| 2423 | hw->phy.ops.release(hw); |
| 2424 | return ret_val; |
| 2425 | } |
| 2426 | |
| 2427 | /** |
| 2428 | * igb_set_master_slave_mode - Setup PHY for Master/slave mode |
| 2429 | * @hw: pointer to the HW structure |
| 2430 | * |
| 2431 | * Sets up Master/slave mode |
| 2432 | **/ |
| 2433 | static s32 igb_set_master_slave_mode(struct e1000_hw *hw) |
| 2434 | { |
| 2435 | s32 ret_val; |
| 2436 | u16 phy_data; |
| 2437 | |
| 2438 | /* Resolve Master/Slave mode */ |
| 2439 | ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); |
| 2440 | if (ret_val) |
| 2441 | return ret_val; |
| 2442 | |
| 2443 | /* load defaults for future use */ |
| 2444 | hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? |
| 2445 | ((phy_data & CR_1000T_MS_VALUE) ? |
| 2446 | e1000_ms_force_master : |
| 2447 | e1000_ms_force_slave) : e1000_ms_auto; |
| 2448 | |
| 2449 | switch (hw->phy.ms_type) { |
| 2450 | case e1000_ms_force_master: |
| 2451 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
| 2452 | break; |
| 2453 | case e1000_ms_force_slave: |
| 2454 | phy_data |= CR_1000T_MS_ENABLE; |
| 2455 | phy_data &= ~(CR_1000T_MS_VALUE); |
| 2456 | break; |
| 2457 | case e1000_ms_auto: |
| 2458 | phy_data &= ~CR_1000T_MS_ENABLE; |
| 2459 | /* fall-through */ |
| 2460 | default: |
| 2461 | break; |
| 2462 | } |
| 2463 | |
| 2464 | return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); |
| 2465 | } |