blob: 3878494bd11827756150235f404e86cb520a14a0 [file] [log] [blame]
Shawn Guo13eed982011-09-06 15:05:25 +08001/*
Anson Huange95dddb2013-03-20 19:39:42 -04002 * Copyright 2011-2013 Freescale Semiconductor, Inc.
Shawn Guo13eed982011-09-06 15:05:25 +08003 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Richard Zhaoa2585612012-04-24 14:19:13 +080013#include <linux/clk.h>
14#include <linux/clkdev.h>
Shawn Guo96574a62013-01-08 14:25:14 +080015#include <linux/cpu.h>
Tim Harvey4bb1d092013-10-22 21:51:28 -070016#include <linux/delay.h>
Robert Leeb9d18dc2012-05-21 17:50:30 -050017#include <linux/export.h>
Shawn Guo13eed982011-09-06 15:05:25 +080018#include <linux/init.h>
Shawn Guo0575fb72011-12-09 00:51:26 +010019#include <linux/io.h>
Shawn Guo13eed982011-09-06 15:05:25 +080020#include <linux/irq.h>
Rob Herring0529e3152012-11-05 16:18:28 -060021#include <linux/irqchip.h>
Shawn Guo13eed982011-09-06 15:05:25 +080022#include <linux/of.h>
Shawn Guo0575fb72011-12-09 00:51:26 +010023#include <linux/of_address.h>
Shawn Guo13eed982011-09-06 15:05:25 +080024#include <linux/of_irq.h>
25#include <linux/of_platform.h>
Nishanth Menone4db1c72013-09-19 16:03:52 -050026#include <linux/pm_opp.h>
Tim Harvey4bb1d092013-10-22 21:51:28 -070027#include <linux/pci.h>
Richard Zhao477fce42011-12-14 09:26:47 +080028#include <linux/phy.h>
Robin Holt7b6d8642013-07-08 16:01:40 -070029#include <linux/reboot.h>
Dong Aishengbaa64152012-09-05 10:57:15 +080030#include <linux/regmap.h>
Richard Zhao477fce42011-12-14 09:26:47 +080031#include <linux/micrel_phy.h>
Dong Aishengbaa64152012-09-05 10:57:15 +080032#include <linux/mfd/syscon.h>
Philipp Zabel6d6fc502013-06-26 15:08:49 +020033#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
Shawn Guo13eed982011-09-06 15:05:25 +080034#include <asm/mach/arch.h>
Shawn Guo3e549a62013-01-17 16:37:42 +080035#include <asm/mach/map.h>
David Howells9f97da72012-03-28 18:30:01 +010036#include <asm/system_misc.h>
Shawn Guo13eed982011-09-06 15:05:25 +080037
Shawn Guoe3372472012-09-13 21:01:00 +080038#include "common.h"
Shawn Guoe29248c2012-09-13 21:12:50 +080039#include "cpuidle.h"
Shawn Guo50f2de62012-09-14 14:14:45 +080040#include "hardware.h"
Robert Leeb9d18dc2012-05-21 17:50:30 -050041
Richard Zhao477fce42011-12-14 09:26:47 +080042/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
43static int ksz9021rn_phy_fixup(struct phy_device *phydev)
44{
Arnd Bergmann9f9ba0f2012-08-16 07:42:50 +000045 if (IS_BUILTIN(CONFIG_PHYLIB)) {
Shawn Guoef441802012-05-08 21:39:33 +080046 /* min rx data delay */
Dinh Nguyendc76a1a2013-08-13 09:59:00 -050047 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
48 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
49 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
Richard Zhao477fce42011-12-14 09:26:47 +080050
Shawn Guoef441802012-05-08 21:39:33 +080051 /* max rx/tx clock delay, min rx/tx control delay */
Dinh Nguyendc76a1a2013-08-13 09:59:00 -050052 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
53 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
54 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
55 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
56 MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
Shawn Guoef441802012-05-08 21:39:33 +080057 }
Richard Zhao477fce42011-12-14 09:26:47 +080058
59 return 0;
60}
61
Sascha Hauerdbf67192013-06-20 17:34:33 +020062static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
Richard Zhaoa2585612012-04-24 14:19:13 +080063{
Sascha Hauerdbf67192013-06-20 17:34:33 +020064 phy_write(dev, 0x0d, device);
65 phy_write(dev, 0x0e, reg);
66 phy_write(dev, 0x0d, (1 << 14) | device);
67 phy_write(dev, 0x0e, val);
Richard Zhaoa2585612012-04-24 14:19:13 +080068}
69
Sascha Hauerdbf67192013-06-20 17:34:33 +020070static int ksz9031rn_phy_fixup(struct phy_device *dev)
Richard Zhao071dea52012-04-27 15:02:59 +080071{
Sascha Hauerdbf67192013-06-20 17:34:33 +020072 /*
73 * min rx data delay, max rx/tx clock delay,
74 * min rx/tx control delay
75 */
76 mmd_write_reg(dev, 2, 4, 0);
77 mmd_write_reg(dev, 2, 5, 0);
78 mmd_write_reg(dev, 2, 8, 0x003ff);
79
80 return 0;
81}
82
Tim Harvey4bb1d092013-10-22 21:51:28 -070083/*
84 * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
85 * as they are used for slots1-7 PERST#
86 */
87static void ventana_pciesw_early_fixup(struct pci_dev *dev)
88{
89 u32 dw;
90
91 if (!of_machine_is_compatible("gw,ventana"))
92 return;
93
94 if (dev->devfn != 0)
95 return;
96
97 pci_read_config_dword(dev, 0x62c, &dw);
98 dw |= 0xaaa8; // GPIO1-7 outputs
99 pci_write_config_dword(dev, 0x62c, dw);
100
101 pci_read_config_dword(dev, 0x644, &dw);
102 dw |= 0xfe; // GPIO1-7 output high
103 pci_write_config_dword(dev, 0x644, dw);
104
105 msleep(100);
106}
107DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
108DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
109DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
110
Sascha Hauer12da4842013-06-20 17:34:32 +0200111static int ar8031_phy_fixup(struct phy_device *dev)
112{
113 u16 val;
114
115 /* To enable AR8031 output a 125MHz clk from CLK_25M */
116 phy_write(dev, 0xd, 0x7);
117 phy_write(dev, 0xe, 0x8016);
118 phy_write(dev, 0xd, 0x4007);
119
120 val = phy_read(dev, 0xe);
121 val &= 0xffe3;
122 val |= 0x18;
123 phy_write(dev, 0xe, val);
124
125 /* introduce tx clock delay */
126 phy_write(dev, 0x1d, 0x5);
127 val = phy_read(dev, 0x1e);
128 val |= 0x0100;
129 phy_write(dev, 0x1e, val);
130
131 return 0;
132}
133
Sascha Hauer12da4842013-06-20 17:34:32 +0200134#define PHY_ID_AR8031 0x004dd074
135
Russell King208d7baf2013-09-27 20:07:26 +0100136static int ar8035_phy_fixup(struct phy_device *dev)
137{
138 u16 val;
139
140 /* Ar803x phy SmartEEE feature cause link status generates glitch,
141 * which cause ethernet link down/up issue, so disable SmartEEE
142 */
143 phy_write(dev, 0xd, 0x3);
144 phy_write(dev, 0xe, 0x805d);
145 phy_write(dev, 0xd, 0x4003);
146
147 val = phy_read(dev, 0xe);
148 phy_write(dev, 0xe, val & ~(1 << 8));
149
150 /*
151 * Enable 125MHz clock from CLK_25M on the AR8031. This
152 * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
153 * Also, introduce a tx clock delay.
154 *
155 * This is the same as is the AR8031 fixup.
156 */
157 ar8031_phy_fixup(dev);
158
159 /*check phy power*/
160 val = phy_read(dev, 0x0);
161 if (val & BMCR_PDOWN)
162 phy_write(dev, 0x0, val & ~BMCR_PDOWN);
163
164 return 0;
165}
166
167#define PHY_ID_AR8035 0x004dd072
168
Sascha Hauer14078292013-06-20 17:34:31 +0200169static void __init imx6q_enet_phy_init(void)
Richard Zhao071dea52012-04-27 15:02:59 +0800170{
Sascha Hauer14078292013-06-20 17:34:31 +0200171 if (IS_BUILTIN(CONFIG_PHYLIB)) {
Shawn Guoef441802012-05-08 21:39:33 +0800172 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
Richard Zhao071dea52012-04-27 15:02:59 +0800173 ksz9021rn_phy_fixup);
Sascha Hauerdbf67192013-06-20 17:34:33 +0200174 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
175 ksz9031rn_phy_fixup);
Sascha Hauer12da4842013-06-20 17:34:32 +0200176 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
177 ar8031_phy_fixup);
Russell King208d7baf2013-09-27 20:07:26 +0100178 phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
179 ar8035_phy_fixup);
Nicolin Chene7eccc72013-06-13 19:50:56 +0800180 }
Nicolin Chene7eccc72013-06-13 19:50:56 +0800181}
182
Frank Lid6e0d9f2012-10-30 18:25:22 +0000183static void __init imx6q_1588_init(void)
184{
Shawn Guo810c0ca2014-02-06 13:22:02 +0800185 struct device_node *np;
186 struct clk *ptp_clk;
187 struct clk *enet_ref;
Frank Lid6e0d9f2012-10-30 18:25:22 +0000188 struct regmap *gpr;
Shawn Guo810c0ca2014-02-06 13:22:02 +0800189 u32 clksel;
Frank Lid6e0d9f2012-10-30 18:25:22 +0000190
Shawn Guo810c0ca2014-02-06 13:22:02 +0800191 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
192 if (!np) {
193 pr_warn("%s: failed to find fec node\n", __func__);
194 return;
195 }
196
197 ptp_clk = of_clk_get(np, 2);
198 if (IS_ERR(ptp_clk)) {
199 pr_warn("%s: failed to get ptp clock\n", __func__);
200 goto put_node;
201 }
202
203 enet_ref = clk_get_sys(NULL, "enet_ref");
204 if (IS_ERR(enet_ref)) {
205 pr_warn("%s: failed to get enet clock\n", __func__);
206 goto put_ptp_clk;
207 }
208
209 /*
210 * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
211 * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
212 * (external OSC), and we need to clear the bit.
213 */
Shawn Guoa51139f2015-02-25 22:53:32 +0800214 clksel = clk_is_match(ptp_clk, enet_ref) ?
215 IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
216 IMX6Q_GPR1_ENET_CLK_SEL_PAD;
Frank Lid6e0d9f2012-10-30 18:25:22 +0000217 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
218 if (!IS_ERR(gpr))
Philipp Zabel6d6fc502013-06-26 15:08:49 +0200219 regmap_update_bits(gpr, IOMUXC_GPR1,
220 IMX6Q_GPR1_ENET_CLK_SEL_MASK,
Shawn Guo810c0ca2014-02-06 13:22:02 +0800221 clksel);
Frank Lid6e0d9f2012-10-30 18:25:22 +0000222 else
223 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
224
Shawn Guo810c0ca2014-02-06 13:22:02 +0800225 clk_put(enet_ref);
226put_ptp_clk:
227 clk_put(ptp_clk);
228put_node:
229 of_node_put(np);
Frank Lid6e0d9f2012-10-30 18:25:22 +0000230}
Richard Zhao396bf1c2012-07-12 10:25:24 +0800231
Philipp Zabel7ea653e2014-02-24 14:51:50 +0100232static void __init imx6q_axi_init(void)
233{
234 struct regmap *gpr;
235 unsigned int mask;
236
237 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
238 if (!IS_ERR(gpr)) {
239 /*
240 * Enable the cacheable attribute of VPU and IPU
241 * AXI transactions.
242 */
243 mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL |
244 IMX6Q_GPR4_VPU_RD_CACHE_SEL |
245 IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
246 IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
247 IMX6Q_GPR4_IPU_WR_CACHE_CTL |
248 IMX6Q_GPR4_IPU_RD_CACHE_CTL;
249 regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);
250
251 /* Increase IPU read QoS priority */
252 regmap_update_bits(gpr, IOMUXC_GPR6,
253 IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
254 IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
255 (0xf << 16) | (0x7 << 20));
256 regmap_update_bits(gpr, IOMUXC_GPR7,
257 IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
258 IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
259 (0xf << 16) | (0x7 << 20));
260 } else {
261 pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
262 }
263}
264
Shawn Guo13eed982011-09-06 15:05:25 +0800265static void __init imx6q_init_machine(void)
266{
Shawn Guoa2887542013-08-13 16:59:28 +0800267 struct device *parent;
268
Sebastian Hesselbarth4d9d18a2013-08-27 14:50:00 +0200269 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
Shawn Guo3f759782013-08-13 14:10:29 +0800270 imx_get_soc_revision());
Sebastian Hesselbarth4d9d18a2013-08-27 14:50:00 +0200271
Shawn Guoa2887542013-08-13 16:59:28 +0800272 parent = imx_soc_device_init();
273 if (parent == NULL)
274 pr_warn("failed to initialize soc device\n");
275
Sascha Hauer14078292013-06-20 17:34:31 +0200276 imx6q_enet_phy_init();
Richard Zhao477fce42011-12-14 09:26:47 +0800277
Shawn Guoa2887542013-08-13 16:59:28 +0800278 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
Shawn Guo13eed982011-09-06 15:05:25 +0800279
Anson Huange95dddb2013-03-20 19:39:42 -0400280 imx_anatop_init();
Anson Huangdf595742014-01-17 11:39:05 +0800281 cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
Frank Lid6e0d9f2012-10-30 18:25:22 +0000282 imx6q_1588_init();
Philipp Zabel7ea653e2014-02-24 14:51:50 +0100283 imx6q_axi_init();
Shawn Guo13eed982011-09-06 15:05:25 +0800284}
285
Shawn Guo96574a62013-01-08 14:25:14 +0800286#define OCOTP_CFG3 0x440
287#define OCOTP_CFG3_SPEED_SHIFT 16
288#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
Anson Huangc962a092014-02-12 17:57:03 +0800289#define OCOTP_CFG3_SPEED_996MHZ 0x2
290#define OCOTP_CFG3_SPEED_852MHZ 0x1
Shawn Guo96574a62013-01-08 14:25:14 +0800291
Anson Huangc962a092014-02-12 17:57:03 +0800292static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
Shawn Guo96574a62013-01-08 14:25:14 +0800293{
294 struct device_node *np;
295 void __iomem *base;
296 u32 val;
297
298 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
299 if (!np) {
300 pr_warn("failed to find ocotp node\n");
301 return;
302 }
303
304 base = of_iomap(np, 0);
305 if (!base) {
306 pr_warn("failed to map ocotp\n");
307 goto put_node;
308 }
309
Anson Huangc962a092014-02-12 17:57:03 +0800310 /*
311 * SPEED_GRADING[1:0] defines the max speed of ARM:
312 * 2b'11: 1200000000Hz;
313 * 2b'10: 996000000Hz;
314 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
315 * 2b'00: 792000000Hz;
316 * We need to set the max speed of ARM according to fuse map.
317 */
Shawn Guo96574a62013-01-08 14:25:14 +0800318 val = readl_relaxed(base + OCOTP_CFG3);
319 val >>= OCOTP_CFG3_SPEED_SHIFT;
Anson Huangc962a092014-02-12 17:57:03 +0800320 val &= 0x3;
321
Fabio Estevama49fb632014-07-01 00:12:52 -0300322 if ((val != OCOTP_CFG3_SPEED_1P2GHZ) && cpu_is_imx6q())
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500323 if (dev_pm_opp_disable(cpu_dev, 1200000000))
Shawn Guo96574a62013-01-08 14:25:14 +0800324 pr_warn("failed to disable 1.2 GHz OPP\n");
Anson Huangc962a092014-02-12 17:57:03 +0800325 if (val < OCOTP_CFG3_SPEED_996MHZ)
326 if (dev_pm_opp_disable(cpu_dev, 996000000))
327 pr_warn("failed to disable 996 MHz OPP\n");
328 if (cpu_is_imx6q()) {
329 if (val != OCOTP_CFG3_SPEED_852MHZ)
330 if (dev_pm_opp_disable(cpu_dev, 852000000))
331 pr_warn("failed to disable 852 MHz OPP\n");
332 }
Sebastian Andrzej Siewior23bec172015-01-13 18:46:53 +0100333 iounmap(base);
Shawn Guo96574a62013-01-08 14:25:14 +0800334put_node:
335 of_node_put(np);
336}
337
Sudeep KarkadaNageshab494b482013-09-10 18:59:47 +0100338static void __init imx6q_opp_init(void)
Shawn Guo96574a62013-01-08 14:25:14 +0800339{
340 struct device_node *np;
Sudeep KarkadaNageshab494b482013-09-10 18:59:47 +0100341 struct device *cpu_dev = get_cpu_device(0);
Shawn Guo96574a62013-01-08 14:25:14 +0800342
Sudeep KarkadaNageshab494b482013-09-10 18:59:47 +0100343 if (!cpu_dev) {
344 pr_warn("failed to get cpu0 device\n");
345 return;
346 }
Sudeep KarkadaNageshacdc58d62013-06-17 14:58:48 +0100347 np = of_node_get(cpu_dev->of_node);
Shawn Guo96574a62013-01-08 14:25:14 +0800348 if (!np) {
349 pr_warn("failed to find cpu0 node\n");
350 return;
351 }
352
Viresh Kumar8f8d37b2015-09-04 13:47:24 +0530353 if (dev_pm_opp_of_add_table(cpu_dev)) {
Shawn Guo96574a62013-01-08 14:25:14 +0800354 pr_warn("failed to init OPP table\n");
355 goto put_node;
356 }
357
Anson Huangc962a092014-02-12 17:57:03 +0800358 imx6q_opp_check_speed_grading(cpu_dev);
Shawn Guo96574a62013-01-08 14:25:14 +0800359
360put_node:
361 of_node_put(np);
362}
363
Fabio Estevamf8c11b22013-03-25 09:20:44 -0300364static struct platform_device imx6q_cpufreq_pdev = {
Shawn Guo96574a62013-01-08 14:25:14 +0800365 .name = "imx6q-cpufreq",
366};
367
Robert Leeb9d18dc2012-05-21 17:50:30 -0500368static void __init imx6q_init_late(void)
369{
Shawn Guoe5f9dec2012-12-04 22:55:15 +0800370 /*
371 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
372 * to run cpuidle on them.
373 */
Shawn Guo3f759782013-08-13 14:10:29 +0800374 if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
Shawn Guoe5f9dec2012-12-04 22:55:15 +0800375 imx6q_cpuidle_init();
Shawn Guo96574a62013-01-08 14:25:14 +0800376
377 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
Sudeep KarkadaNageshab494b482013-09-10 18:59:47 +0100378 imx6q_opp_init();
Shawn Guo96574a62013-01-08 14:25:14 +0800379 platform_device_register(&imx6q_cpufreq_pdev);
380 }
Robert Leeb9d18dc2012-05-21 17:50:30 -0500381}
382
Shawn Guo13eed982011-09-06 15:05:25 +0800383static void __init imx6q_map_io(void)
384{
Shawn Guo3e549a62013-01-17 16:37:42 +0800385 debug_ll_io_init();
Shawn Guo13eed982011-09-06 15:05:25 +0800386 imx_scu_map_io();
Shawn Guo13eed982011-09-06 15:05:25 +0800387}
388
Shawn Guo13eed982011-09-06 15:05:25 +0800389static void __init imx6q_init_irq(void)
390{
Marc Zyngier14517562015-03-13 16:05:37 +0000391 imx_gpc_check_dt();
Shawn Guof1c6f312013-08-13 14:59:43 +0800392 imx_init_revision_from_anatop();
Shawn Guoe6a07562013-07-08 21:45:20 +0800393 imx_init_l2cache();
Shawn Guo13eed982011-09-06 15:05:25 +0800394 imx_src_init();
Rob Herring0529e3152012-11-05 16:18:28 -0600395 irqchip_init();
Shawn Guo35e29162015-04-29 13:07:03 +0800396 imx6_pm_ccm_init("fsl,imx6q-ccm");
Shawn Guo13eed982011-09-06 15:05:25 +0800397}
398
Shawn Guo8756dd92014-07-01 16:03:00 +0800399static const char * const imx6q_dt_compat[] __initconst = {
Shawn Guo3c03a2f2013-04-01 22:13:32 +0800400 "fsl,imx6dl",
Sascha Hauer3f8976d2012-02-17 12:07:00 +0100401 "fsl,imx6q",
Shawn Guo13eed982011-09-06 15:05:25 +0800402 NULL,
403};
404
Shawn Guo3c03a2f2013-04-01 22:13:32 +0800405DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
Marc Zyngiere4f2d972011-09-08 13:15:22 +0100406 .smp = smp_ops(imx_smp_ops),
Shawn Guo13eed982011-09-06 15:05:25 +0800407 .map_io = imx6q_map_io,
408 .init_irq = imx6q_init_irq,
Shawn Guo13eed982011-09-06 15:05:25 +0800409 .init_machine = imx6q_init_machine,
Robert Leeb9d18dc2012-05-21 17:50:30 -0500410 .init_late = imx6q_init_late,
Shawn Guo13eed982011-09-06 15:05:25 +0800411 .dt_compat = imx6q_dt_compat,
Shawn Guo13eed982011-09-06 15:05:25 +0800412MACHINE_END