blob: 0884ca90d15a309eab1a33af6cfc68c95db82b75 [file] [log] [blame]
Uwe Kleine-König27ad4bf2011-03-17 09:40:29 +01001/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
Dong Aishenga2aa65a2012-05-02 19:31:20 +080022#include <linux/pinctrl/machine.h>
Uwe Kleine-König27ad4bf2011-03-17 09:40:29 +010023
24#include <asm/pgtable.h>
Olof Johansson86dfe442012-03-29 23:22:44 -070025#include <asm/system_misc.h>
Shawn Guoddd5f512011-09-28 17:16:05 +080026#include <asm/hardware/cache-l2x0.h>
Uwe Kleine-König27ad4bf2011-03-17 09:40:29 +010027#include <asm/mach/map.h>
28
Shawn Guoe3372472012-09-13 21:01:00 +080029#include "common.h"
Sascha Hauereb920442012-04-03 12:42:27 +020030#include "crmregs-imx3.h"
Shawn Guoe0557c02012-09-13 15:51:15 +080031#include "devices/devices-common.h"
Shawn Guo50f2de62012-09-14 14:14:45 +080032#include "hardware.h"
Shawn Guo267dd342012-09-13 13:26:00 +080033#include "iomux-v3.h"
Sascha Hauereb920442012-04-03 12:42:27 +020034
35void __iomem *mx3_ccm_base;
36
Shawn Guo41e7daf2011-09-28 17:16:06 +080037static void imx3_idle(void)
38{
39 unsigned long reg = 0;
Shawn Guo8c6d8312011-11-11 13:09:18 +080040
Fabio Estevam3ac804e2012-02-02 20:02:32 -020041 mx3_cpu_lp_set(MX3_WAIT);
42
Nicolas Pitre4a3ea242011-08-03 11:34:59 -040043 __asm__ __volatile__(
44 /* disable I and D cache */
45 "mrc p15, 0, %0, c1, c0, 0\n"
46 "bic %0, %0, #0x00001000\n"
47 "bic %0, %0, #0x00000004\n"
48 "mcr p15, 0, %0, c1, c0, 0\n"
49 /* invalidate I cache */
50 "mov %0, #0\n"
51 "mcr p15, 0, %0, c7, c5, 0\n"
52 /* clear and invalidate D cache */
53 "mov %0, #0\n"
54 "mcr p15, 0, %0, c7, c14, 0\n"
55 /* WFI */
56 "mov %0, #0\n"
57 "mcr p15, 0, %0, c7, c0, 4\n"
58 "nop\n" "nop\n" "nop\n" "nop\n"
59 "nop\n" "nop\n" "nop\n"
60 /* enable I and D cache */
61 "mrc p15, 0, %0, c1, c0, 0\n"
62 "orr %0, %0, #0x00001000\n"
63 "orr %0, %0, #0x00000004\n"
64 "mcr p15, 0, %0, c1, c0, 0\n"
65 : "=r" (reg));
Shawn Guo41e7daf2011-09-28 17:16:06 +080066}
67
Laura Abbott9b971732013-05-16 19:40:22 +010068static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
Rob Herringc177aa92012-02-13 13:24:15 -060069 unsigned int mtype, void *caller)
Shawn Guof5488972011-09-28 17:16:07 +080070{
71 if (mtype == MT_DEVICE) {
72 /*
73 * Access all peripherals below 0x80000000 as nonshared device
74 * on mx3, but leave l2cc alone. Otherwise cache corruptions
75 * can occur.
76 */
77 if (phys_addr < 0x80000000 &&
78 !addr_in_module(phys_addr, MX3x_L2CC))
79 mtype = MT_DEVICE_NONSHARED;
80 }
81
Rob Herringc177aa92012-02-13 13:24:15 -060082 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
Shawn Guof5488972011-09-28 17:16:07 +080083}
84
Fabio Estevameb7099b2013-03-25 09:20:29 -030085static void __init imx3_init_l2x0(void)
Shawn Guoddd5f512011-09-28 17:16:05 +080086{
Uwe Kleine-Königf90da3c72012-05-18 16:58:03 +020087#ifdef CONFIG_CACHE_L2X0
Shawn Guoddd5f512011-09-28 17:16:05 +080088 void __iomem *l2x0_base;
89 void __iomem *clkctl_base;
90
91/*
92 * First of all, we must repair broken chip settings. There are some
93 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
94 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
95 * Workaraound is to setup the correct register setting prior enabling the
96 * L2 cache. This should not hurt already working CPUs, as they are using the
97 * same value.
98 */
99#define L2_MEM_VAL 0x10
100
101 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
102 if (clkctl_base != NULL) {
103 writel(0x00000515, clkctl_base + L2_MEM_VAL);
104 iounmap(clkctl_base);
105 } else {
106 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
107 }
108
109 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
Wei Yongjun1d10ecf2012-09-27 13:54:01 +0800110 if (!l2x0_base) {
111 printk(KERN_ERR "remapping L2 cache area failed\n");
Shawn Guoddd5f512011-09-28 17:16:05 +0800112 return;
113 }
114
115 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
Uwe Kleine-Königf90da3c72012-05-18 16:58:03 +0200116#endif
Shawn Guoddd5f512011-09-28 17:16:05 +0800117}
118
Uwe Kleine-König87514fc2011-11-22 10:07:26 +0100119#ifdef CONFIG_SOC_IMX31
Uwe Kleine-König27ad4bf2011-03-17 09:40:29 +0100120static struct map_desc mx31_io_desc[] __initdata = {
121 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
122 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
123 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
124 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
125 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
126};
127
128/*
129 * This function initializes the memory map. It is called during the
130 * system startup to create static physical to virtual memory mappings
131 * for the IO modules.
132 */
133void __init mx31_map_io(void)
134{
135 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
136}
137
138void __init imx31_init_early(void)
139{
140 mxc_set_cpu_type(MXC_CPU_MX31);
Rob Herringc177aa92012-02-13 13:24:15 -0600141 arch_ioremap_caller = imx3_ioremap_caller;
Nicolas Pitre4a3ea242011-08-03 11:34:59 -0400142 arm_pm_idle = imx3_idle;
Sascha Hauereb920442012-04-03 12:42:27 +0200143 mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
Uwe Kleine-König27ad4bf2011-03-17 09:40:29 +0100144}
145
Uwe Kleine-König27ad4bf2011-03-17 09:40:29 +0100146void __init mx31_init_irq(void)
147{
148 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
Shawn Guob78d8e52011-06-06 00:07:55 +0800149}
150
Shawn Guo36223602011-06-22 22:41:30 +0800151static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
152 .per_2_per_addr = 1677,
153};
154
155static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
156 .ap_2_ap_addr = 423,
157 .ap_2_bp_addr = 829,
158 .bp_2_ap_addr = 1029,
159};
160
161static struct sdma_platform_data imx31_sdma_pdata __initdata = {
Shawn Guo2e534b22011-06-22 22:41:31 +0800162 .fw_name = "sdma-imx31-to2.bin",
Shawn Guo36223602011-06-22 22:41:30 +0800163 .script_addrs = &imx31_to2_sdma_script,
164};
165
Richard Zhao3bc34a62012-03-05 22:30:52 +0800166static const struct resource imx31_audmux_res[] __initconst = {
167 DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
168};
169
Shawn Guob78d8e52011-06-06 00:07:55 +0800170void __init imx31_soc_init(void)
171{
Shawn Guo36223602011-06-22 22:41:30 +0800172 int to_version = mx31_revision() >> 4;
173
Shawn Guoddd5f512011-09-28 17:16:05 +0800174 imx3_init_l2x0();
175
Shawn Guo18cb6802013-05-10 09:13:44 +0800176 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
Shawn Guo69ac71d2012-09-20 14:21:16 +0800177 mxc_device_init();
178
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800179 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
180 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
181 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
Shawn Guo36223602011-06-22 22:41:30 +0800182
Fabio Estevamaa29cab2012-05-20 14:11:24 -0300183 pinctrl_provide_dummies();
184
Shawn Guo2e534b22011-06-22 22:41:31 +0800185 if (to_version == 1) {
186 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
187 strlen(imx31_sdma_pdata.fw_name));
Shawn Guo36223602011-06-22 22:41:30 +0800188 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
Shawn Guo2e534b22011-06-22 22:41:31 +0800189 }
190
Shawn Guo62550cd2011-07-13 21:33:17 +0800191 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
Fabio Estevambb07d752012-02-29 10:28:08 -0300192
193 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
194 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
Linus Torvalds281b0532012-03-27 16:14:44 -0700195
Richard Zhao3bc34a62012-03-05 22:30:52 +0800196 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
197 ARRAY_SIZE(imx31_audmux_res));
Uwe Kleine-König27ad4bf2011-03-17 09:40:29 +0100198}
Uwe Kleine-König87514fc2011-11-22 10:07:26 +0100199#endif /* ifdef CONFIG_SOC_IMX31 */
200
201#ifdef CONFIG_SOC_IMX35
202static struct map_desc mx35_io_desc[] __initdata = {
203 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
204 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
205 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
206 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
207 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
208};
209
210void __init mx35_map_io(void)
211{
212 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
213}
214
215void __init imx35_init_early(void)
216{
217 mxc_set_cpu_type(MXC_CPU_MX35);
218 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
Nicolas Pitre4a3ea242011-08-03 11:34:59 -0400219 arm_pm_idle = imx3_idle;
Rob Herringc177aa92012-02-13 13:24:15 -0600220 arch_ioremap_caller = imx3_ioremap_caller;
Sascha Hauereb920442012-04-03 12:42:27 +0200221 mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
Uwe Kleine-König87514fc2011-11-22 10:07:26 +0100222}
223
224void __init mx35_init_irq(void)
225{
226 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
227}
Shawn Guof1263de2011-09-28 17:16:03 +0800228
229static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
230 .ap_2_ap_addr = 642,
231 .uart_2_mcu_addr = 817,
232 .mcu_2_app_addr = 747,
233 .uartsh_2_mcu_addr = 1183,
234 .per_2_shp_addr = 1033,
235 .mcu_2_shp_addr = 961,
236 .ata_2_mcu_addr = 1333,
237 .mcu_2_ata_addr = 1252,
238 .app_2_mcu_addr = 683,
239 .shp_2_per_addr = 1111,
240 .shp_2_mcu_addr = 892,
241};
242
243static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
244 .ap_2_ap_addr = 729,
245 .uart_2_mcu_addr = 904,
246 .per_2_app_addr = 1597,
247 .mcu_2_app_addr = 834,
248 .uartsh_2_mcu_addr = 1270,
249 .per_2_shp_addr = 1120,
250 .mcu_2_shp_addr = 1048,
251 .ata_2_mcu_addr = 1429,
252 .mcu_2_ata_addr = 1339,
253 .app_2_per_addr = 1531,
254 .app_2_mcu_addr = 770,
255 .shp_2_per_addr = 1198,
256 .shp_2_mcu_addr = 979,
257};
258
259static struct sdma_platform_data imx35_sdma_pdata __initdata = {
260 .fw_name = "sdma-imx35-to2.bin",
261 .script_addrs = &imx35_to2_sdma_script,
262};
263
Richard Zhao3bc34a62012-03-05 22:30:52 +0800264static const struct resource imx35_audmux_res[] __initconst = {
265 DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
266};
267
Shawn Guof1263de2011-09-28 17:16:03 +0800268void __init imx35_soc_init(void)
269{
270 int to_version = mx35_revision() >> 4;
271
Shawn Guoddd5f512011-09-28 17:16:05 +0800272 imx3_init_l2x0();
273
Shawn Guo18cb6802013-05-10 09:13:44 +0800274 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
Shawn Guo69ac71d2012-09-20 14:21:16 +0800275 mxc_device_init();
276
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200277 mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
278 mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
279 mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
Shawn Guof1263de2011-09-28 17:16:03 +0800280
Dong Aishenga2aa65a2012-05-02 19:31:20 +0800281 pinctrl_provide_dummies();
Shawn Guof1263de2011-09-28 17:16:03 +0800282 if (to_version == 1) {
283 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
284 strlen(imx35_sdma_pdata.fw_name));
285 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
286 }
287
288 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
Fabio Estevam38bb3632012-03-02 07:45:59 -0300289
290 /* Setup AIPS registers */
291 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
292 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
Linus Torvalds281b0532012-03-27 16:14:44 -0700293
Richard Zhao3bc34a62012-03-05 22:30:52 +0800294 /* i.mx35 has the i.mx31 type audmux */
295 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
296 ARRAY_SIZE(imx35_audmux_res));
Shawn Guof1263de2011-09-28 17:16:03 +0800297}
Uwe Kleine-König87514fc2011-11-22 10:07:26 +0100298#endif /* ifdef CONFIG_SOC_IMX35 */