blob: 04747868d6c4d4605ec679f21306b650b4475657 [file] [log] [blame]
Dragos Carp00b8fd22007-05-10 22:22:52 -07001/*
Grant Likely57cc0972008-05-14 16:05:29 -07002 * MPC52xx PSC in SPI mode driver.
Dragos Carp00b8fd22007-05-10 22:22:52 -07003 *
4 * Maintainer: Dragos Carp
5 *
6 * Copyright (C) 2006 TOPTICA Photonics AG.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
Anton Vorontsov73902842009-06-17 16:26:05 -070016#include <linux/types.h>
Dragos Carp00b8fd22007-05-10 22:22:52 -070017#include <linux/errno.h>
18#include <linux/interrupt.h>
Stephen Rothwell76ef7dd2008-05-23 16:35:47 +100019#include <linux/of_platform.h>
Grant Likelyad657762009-11-04 15:23:37 -070020#include <linux/of_spi.h>
Dragos Carp00b8fd22007-05-10 22:22:52 -070021#include <linux/workqueue.h>
22#include <linux/completion.h>
23#include <linux/io.h>
24#include <linux/delay.h>
25#include <linux/spi/spi.h>
26#include <linux/fsl_devices.h>
27
28#include <asm/mpc52xx.h>
29#include <asm/mpc52xx_psc.h>
30
31#define MCLK 20000000 /* PSC port MClk in hz */
32
33struct mpc52xx_psc_spi {
34 /* fsl_spi_platform data */
Anton Vorontsov73902842009-06-17 16:26:05 -070035 void (*cs_control)(struct spi_device *spi, bool on);
Dragos Carp00b8fd22007-05-10 22:22:52 -070036 u32 sysclk;
37
38 /* driver internal data */
39 struct mpc52xx_psc __iomem *psc;
Grant Likely4874cc12008-03-04 14:28:42 -080040 struct mpc52xx_psc_fifo __iomem *fifo;
Dragos Carp00b8fd22007-05-10 22:22:52 -070041 unsigned int irq;
42 u8 bits_per_word;
43 u8 busy;
44
45 struct workqueue_struct *workqueue;
46 struct work_struct work;
47
48 struct list_head queue;
49 spinlock_t lock;
50
51 struct completion done;
52};
53
54/* controller state */
55struct mpc52xx_psc_spi_cs {
56 int bits_per_word;
57 int speed_hz;
58};
59
60/* set clock freq, clock ramp, bits per work
61 * if t is NULL then reset the values to the default values
62 */
63static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
64 struct spi_transfer *t)
65{
66 struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
67
68 cs->speed_hz = (t && t->speed_hz)
69 ? t->speed_hz : spi->max_speed_hz;
70 cs->bits_per_word = (t && t->bits_per_word)
71 ? t->bits_per_word : spi->bits_per_word;
72 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
73 return 0;
74}
75
76static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
77{
78 struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
79 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
80 struct mpc52xx_psc __iomem *psc = mps->psc;
81 u32 sicr;
82 u16 ccr;
83
84 sicr = in_be32(&psc->sicr);
85
86 /* Set clock phase and polarity */
87 if (spi->mode & SPI_CPHA)
88 sicr |= 0x00001000;
89 else
90 sicr &= ~0x00001000;
91 if (spi->mode & SPI_CPOL)
92 sicr |= 0x00002000;
93 else
94 sicr &= ~0x00002000;
95
96 if (spi->mode & SPI_LSB_FIRST)
97 sicr |= 0x10000000;
98 else
99 sicr &= ~0x10000000;
100 out_be32(&psc->sicr, sicr);
101
102 /* Set clock frequency and bits per word
103 * Because psc->ccr is defined as 16bit register instead of 32bit
104 * just set the lower byte of BitClkDiv
105 */
Grant Likelya897ea12008-10-08 09:02:11 -0600106 ccr = in_be16((u16 __iomem *)&psc->ccr);
Dragos Carp00b8fd22007-05-10 22:22:52 -0700107 ccr &= 0xFF00;
108 if (cs->speed_hz)
109 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
110 else /* by default SPI Clk 1MHz */
111 ccr |= (MCLK / 1000000 - 1) & 0xFF;
Grant Likelya897ea12008-10-08 09:02:11 -0600112 out_be16((u16 __iomem *)&psc->ccr, ccr);
Dragos Carp00b8fd22007-05-10 22:22:52 -0700113 mps->bits_per_word = cs->bits_per_word;
114
Anton Vorontsov73902842009-06-17 16:26:05 -0700115 if (mps->cs_control)
116 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
Dragos Carp00b8fd22007-05-10 22:22:52 -0700117}
118
119static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
120{
121 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
122
Anton Vorontsov73902842009-06-17 16:26:05 -0700123 if (mps->cs_control)
124 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
Dragos Carp00b8fd22007-05-10 22:22:52 -0700125}
126
127#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
128/* wake up when 80% fifo full */
129#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
130
131static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
132 struct spi_transfer *t)
133{
134 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
135 struct mpc52xx_psc __iomem *psc = mps->psc;
Grant Likely4874cc12008-03-04 14:28:42 -0800136 struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700137 unsigned rb = 0; /* number of bytes receieved */
138 unsigned sb = 0; /* number of bytes sent */
139 unsigned char *rx_buf = (unsigned char *)t->rx_buf;
140 unsigned char *tx_buf = (unsigned char *)t->tx_buf;
141 unsigned rfalarm;
142 unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
143 unsigned recv_at_once;
Stefano Babicb7d271d2008-12-01 13:13:53 -0800144 int last_block = 0;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700145
146 if (!t->tx_buf && !t->rx_buf && t->len)
147 return -EINVAL;
148
149 /* enable transmiter/receiver */
150 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
151 while (rb < t->len) {
152 if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
153 rfalarm = MPC52xx_PSC_RFALARM;
Stefano Babicb7d271d2008-12-01 13:13:53 -0800154 last_block = 0;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700155 } else {
156 send_at_once = t->len - sb;
157 rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
Stefano Babicb7d271d2008-12-01 13:13:53 -0800158 last_block = 1;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700159 }
160
161 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
Luotao Fu9a7867e2008-07-28 15:46:32 -0700162 for (; send_at_once; sb++, send_at_once--) {
163 /* set EOF flag before the last word is sent */
Stefano Babicb7d271d2008-12-01 13:13:53 -0800164 if (send_at_once == 1 && last_block)
Luotao Fu9a7867e2008-07-28 15:46:32 -0700165 out_8(&psc->ircr2, 0x01);
166
167 if (tx_buf)
Dragos Carp00b8fd22007-05-10 22:22:52 -0700168 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
Luotao Fu9a7867e2008-07-28 15:46:32 -0700169 else
Dragos Carp00b8fd22007-05-10 22:22:52 -0700170 out_8(&psc->mpc52xx_psc_buffer_8, 0);
Dragos Carp00b8fd22007-05-10 22:22:52 -0700171 }
172
173
Robert P. J. Day3a4fa0a2007-10-19 23:10:43 +0200174 /* enable interrupts and wait for wake up
Dragos Carp00b8fd22007-05-10 22:22:52 -0700175 * if just one byte is expected the Rx FIFO genererates no
176 * FFULL interrupt, so activate the RxRDY interrupt
177 */
178 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
179 if (t->len - rb == 1) {
180 out_8(&psc->mode, 0);
181 } else {
182 out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
Grant Likely4874cc12008-03-04 14:28:42 -0800183 out_be16(&fifo->rfalarm, rfalarm);
Dragos Carp00b8fd22007-05-10 22:22:52 -0700184 }
185 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
186 wait_for_completion(&mps->done);
Grant Likely4874cc12008-03-04 14:28:42 -0800187 recv_at_once = in_be16(&fifo->rfnum);
Dragos Carp00b8fd22007-05-10 22:22:52 -0700188 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
189
190 send_at_once = recv_at_once;
191 if (rx_buf) {
192 for (; recv_at_once; rb++, recv_at_once--)
193 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
194 } else {
195 for (; recv_at_once; rb++, recv_at_once--)
196 in_8(&psc->mpc52xx_psc_buffer_8);
197 }
198 }
199 /* disable transmiter/receiver */
200 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
201
202 return 0;
203}
204
205static void mpc52xx_psc_spi_work(struct work_struct *work)
206{
207 struct mpc52xx_psc_spi *mps =
208 container_of(work, struct mpc52xx_psc_spi, work);
209
210 spin_lock_irq(&mps->lock);
211 mps->busy = 1;
212 while (!list_empty(&mps->queue)) {
213 struct spi_message *m;
214 struct spi_device *spi;
215 struct spi_transfer *t = NULL;
216 unsigned cs_change;
217 int status;
218
219 m = container_of(mps->queue.next, struct spi_message, queue);
220 list_del_init(&m->queue);
221 spin_unlock_irq(&mps->lock);
222
223 spi = m->spi;
224 cs_change = 1;
225 status = 0;
226 list_for_each_entry (t, &m->transfers, transfer_list) {
227 if (t->bits_per_word || t->speed_hz) {
228 status = mpc52xx_psc_spi_transfer_setup(spi, t);
229 if (status < 0)
230 break;
231 }
232
233 if (cs_change)
234 mpc52xx_psc_spi_activate_cs(spi);
235 cs_change = t->cs_change;
236
237 status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
238 if (status)
239 break;
240 m->actual_length += t->len;
241
242 if (t->delay_usecs)
243 udelay(t->delay_usecs);
244
245 if (cs_change)
246 mpc52xx_psc_spi_deactivate_cs(spi);
247 }
248
249 m->status = status;
250 m->complete(m->context);
251
252 if (status || !cs_change)
253 mpc52xx_psc_spi_deactivate_cs(spi);
254
255 mpc52xx_psc_spi_transfer_setup(spi, NULL);
256
257 spin_lock_irq(&mps->lock);
258 }
259 mps->busy = 0;
260 spin_unlock_irq(&mps->lock);
261}
262
263static int mpc52xx_psc_spi_setup(struct spi_device *spi)
264{
265 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
266 struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
267 unsigned long flags;
268
269 if (spi->bits_per_word%8)
270 return -EINVAL;
271
272 if (!cs) {
273 cs = kzalloc(sizeof *cs, GFP_KERNEL);
274 if (!cs)
275 return -ENOMEM;
276 spi->controller_state = cs;
277 }
278
279 cs->bits_per_word = spi->bits_per_word;
280 cs->speed_hz = spi->max_speed_hz;
281
282 spin_lock_irqsave(&mps->lock, flags);
283 if (!mps->busy)
284 mpc52xx_psc_spi_deactivate_cs(spi);
285 spin_unlock_irqrestore(&mps->lock, flags);
286
287 return 0;
288}
289
290static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
291 struct spi_message *m)
292{
293 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
294 unsigned long flags;
295
296 m->actual_length = 0;
297 m->status = -EINPROGRESS;
298
299 spin_lock_irqsave(&mps->lock, flags);
300 list_add_tail(&m->queue, &mps->queue);
301 queue_work(mps->workqueue, &mps->work);
302 spin_unlock_irqrestore(&mps->lock, flags);
303
304 return 0;
305}
306
307static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
308{
309 kfree(spi->controller_state);
310}
311
312static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
313{
Dragos Carp00b8fd22007-05-10 22:22:52 -0700314 struct mpc52xx_psc __iomem *psc = mps->psc;
Grant Likely4874cc12008-03-04 14:28:42 -0800315 struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700316 u32 mclken_div;
Wolfram Sangf856cf02009-11-02 03:53:11 +0000317 int ret;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700318
Dragos Carp00b8fd22007-05-10 22:22:52 -0700319 /* default sysclk is 512MHz */
Grant Likely4fb4c552008-01-24 22:25:31 -0700320 mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
Wolfram Sangf856cf02009-11-02 03:53:11 +0000321 ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
322 if (ret)
323 return ret;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700324
325 /* Reset the PSC into a known state */
326 out_8(&psc->command, MPC52xx_PSC_RST_RX);
327 out_8(&psc->command, MPC52xx_PSC_RST_TX);
328 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
329
330 /* Disable interrupts, interrupts are based on alarm level */
331 out_be16(&psc->mpc52xx_psc_imr, 0);
332 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
Grant Likely4874cc12008-03-04 14:28:42 -0800333 out_8(&fifo->rfcntl, 0);
Dragos Carp00b8fd22007-05-10 22:22:52 -0700334 out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
335
336 /* Configure 8bit codec mode as a SPI master and use EOF flags */
337 /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
338 out_be32(&psc->sicr, 0x0180C800);
Grant Likelya897ea12008-10-08 09:02:11 -0600339 out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
Dragos Carp00b8fd22007-05-10 22:22:52 -0700340
341 /* Set 2ms DTL delay */
342 out_8(&psc->ctur, 0x00);
343 out_8(&psc->ctlr, 0x84);
344
345 mps->bits_per_word = 8;
346
Wolfram Sangf856cf02009-11-02 03:53:11 +0000347 return 0;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700348}
349
350static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
351{
352 struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
353 struct mpc52xx_psc __iomem *psc = mps->psc;
354
355 /* disable interrupt and wake up the work queue */
356 if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
357 out_be16(&psc->mpc52xx_psc_imr, 0);
358 complete(&mps->done);
359 return IRQ_HANDLED;
360 }
361 return IRQ_NONE;
362}
363
364/* bus_num is used only for the case dev->platform_data == NULL */
365static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
366 u32 size, unsigned int irq, s16 bus_num)
367{
368 struct fsl_spi_platform_data *pdata = dev->platform_data;
369 struct mpc52xx_psc_spi *mps;
370 struct spi_master *master;
371 int ret;
372
Dragos Carp00b8fd22007-05-10 22:22:52 -0700373 master = spi_alloc_master(dev, sizeof *mps);
374 if (master == NULL)
375 return -ENOMEM;
376
377 dev_set_drvdata(dev, master);
378 mps = spi_master_get_devdata(master);
379
David Brownelle7db06b2009-06-17 16:26:04 -0700380 /* the spi->mode bits understood by this driver: */
381 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
382
Dragos Carp00b8fd22007-05-10 22:22:52 -0700383 mps->irq = irq;
384 if (pdata == NULL) {
385 dev_warn(dev, "probe called without platform data, no "
Anton Vorontsov73902842009-06-17 16:26:05 -0700386 "cs_control function will be called\n");
387 mps->cs_control = NULL;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700388 mps->sysclk = 0;
389 master->bus_num = bus_num;
390 master->num_chipselect = 255;
391 } else {
Anton Vorontsov73902842009-06-17 16:26:05 -0700392 mps->cs_control = pdata->cs_control;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700393 mps->sysclk = pdata->sysclk;
394 master->bus_num = pdata->bus_num;
395 master->num_chipselect = pdata->max_chipselect;
396 }
397 master->setup = mpc52xx_psc_spi_setup;
398 master->transfer = mpc52xx_psc_spi_transfer;
399 master->cleanup = mpc52xx_psc_spi_cleanup;
400
401 mps->psc = ioremap(regaddr, size);
402 if (!mps->psc) {
403 dev_err(dev, "could not ioremap I/O port range\n");
404 ret = -EFAULT;
405 goto free_master;
406 }
Grant Likely4874cc12008-03-04 14:28:42 -0800407 /* On the 5200, fifo regs are immediately ajacent to the psc regs */
408 mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
Dragos Carp00b8fd22007-05-10 22:22:52 -0700409
410 ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
411 mps);
412 if (ret)
413 goto free_master;
414
415 ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
Wolfram Sangf856cf02009-11-02 03:53:11 +0000416 if (ret < 0) {
417 dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
Dragos Carp00b8fd22007-05-10 22:22:52 -0700418 goto free_irq;
Wolfram Sangf856cf02009-11-02 03:53:11 +0000419 }
Dragos Carp00b8fd22007-05-10 22:22:52 -0700420
421 spin_lock_init(&mps->lock);
422 init_completion(&mps->done);
423 INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
424 INIT_LIST_HEAD(&mps->queue);
425
426 mps->workqueue = create_singlethread_workqueue(
Kay Sievers6c7377a2009-03-24 16:38:21 -0700427 dev_name(master->dev.parent));
Dragos Carp00b8fd22007-05-10 22:22:52 -0700428 if (mps->workqueue == NULL) {
429 ret = -EBUSY;
430 goto free_irq;
431 }
432
433 ret = spi_register_master(master);
434 if (ret < 0)
435 goto unreg_master;
436
437 return ret;
438
439unreg_master:
440 destroy_workqueue(mps->workqueue);
441free_irq:
442 free_irq(mps->irq, mps);
443free_master:
444 if (mps->psc)
445 iounmap(mps->psc);
446 spi_master_put(master);
447
448 return ret;
449}
450
451static int __exit mpc52xx_psc_spi_do_remove(struct device *dev)
452{
453 struct spi_master *master = dev_get_drvdata(dev);
454 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
455
456 flush_workqueue(mps->workqueue);
457 destroy_workqueue(mps->workqueue);
458 spi_unregister_master(master);
459 free_irq(mps->irq, mps);
460 if (mps->psc)
461 iounmap(mps->psc);
462
463 return 0;
464}
465
Dragos Carp00b8fd22007-05-10 22:22:52 -0700466static int __init mpc52xx_psc_spi_of_probe(struct of_device *op,
467 const struct of_device_id *match)
468{
469 const u32 *regaddr_p;
470 u64 regaddr64, size64;
471 s16 id = -1;
Grant Likelyad657762009-11-04 15:23:37 -0700472 int rc;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700473
474 regaddr_p = of_get_address(op->node, 0, &size64, NULL);
475 if (!regaddr_p) {
Wolfram Sang5cc17d72009-11-03 23:49:20 +0000476 dev_err(&op->dev, "Invalid PSC address\n");
Dragos Carp00b8fd22007-05-10 22:22:52 -0700477 return -EINVAL;
478 }
479 regaddr64 = of_translate_address(op->node, regaddr_p);
480
Domen Puncer88887352007-05-23 13:57:32 -0700481 /* get PSC id (1..6, used by port_config) */
Dragos Carp00b8fd22007-05-10 22:22:52 -0700482 if (op->dev.platform_data == NULL) {
Domen Puncer88887352007-05-23 13:57:32 -0700483 const u32 *psc_nump;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700484
Domen Puncer88887352007-05-23 13:57:32 -0700485 psc_nump = of_get_property(op->node, "cell-index", NULL);
486 if (!psc_nump || *psc_nump > 5) {
Wolfram Sang5cc17d72009-11-03 23:49:20 +0000487 dev_err(&op->dev, "Invalid cell-index property\n");
Domen Puncer88887352007-05-23 13:57:32 -0700488 return -EINVAL;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700489 }
Domen Puncer88887352007-05-23 13:57:32 -0700490 id = *psc_nump + 1;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700491 }
492
Grant Likelyad657762009-11-04 15:23:37 -0700493 rc = mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
Dragos Carp00b8fd22007-05-10 22:22:52 -0700494 irq_of_parse_and_map(op->node, 0), id);
Grant Likelyad657762009-11-04 15:23:37 -0700495 if (rc == 0)
496 of_register_spi_devices(dev_get_drvdata(&op->dev), op->node);
497
498 return rc;
Dragos Carp00b8fd22007-05-10 22:22:52 -0700499}
500
501static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op)
502{
503 return mpc52xx_psc_spi_do_remove(&op->dev);
504}
505
Márton Németh631e61b2010-01-20 13:49:44 -0700506static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
Grant Likely66ffbe42008-01-24 22:25:31 -0700507 { .compatible = "fsl,mpc5200-psc-spi", },
508 { .compatible = "mpc5200-psc-spi", }, /* old */
509 {}
Dragos Carp00b8fd22007-05-10 22:22:52 -0700510};
511
512MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
513
514static struct of_platform_driver mpc52xx_psc_spi_of_driver = {
515 .owner = THIS_MODULE,
516 .name = "mpc52xx-psc-spi",
517 .match_table = mpc52xx_psc_spi_of_match,
518 .probe = mpc52xx_psc_spi_of_probe,
519 .remove = __exit_p(mpc52xx_psc_spi_of_remove),
520 .driver = {
521 .name = "mpc52xx-psc-spi",
522 .owner = THIS_MODULE,
523 },
524};
525
526static int __init mpc52xx_psc_spi_init(void)
527{
528 return of_register_platform_driver(&mpc52xx_psc_spi_of_driver);
529}
530module_init(mpc52xx_psc_spi_init);
531
532static void __exit mpc52xx_psc_spi_exit(void)
533{
534 of_unregister_platform_driver(&mpc52xx_psc_spi_of_driver);
535}
536module_exit(mpc52xx_psc_spi_exit);
537
Dragos Carp00b8fd22007-05-10 22:22:52 -0700538MODULE_AUTHOR("Dragos Carp");
539MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
540MODULE_LICENSE("GPL");