Roger Chen | 53a8393 | 2014-12-29 17:44:34 +0800 | [diff] [blame] | 1 | Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC) |
| 2 | |
| 3 | The device node has following properties. |
| 4 | |
| 5 | Required properties: |
Roger Chen | ba289af | 2016-09-02 01:49:59 +0800 | [diff] [blame] | 6 | - compatible: should be "rockchip,<name>-gamc" |
| 7 | "rockchip,rk3228-gmac": found on RK322x SoCs |
| 8 | "rockchip,rk3288-gmac": found on RK3288 SoCs |
| 9 | "rockchip,rk3366-gmac": found on RK3366 SoCs |
| 10 | "rockchip,rk3368-gmac": found on RK3368 SoCs |
| 11 | "rockchip,rk3399-gmac": found on RK3399 SoCs |
Roger Chen | 53a8393 | 2014-12-29 17:44:34 +0800 | [diff] [blame] | 12 | - reg: addresses and length of the register sets for the device. |
| 13 | - interrupts: Should contain the GMAC interrupts. |
| 14 | - interrupt-names: Should contain the interrupt names "macirq". |
| 15 | - rockchip,grf: phandle to the syscon grf used to control speed and mode. |
| 16 | - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY. |
| 17 | <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC |
| 18 | <&cru SCLK_MAC_RX>: clock gate for RX |
| 19 | <&cru SCLK_MAC_TX>: clock gate for TX |
| 20 | <&cru SCLK_MACREF>: clock gate for RMII referce clock |
| 21 | <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output |
| 22 | <&cru ACLK_GMAC>: AXI clock gate for GMAC |
| 23 | <&cru PCLK_GMAC>: APB clock gate for GMAC |
| 24 | - clock-names: One name for each entry in the clocks property. |
| 25 | - phy-mode: See ethernet.txt file in the same directory. |
| 26 | - pinctrl-names: Names corresponding to the numbered pinctrl states. |
| 27 | - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>. |
| 28 | - clock_in_out: For RGMII, it must be "input", means main clock(125MHz) |
| 29 | is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means |
| 30 | PHY provides the reference clock(50MHz), "output" means GMAC provides the |
| 31 | reference clock. |
| 32 | - snps,reset-gpio gpio number for phy reset. |
| 33 | - snps,reset-active-low boolean flag to indicate if phy reset is active low. |
| 34 | - assigned-clocks: main clock, should be <&cru SCLK_MAC>; |
| 35 | - assigned-clock-parents = parent of main clock. |
| 36 | can be <&ext_gmac> or <&cru SCLK_MAC_PLL>. |
| 37 | |
| 38 | Optional properties: |
| 39 | - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default. |
| 40 | - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default. |
Romain Perier | 384dd55 | 2015-01-20 07:09:40 +0000 | [diff] [blame] | 41 | - phy-supply: phandle to a regulator if the PHY needs one |
Roger Chen | 53a8393 | 2014-12-29 17:44:34 +0800 | [diff] [blame] | 42 | |
| 43 | Example: |
| 44 | |
| 45 | gmac: ethernet@ff290000 { |
| 46 | compatible = "rockchip,rk3288-gmac"; |
| 47 | reg = <0xff290000 0x10000>; |
| 48 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| 49 | interrupt-names = "macirq"; |
| 50 | rockchip,grf = <&grf>; |
| 51 | clocks = <&cru SCLK_MAC>, |
| 52 | <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, |
| 53 | <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, |
| 54 | <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; |
| 55 | clock-names = "stmmaceth", |
| 56 | "mac_clk_rx", "mac_clk_tx", |
| 57 | "clk_mac_ref", "clk_mac_refout", |
| 58 | "aclk_mac", "pclk_mac"; |
| 59 | phy-mode = "rgmii"; |
| 60 | pinctrl-names = "default"; |
| 61 | pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>; |
| 62 | |
| 63 | clock_in_out = "input"; |
| 64 | snps,reset-gpio = <&gpio4 7 0>; |
| 65 | snps,reset-active-low; |
| 66 | |
| 67 | assigned-clocks = <&cru SCLK_MAC>; |
| 68 | assigned-clock-parents = <&ext_gmac>; |
| 69 | tx_delay = <0x30>; |
| 70 | rx_delay = <0x10>; |
| 71 | |
| 72 | status = "ok"; |
| 73 | }; |