Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/kernel/setup.c |
| 3 | * |
| 4 | * Copyright (C) 1995-2001 Russell King |
| 5 | * Copyright (C) 2012 ARM Ltd. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
Al Stone | 3765516 | 2015-03-24 14:02:37 +0000 | [diff] [blame] | 20 | #include <linux/acpi.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 21 | #include <linux/export.h> |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/stddef.h> |
| 24 | #include <linux/ioport.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/utsname.h> |
| 27 | #include <linux/initrd.h> |
| 28 | #include <linux/console.h> |
Catalin Marinas | a41dc0e | 2014-04-03 17:48:54 +0100 | [diff] [blame] | 29 | #include <linux/cache.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 30 | #include <linux/bootmem.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 31 | #include <linux/screen_info.h> |
| 32 | #include <linux/init.h> |
| 33 | #include <linux/kexec.h> |
| 34 | #include <linux/crash_dump.h> |
| 35 | #include <linux/root_dev.h> |
| 36 | #include <linux/cpu.h> |
| 37 | #include <linux/interrupt.h> |
| 38 | #include <linux/smp.h> |
| 39 | #include <linux/fs.h> |
| 40 | #include <linux/proc_fs.h> |
| 41 | #include <linux/memblock.h> |
| 42 | #include <linux/of_fdt.h> |
Mark Salter | f84d027 | 2014-04-15 21:59:30 -0400 | [diff] [blame] | 43 | #include <linux/efi.h> |
Mark Rutland | bff6079 | 2015-07-31 15:46:16 +0100 | [diff] [blame] | 44 | #include <linux/psci.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 45 | |
Al Stone | 3765516 | 2015-03-24 14:02:37 +0000 | [diff] [blame] | 46 | #include <asm/acpi.h> |
Mark Salter | bf4b558 | 2014-04-07 15:39:52 -0700 | [diff] [blame] | 47 | #include <asm/fixmap.h> |
Mark Rutland | df85741 | 2014-07-16 16:32:44 +0100 | [diff] [blame] | 48 | #include <asm/cpu.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 49 | #include <asm/cputype.h> |
| 50 | #include <asm/elf.h> |
Andre Przywara | 930da09 | 2014-11-14 15:54:07 +0000 | [diff] [blame] | 51 | #include <asm/cpufeature.h> |
Mark Rutland | e8765b2 | 2013-10-24 20:30:17 +0100 | [diff] [blame] | 52 | #include <asm/cpu_ops.h> |
Andrey Ryabinin | 39d114d | 2015-10-12 18:52:58 +0300 | [diff] [blame] | 53 | #include <asm/kasan.h> |
Ganapatrao Kulkarni | 1a2db30 | 2016-04-08 15:50:27 -0700 | [diff] [blame] | 54 | #include <asm/numa.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 55 | #include <asm/sections.h> |
| 56 | #include <asm/setup.h> |
Javi Merino | 4c7aa00 | 2012-08-29 09:47:19 +0100 | [diff] [blame] | 57 | #include <asm/smp_plat.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 58 | #include <asm/cacheflush.h> |
| 59 | #include <asm/tlbflush.h> |
| 60 | #include <asm/traps.h> |
| 61 | #include <asm/memblock.h> |
Mark Salter | f84d027 | 2014-04-15 21:59:30 -0400 | [diff] [blame] | 62 | #include <asm/efi.h> |
Stefano Stabellini | 5882bfe | 2015-05-06 14:13:31 +0000 | [diff] [blame] | 63 | #include <asm/xen/hypervisor.h> |
Mark Rutland | 9e8e865 | 2016-01-25 11:44:58 +0000 | [diff] [blame] | 64 | #include <asm/mmu_context.h> |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 65 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 66 | phys_addr_t __fdt_pointer __initdata; |
| 67 | |
| 68 | /* |
| 69 | * Standard memory resources |
| 70 | */ |
| 71 | static struct resource mem_res[] = { |
| 72 | { |
| 73 | .name = "Kernel code", |
| 74 | .start = 0, |
| 75 | .end = 0, |
Toshi Kani | 35d98e9 | 2016-01-26 21:57:22 +0100 | [diff] [blame] | 76 | .flags = IORESOURCE_SYSTEM_RAM |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 77 | }, |
| 78 | { |
| 79 | .name = "Kernel data", |
| 80 | .start = 0, |
| 81 | .end = 0, |
Toshi Kani | 35d98e9 | 2016-01-26 21:57:22 +0100 | [diff] [blame] | 82 | .flags = IORESOURCE_SYSTEM_RAM |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 83 | } |
| 84 | }; |
| 85 | |
| 86 | #define kernel_code mem_res[0] |
| 87 | #define kernel_data mem_res[1] |
| 88 | |
Ard Biesheuvel | da9c177 | 2015-03-17 10:55:12 +0100 | [diff] [blame] | 89 | /* |
| 90 | * The recorded values of x0 .. x3 upon kernel entry. |
| 91 | */ |
| 92 | u64 __cacheline_aligned boot_args[4]; |
| 93 | |
Will Deacon | 7158627 | 2013-11-05 18:10:47 +0000 | [diff] [blame] | 94 | void __init smp_setup_processor_id(void) |
| 95 | { |
Mark Rutland | 8070867 | 2014-11-04 10:50:16 +0000 | [diff] [blame] | 96 | u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; |
| 97 | cpu_logical_map(0) = mpidr; |
| 98 | |
Will Deacon | 7158627 | 2013-11-05 18:10:47 +0000 | [diff] [blame] | 99 | /* |
| 100 | * clear __my_cpu_offset on boot CPU to avoid hang caused by |
| 101 | * using percpu variable early, for example, lockdep will |
| 102 | * access percpu variable inside lock_release |
| 103 | */ |
| 104 | set_my_cpu_offset(0); |
Mark Rutland | 8070867 | 2014-11-04 10:50:16 +0000 | [diff] [blame] | 105 | pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr); |
Will Deacon | 7158627 | 2013-11-05 18:10:47 +0000 | [diff] [blame] | 106 | } |
| 107 | |
Sudeep KarkadaNagesha | 6e15d0e | 2013-10-21 13:29:42 +0100 | [diff] [blame] | 108 | bool arch_match_cpu_phys_id(int cpu, u64 phys_id) |
| 109 | { |
| 110 | return phys_id == cpu_logical_map(cpu); |
| 111 | } |
| 112 | |
Lorenzo Pieralisi | 976d7d3 | 2013-05-16 10:32:09 +0100 | [diff] [blame] | 113 | struct mpidr_hash mpidr_hash; |
Lorenzo Pieralisi | 976d7d3 | 2013-05-16 10:32:09 +0100 | [diff] [blame] | 114 | /** |
| 115 | * smp_build_mpidr_hash - Pre-compute shifts required at each affinity |
| 116 | * level in order to build a linear index from an |
| 117 | * MPIDR value. Resulting algorithm is a collision |
| 118 | * free hash carried out through shifting and ORing |
| 119 | */ |
| 120 | static void __init smp_build_mpidr_hash(void) |
| 121 | { |
| 122 | u32 i, affinity, fs[4], bits[4], ls; |
| 123 | u64 mask = 0; |
| 124 | /* |
| 125 | * Pre-scan the list of MPIDRS and filter out bits that do |
| 126 | * not contribute to affinity levels, ie they never toggle. |
| 127 | */ |
| 128 | for_each_possible_cpu(i) |
| 129 | mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); |
| 130 | pr_debug("mask of set bits %#llx\n", mask); |
| 131 | /* |
| 132 | * Find and stash the last and first bit set at all affinity levels to |
| 133 | * check how many bits are required to represent them. |
| 134 | */ |
| 135 | for (i = 0; i < 4; i++) { |
| 136 | affinity = MPIDR_AFFINITY_LEVEL(mask, i); |
| 137 | /* |
| 138 | * Find the MSB bit and LSB bits position |
| 139 | * to determine how many bits are required |
| 140 | * to express the affinity level. |
| 141 | */ |
| 142 | ls = fls(affinity); |
| 143 | fs[i] = affinity ? ffs(affinity) - 1 : 0; |
| 144 | bits[i] = ls - fs[i]; |
| 145 | } |
| 146 | /* |
| 147 | * An index can be created from the MPIDR_EL1 by isolating the |
| 148 | * significant bits at each affinity level and by shifting |
| 149 | * them in order to compress the 32 bits values space to a |
| 150 | * compressed set of values. This is equivalent to hashing |
| 151 | * the MPIDR_EL1 through shifting and ORing. It is a collision free |
| 152 | * hash though not minimal since some levels might contain a number |
| 153 | * of CPUs that is not an exact power of 2 and their bit |
| 154 | * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}. |
| 155 | */ |
| 156 | mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0]; |
| 157 | mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; |
| 158 | mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - |
| 159 | (bits[1] + bits[0]); |
| 160 | mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) + |
| 161 | fs[3] - (bits[2] + bits[1] + bits[0]); |
| 162 | mpidr_hash.mask = mask; |
| 163 | mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0]; |
| 164 | pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n", |
| 165 | mpidr_hash.shift_aff[0], |
| 166 | mpidr_hash.shift_aff[1], |
| 167 | mpidr_hash.shift_aff[2], |
| 168 | mpidr_hash.shift_aff[3], |
| 169 | mpidr_hash.mask, |
| 170 | mpidr_hash.bits); |
| 171 | /* |
| 172 | * 4x is an arbitrary value used to warn on a hash table much bigger |
| 173 | * than expected on most systems. |
| 174 | */ |
| 175 | if (mpidr_hash_size() > 4 * num_possible_cpus()) |
| 176 | pr_warn("Large number of MPIDR hash buckets detected\n"); |
Lorenzo Pieralisi | 976d7d3 | 2013-05-16 10:32:09 +0100 | [diff] [blame] | 177 | } |
Mark Rutland | 137650aa | 2015-03-13 16:14:34 +0000 | [diff] [blame] | 178 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 179 | static void __init setup_machine_fdt(phys_addr_t dt_phys) |
| 180 | { |
Ard Biesheuvel | 61bd93c | 2015-06-01 13:40:32 +0200 | [diff] [blame] | 181 | void *dt_virt = fixmap_remap_fdt(dt_phys); |
| 182 | |
| 183 | if (!dt_virt || !early_init_dt_scan(dt_virt)) { |
| 184 | pr_crit("\n" |
| 185 | "Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n" |
| 186 | "The dtb must be 8-byte aligned and must not exceed 2 MB in size\n" |
| 187 | "\nPlease check your bootloader.", |
| 188 | &dt_phys, dt_virt); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 189 | |
| 190 | while (true) |
| 191 | cpu_relax(); |
| 192 | } |
Will Deacon | 5e39977 | 2014-09-01 15:47:19 +0100 | [diff] [blame] | 193 | |
Mark Rutland | 44b82b7 | 2014-10-24 14:56:40 +0100 | [diff] [blame] | 194 | dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name()); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 195 | } |
| 196 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 197 | static void __init request_standard_resources(void) |
| 198 | { |
| 199 | struct memblock_region *region; |
| 200 | struct resource *res; |
| 201 | |
| 202 | kernel_code.start = virt_to_phys(_text); |
Ard Biesheuvel | 9fdc14c5 | 2016-06-23 15:53:17 +0200 | [diff] [blame] | 203 | kernel_code.end = virt_to_phys(__init_begin - 1); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 204 | kernel_data.start = virt_to_phys(_sdata); |
| 205 | kernel_data.end = virt_to_phys(_end - 1); |
| 206 | |
| 207 | for_each_memblock(memory, region) { |
| 208 | res = alloc_bootmem_low(sizeof(*res)); |
AKASHI Takahiro | e7cd190 | 2016-08-22 15:55:24 +0900 | [diff] [blame] | 209 | if (memblock_is_nomap(region)) { |
| 210 | res->name = "reserved"; |
| 211 | res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; |
| 212 | } else { |
| 213 | res->name = "System RAM"; |
| 214 | res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY; |
| 215 | } |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 216 | res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region)); |
| 217 | res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1; |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 218 | |
| 219 | request_resource(&iomem_resource, res); |
| 220 | |
| 221 | if (kernel_code.start >= res->start && |
| 222 | kernel_code.end <= res->end) |
| 223 | request_resource(res, &kernel_code); |
| 224 | if (kernel_data.start >= res->start && |
| 225 | kernel_data.end <= res->end) |
| 226 | request_resource(res, &kernel_data); |
| 227 | } |
| 228 | } |
| 229 | |
Javi Merino | 4c7aa00 | 2012-08-29 09:47:19 +0100 | [diff] [blame] | 230 | u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; |
| 231 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 232 | void __init setup_arch(char **cmdline_p) |
| 233 | { |
Suzuki K. Poulose | 4b998ff | 2015-10-19 14:24:40 +0100 | [diff] [blame] | 234 | pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id()); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 235 | |
Michal Marek | cfa88c7 | 2016-08-30 10:31:35 +0200 | [diff] [blame] | 236 | sprintf(init_utsname()->machine, UTS_MACHINE); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 237 | init_mm.start_code = (unsigned long) _text; |
| 238 | init_mm.end_code = (unsigned long) _etext; |
| 239 | init_mm.end_data = (unsigned long) _edata; |
| 240 | init_mm.brk = (unsigned long) _end; |
| 241 | |
| 242 | *cmdline_p = boot_command_line; |
| 243 | |
Laura Abbott | af86e59 | 2014-11-21 21:50:42 +0000 | [diff] [blame] | 244 | early_fixmap_init(); |
Mark Salter | bf4b558 | 2014-04-07 15:39:52 -0700 | [diff] [blame] | 245 | early_ioremap_init(); |
Mark Salter | 0bf757c | 2014-04-07 15:39:51 -0700 | [diff] [blame] | 246 | |
Ard Biesheuvel | 61bd93c | 2015-06-01 13:40:32 +0200 | [diff] [blame] | 247 | setup_machine_fdt(__fdt_pointer); |
| 248 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 249 | parse_early_param(); |
| 250 | |
Jon Masters | 7a9c43b | 2014-08-26 21:23:38 +0100 | [diff] [blame] | 251 | /* |
| 252 | * Unmask asynchronous aborts after bringing up possible earlycon. |
| 253 | * (Report possible System Errors once we can report this occurred) |
| 254 | */ |
| 255 | local_async_enable(); |
| 256 | |
Mark Rutland | 86ccce8 | 2016-01-25 11:44:59 +0000 | [diff] [blame] | 257 | /* |
| 258 | * TTBR0 is only used for the identity mapping at this stage. Make it |
| 259 | * point to zero page to avoid speculatively fetching new entries. |
| 260 | */ |
| 261 | cpu_uninstall_idmap(); |
| 262 | |
Shannon Zhao | 9b08aaa | 2016-04-07 20:03:28 +0800 | [diff] [blame] | 263 | xen_early_init(); |
Mark Salter | f84d027 | 2014-04-15 21:59:30 -0400 | [diff] [blame] | 264 | efi_init(); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 265 | arm64_memblock_init(); |
| 266 | |
Jon Masters | 38b04a7 | 2016-06-20 13:56:13 +0300 | [diff] [blame] | 267 | paging_init(); |
| 268 | |
| 269 | acpi_table_upgrade(); |
| 270 | |
Al Stone | 3765516 | 2015-03-24 14:02:37 +0000 | [diff] [blame] | 271 | /* Parse the ACPI tables for possible boot-time configuration */ |
| 272 | acpi_boot_table_init(); |
| 273 | |
David Daney | 3194ac6 | 2016-04-08 15:50:26 -0700 | [diff] [blame] | 274 | if (acpi_disabled) |
| 275 | unflatten_device_tree(); |
| 276 | |
| 277 | bootmem_init(); |
| 278 | |
Andrey Ryabinin | 39d114d | 2015-10-12 18:52:58 +0300 | [diff] [blame] | 279 | kasan_init(); |
| 280 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 281 | request_standard_resources(); |
| 282 | |
Ard Biesheuvel | 0e63ea4 | 2015-01-08 09:54:58 +0000 | [diff] [blame] | 283 | early_ioremap_reset(); |
Mark Salter | f84d027 | 2014-04-15 21:59:30 -0400 | [diff] [blame] | 284 | |
David Daney | 3194ac6 | 2016-04-08 15:50:26 -0700 | [diff] [blame] | 285 | if (acpi_disabled) |
Graeme Gregory | 7c59a3d | 2015-03-24 14:02:43 +0000 | [diff] [blame] | 286 | psci_dt_init(); |
David Daney | 3194ac6 | 2016-04-08 15:50:26 -0700 | [diff] [blame] | 287 | else |
Graeme Gregory | 7c59a3d | 2015-03-24 14:02:43 +0000 | [diff] [blame] | 288 | psci_acpi_init(); |
David Daney | 3194ac6 | 2016-04-08 15:50:26 -0700 | [diff] [blame] | 289 | |
Lorenzo Pieralisi | 0f07833 | 2015-05-13 14:12:47 +0100 | [diff] [blame] | 290 | cpu_read_bootcpu_ops(); |
Lorenzo Pieralisi | 0f07833 | 2015-05-13 14:12:47 +0100 | [diff] [blame] | 291 | smp_init_cpus(); |
Lorenzo Pieralisi | 976d7d3 | 2013-05-16 10:32:09 +0100 | [diff] [blame] | 292 | smp_build_mpidr_hash(); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 293 | |
| 294 | #ifdef CONFIG_VT |
| 295 | #if defined(CONFIG_VGA_CONSOLE) |
| 296 | conswitchp = &vga_con; |
| 297 | #elif defined(CONFIG_DUMMY_CONSOLE) |
| 298 | conswitchp = &dummy_con; |
| 299 | #endif |
| 300 | #endif |
Ard Biesheuvel | da9c177 | 2015-03-17 10:55:12 +0100 | [diff] [blame] | 301 | if (boot_args[1] || boot_args[2] || boot_args[3]) { |
| 302 | pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n" |
| 303 | "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n" |
| 304 | "This indicates a broken bootloader or old kernel\n", |
| 305 | boot_args[1], boot_args[2], boot_args[3]); |
| 306 | } |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 307 | } |
| 308 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 309 | static int __init topology_init(void) |
| 310 | { |
| 311 | int i; |
| 312 | |
Ganapatrao Kulkarni | 1a2db30 | 2016-04-08 15:50:27 -0700 | [diff] [blame] | 313 | for_each_online_node(i) |
| 314 | register_one_node(i); |
| 315 | |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 316 | for_each_possible_cpu(i) { |
Mark Rutland | df85741 | 2014-07-16 16:32:44 +0100 | [diff] [blame] | 317 | struct cpu *cpu = &per_cpu(cpu_data.cpu, i); |
Catalin Marinas | 9703d9d | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 318 | cpu->hotpluggable = 1; |
| 319 | register_cpu(cpu, i); |
| 320 | } |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | subsys_initcall(topology_init); |
Ard Biesheuvel | f80fb3a | 2016-01-26 14:12:01 +0100 | [diff] [blame] | 325 | |
| 326 | /* |
| 327 | * Dump out kernel offset information on panic. |
| 328 | */ |
| 329 | static int dump_kernel_offset(struct notifier_block *self, unsigned long v, |
| 330 | void *p) |
| 331 | { |
| 332 | u64 const kaslr_offset = kimage_vaddr - KIMAGE_VADDR; |
| 333 | |
| 334 | if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset > 0) { |
| 335 | pr_emerg("Kernel Offset: 0x%llx from 0x%lx\n", |
| 336 | kaslr_offset, KIMAGE_VADDR); |
| 337 | } else { |
| 338 | pr_emerg("Kernel Offset: disabled\n"); |
| 339 | } |
| 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | static struct notifier_block kernel_offset_notifier = { |
| 344 | .notifier_call = dump_kernel_offset |
| 345 | }; |
| 346 | |
| 347 | static int __init register_kernel_offset_dumper(void) |
| 348 | { |
| 349 | atomic_notifier_chain_register(&panic_notifier_list, |
| 350 | &kernel_offset_notifier); |
| 351 | return 0; |
| 352 | } |
| 353 | __initcall(register_kernel_offset_dumper); |