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Rabin Vincent03f822f2010-07-02 16:52:09 +05301/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
Rabin Vincent03f822f2010-07-02 16:52:09 +05308#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/slab.h>
11#include <linux/gpio.h>
Rabin Vincent03f822f2010-07-02 16:52:09 +053012#include <linux/interrupt.h>
Vipul Kumar Samar86605cf2012-11-26 17:06:51 +053013#include <linux/of.h>
Rabin Vincent03f822f2010-07-02 16:52:09 +053014#include <linux/mfd/stmpe.h>
Linus Walleij27ec8a92014-10-02 07:55:41 +020015#include <linux/seq_file.h>
Linus Walleij96b2cca2016-09-27 15:59:12 -070016#include <linux/bitops.h>
Rabin Vincent03f822f2010-07-02 16:52:09 +053017
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_RE, REG_FE, REG_IE };
23
Patrice Chotard43db2892016-08-10 09:39:12 +020024enum { LSB, CSB, MSB };
25
Rabin Vincent03f822f2010-07-02 16:52:09 +053026#define CACHE_NR_REGS 3
Linus Walleij9e9dc7d2014-05-08 23:16:34 +020027/* No variant has more than 24 GPIOs */
28#define CACHE_NR_BANKS (24 / 8)
Rabin Vincent03f822f2010-07-02 16:52:09 +053029
30struct stmpe_gpio {
31 struct gpio_chip chip;
32 struct stmpe *stmpe;
33 struct device *dev;
34 struct mutex irq_lock;
Linus Walleij1dfb4a02015-01-13 08:00:29 +010035 u32 norequest_mask;
Rabin Vincent03f822f2010-07-02 16:52:09 +053036 /* Caches of interrupt control registers for bus_lock */
37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
39};
40
Rabin Vincent03f822f2010-07-02 16:52:09 +053041static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
42{
Linus Walleijb03c04a2015-12-07 14:32:13 +010043 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
Rabin Vincent03f822f2010-07-02 16:52:09 +053044 struct stmpe *stmpe = stmpe_gpio->stmpe;
Patrice Chotard43db2892016-08-10 09:39:12 +020045 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
Linus Walleij4e2678b2016-09-27 16:11:10 -070046 u8 mask = BIT(offset % 8);
Rabin Vincent03f822f2010-07-02 16:52:09 +053047 int ret;
48
49 ret = stmpe_reg_read(stmpe, reg);
50 if (ret < 0)
51 return ret;
52
Bhupesh Sharma7535b8b2012-02-27 11:19:43 +053053 return !!(ret & mask);
Rabin Vincent03f822f2010-07-02 16:52:09 +053054}
55
56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57{
Linus Walleijb03c04a2015-12-07 14:32:13 +010058 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
Rabin Vincent03f822f2010-07-02 16:52:09 +053059 struct stmpe *stmpe = stmpe_gpio->stmpe;
60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
Patrice Chotard43db2892016-08-10 09:39:12 +020061 u8 reg = stmpe->regs[which + (offset / 8)];
Linus Walleij4e2678b2016-09-27 16:11:10 -070062 u8 mask = BIT(offset % 8);
Rabin Vincent03f822f2010-07-02 16:52:09 +053063
Viresh Kumarcccdceb2011-12-14 09:28:27 +053064 /*
65 * Some variants have single register for gpio set/clear functionality.
66 * For them we need to write 0 to clear and 1 to set.
67 */
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
70 else
71 stmpe_reg_write(stmpe, reg, mask);
Rabin Vincent03f822f2010-07-02 16:52:09 +053072}
73
Linus Walleij8e293fb2016-04-28 15:00:18 +020074static int stmpe_gpio_get_direction(struct gpio_chip *chip,
75 unsigned offset)
76{
77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
78 struct stmpe *stmpe = stmpe_gpio->stmpe;
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
Linus Walleij4e2678b2016-09-27 16:11:10 -070080 u8 mask = BIT(offset % 8);
Linus Walleij8e293fb2016-04-28 15:00:18 +020081 int ret;
82
83 ret = stmpe_reg_read(stmpe, reg);
84 if (ret < 0)
85 return ret;
86
87 return !(ret & mask);
88}
89
Rabin Vincent03f822f2010-07-02 16:52:09 +053090static int stmpe_gpio_direction_output(struct gpio_chip *chip,
91 unsigned offset, int val)
92{
Linus Walleijb03c04a2015-12-07 14:32:13 +010093 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
Rabin Vincent03f822f2010-07-02 16:52:09 +053094 struct stmpe *stmpe = stmpe_gpio->stmpe;
Patrice Chotard43db2892016-08-10 09:39:12 +020095 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
Linus Walleij4e2678b2016-09-27 16:11:10 -070096 u8 mask = BIT(offset % 8);
Rabin Vincent03f822f2010-07-02 16:52:09 +053097
98 stmpe_gpio_set(chip, offset, val);
99
100 return stmpe_set_bits(stmpe, reg, mask, mask);
101}
102
103static int stmpe_gpio_direction_input(struct gpio_chip *chip,
104 unsigned offset)
105{
Linus Walleijb03c04a2015-12-07 14:32:13 +0100106 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530107 struct stmpe *stmpe = stmpe_gpio->stmpe;
Patrice Chotard43db2892016-08-10 09:39:12 +0200108 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
Linus Walleij4e2678b2016-09-27 16:11:10 -0700109 u8 mask = BIT(offset % 8);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530110
111 return stmpe_set_bits(stmpe, reg, mask, 0);
112}
113
Rabin Vincent03f822f2010-07-02 16:52:09 +0530114static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
115{
Linus Walleijb03c04a2015-12-07 14:32:13 +0100116 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530117 struct stmpe *stmpe = stmpe_gpio->stmpe;
118
Linus Walleij4e2678b2016-09-27 16:11:10 -0700119 if (stmpe_gpio->norequest_mask & BIT(offset))
Wolfram Sangb8e9cf02010-08-16 17:14:44 +0200120 return -EINVAL;
121
Linus Walleij4e2678b2016-09-27 16:11:10 -0700122 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530123}
124
Julia Lawalle35b5ab2016-09-11 14:14:37 +0200125static const struct gpio_chip template_chip = {
Rabin Vincent03f822f2010-07-02 16:52:09 +0530126 .label = "stmpe",
127 .owner = THIS_MODULE,
Linus Walleij8e293fb2016-04-28 15:00:18 +0200128 .get_direction = stmpe_gpio_get_direction,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530129 .direction_input = stmpe_gpio_direction_input,
130 .get = stmpe_gpio_get,
131 .direction_output = stmpe_gpio_direction_output,
132 .set = stmpe_gpio_set,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530133 .request = stmpe_gpio_request,
Linus Walleij9fb1f392013-12-04 14:42:46 +0100134 .can_sleep = true,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530135};
136
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800137static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530138{
Linus Walleijfe44e702014-04-15 23:38:56 +0200139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijb03c04a2015-12-07 14:32:13 +0100140 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
Lee Jonesfc13d5a2012-12-10 10:07:54 +0000141 int offset = d->hwirq;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530142 int regoffset = offset / 8;
Linus Walleij4e2678b2016-09-27 16:11:10 -0700143 int mask = BIT(offset % 8);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530144
Linus Walleij1fe3bd92014-10-02 07:55:27 +0200145 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530146 return -EINVAL;
147
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200148 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
149 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
150 stmpe_gpio->stmpe->partnum == STMPE1600)
Viresh Kumarcccdceb2011-12-14 09:28:27 +0530151 return 0;
152
Linus Walleij1fe3bd92014-10-02 07:55:27 +0200153 if (type & IRQ_TYPE_EDGE_RISING)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530154 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
155 else
156 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
157
Linus Walleij1fe3bd92014-10-02 07:55:27 +0200158 if (type & IRQ_TYPE_EDGE_FALLING)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530159 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
160 else
161 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
162
163 return 0;
164}
165
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800166static void stmpe_gpio_irq_lock(struct irq_data *d)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530167{
Linus Walleijfe44e702014-04-15 23:38:56 +0200168 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijb03c04a2015-12-07 14:32:13 +0100169 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530170
171 mutex_lock(&stmpe_gpio->irq_lock);
172}
173
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800174static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530175{
Linus Walleijfe44e702014-04-15 23:38:56 +0200176 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijb03c04a2015-12-07 14:32:13 +0100177 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530178 struct stmpe *stmpe = stmpe_gpio->stmpe;
179 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
Patrice Chotard43db2892016-08-10 09:39:12 +0200180 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
181 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
182 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
183 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
184 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
185 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
186 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
187 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
188 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
189 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530190 };
191 int i, j;
192
193 for (i = 0; i < CACHE_NR_REGS; i++) {
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200194 /* STMPE801 and STMPE1600 don't have RE and FE registers */
195 if ((stmpe->partnum == STMPE801 ||
196 stmpe->partnum == STMPE1600) &&
197 (i != REG_IE))
Viresh Kumarcccdceb2011-12-14 09:28:27 +0530198 continue;
199
Rabin Vincent03f822f2010-07-02 16:52:09 +0530200 for (j = 0; j < num_banks; j++) {
201 u8 old = stmpe_gpio->oldregs[i][j];
202 u8 new = stmpe_gpio->regs[i][j];
203
204 if (new == old)
205 continue;
206
207 stmpe_gpio->oldregs[i][j] = new;
Patrice Chotard43db2892016-08-10 09:39:12 +0200208 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530209 }
210 }
211
212 mutex_unlock(&stmpe_gpio->irq_lock);
213}
214
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800215static void stmpe_gpio_irq_mask(struct irq_data *d)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530216{
Linus Walleijfe44e702014-04-15 23:38:56 +0200217 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijb03c04a2015-12-07 14:32:13 +0100218 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
Lee Jonesfc13d5a2012-12-10 10:07:54 +0000219 int offset = d->hwirq;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530220 int regoffset = offset / 8;
Linus Walleij4e2678b2016-09-27 16:11:10 -0700221 int mask = BIT(offset % 8);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530222
223 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
224}
225
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800226static void stmpe_gpio_irq_unmask(struct irq_data *d)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530227{
Linus Walleijfe44e702014-04-15 23:38:56 +0200228 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijb03c04a2015-12-07 14:32:13 +0100229 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200230 struct stmpe *stmpe = stmpe_gpio->stmpe;
Lee Jonesfc13d5a2012-12-10 10:07:54 +0000231 int offset = d->hwirq;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530232 int regoffset = offset / 8;
Linus Walleij4e2678b2016-09-27 16:11:10 -0700233 int mask = BIT(offset % 8);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530234
235 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200236
237 /*
238 * STMPE1600 workaround: to be able to get IRQ from pins,
239 * a read must be done on GPMR register, or a write in
240 * GPSR or GPCR registers
241 */
242 if (stmpe->partnum == STMPE1600)
243 stmpe_reg_read(stmpe,
244 stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530245}
246
Linus Walleij27ec8a92014-10-02 07:55:41 +0200247static void stmpe_dbg_show_one(struct seq_file *s,
248 struct gpio_chip *gc,
249 unsigned offset, unsigned gpio)
250{
Linus Walleijb03c04a2015-12-07 14:32:13 +0100251 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
Linus Walleij27ec8a92014-10-02 07:55:41 +0200252 struct stmpe *stmpe = stmpe_gpio->stmpe;
253 const char *label = gpiochip_is_requested(gc, offset);
Linus Walleij27ec8a92014-10-02 07:55:41 +0200254 bool val = !!stmpe_gpio_get(gc, offset);
Patrice Chotard43db2892016-08-10 09:39:12 +0200255 u8 bank = offset / 8;
256 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
Linus Walleij4e2678b2016-09-27 16:11:10 -0700257 u8 mask = BIT(offset % 8);
Linus Walleij27ec8a92014-10-02 07:55:41 +0200258 int ret;
259 u8 dir;
260
261 ret = stmpe_reg_read(stmpe, dir_reg);
262 if (ret < 0)
263 return;
264 dir = !!(ret & mask);
265
266 if (dir) {
267 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
268 gpio, label ?: "(none)",
269 val ? "hi" : "lo");
270 } else {
Patrice Chotard287849c2016-08-10 09:39:08 +0200271 u8 edge_det_reg;
272 u8 rise_reg;
273 u8 fall_reg;
274 u8 irqen_reg;
275
276 char *edge_det_values[] = {"edge-inactive",
277 "edge-asserted",
278 "not-supported"};
279 char *rise_values[] = {"no-rising-edge-detection",
280 "rising-edge-detection",
281 "not-supported"};
282 char *fall_values[] = {"no-falling-edge-detection",
283 "falling-edge-detection",
284 "not-supported"};
285 #define NOT_SUPPORTED_IDX 2
286 u8 edge_det = NOT_SUPPORTED_IDX;
287 u8 rise = NOT_SUPPORTED_IDX;
288 u8 fall = NOT_SUPPORTED_IDX;
Linus Walleij27ec8a92014-10-02 07:55:41 +0200289 bool irqen;
290
Patrice Chotard287849c2016-08-10 09:39:08 +0200291 switch (stmpe->partnum) {
292 case STMPE610:
293 case STMPE811:
294 case STMPE1601:
295 case STMPE2401:
296 case STMPE2403:
Patrice Chotard43db2892016-08-10 09:39:12 +0200297 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
Patrice Chotard287849c2016-08-10 09:39:08 +0200298 ret = stmpe_reg_read(stmpe, edge_det_reg);
299 if (ret < 0)
300 return;
301 edge_det = !!(ret & mask);
302
303 case STMPE1801:
Patrice Chotard43db2892016-08-10 09:39:12 +0200304 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
305 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
306
Patrice Chotard287849c2016-08-10 09:39:08 +0200307 ret = stmpe_reg_read(stmpe, rise_reg);
308 if (ret < 0)
309 return;
310 rise = !!(ret & mask);
311 ret = stmpe_reg_read(stmpe, fall_reg);
312 if (ret < 0)
313 return;
314 fall = !!(ret & mask);
315
316 case STMPE801:
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200317 case STMPE1600:
Patrice Chotard43db2892016-08-10 09:39:12 +0200318 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
Patrice Chotard287849c2016-08-10 09:39:08 +0200319 break;
320
321 default:
Linus Walleij27ec8a92014-10-02 07:55:41 +0200322 return;
Patrice Chotard287849c2016-08-10 09:39:08 +0200323 }
324
Linus Walleij27ec8a92014-10-02 07:55:41 +0200325 ret = stmpe_reg_read(stmpe, irqen_reg);
326 if (ret < 0)
327 return;
328 irqen = !!(ret & mask);
329
Patrice Chotard287849c2016-08-10 09:39:08 +0200330 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
Linus Walleij27ec8a92014-10-02 07:55:41 +0200331 gpio, label ?: "(none)",
332 val ? "hi" : "lo",
Patrice Chotard287849c2016-08-10 09:39:08 +0200333 edge_det_values[edge_det],
334 irqen ? "IRQ-enabled" : "IRQ-disabled",
335 rise_values[rise],
336 fall_values[fall]);
Linus Walleij27ec8a92014-10-02 07:55:41 +0200337 }
338}
339
340static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
341{
342 unsigned i;
343 unsigned gpio = gc->base;
344
345 for (i = 0; i < gc->ngpio; i++, gpio++) {
346 stmpe_dbg_show_one(s, gc, i, gpio);
347 seq_printf(s, "\n");
348 }
349}
350
Rabin Vincent03f822f2010-07-02 16:52:09 +0530351static struct irq_chip stmpe_gpio_irq_chip = {
352 .name = "stmpe-gpio",
Lennert Buytenhek2a866f32011-01-12 17:00:17 -0800353 .irq_bus_lock = stmpe_gpio_irq_lock,
354 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
355 .irq_mask = stmpe_gpio_irq_mask,
356 .irq_unmask = stmpe_gpio_irq_unmask,
357 .irq_set_type = stmpe_gpio_irq_set_type,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530358};
359
360static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
361{
362 struct stmpe_gpio *stmpe_gpio = dev;
363 struct stmpe *stmpe = stmpe_gpio->stmpe;
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200364 u8 statmsbreg;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530365 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
366 u8 status[num_banks];
367 int ret;
368 int i;
369
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200370 /*
371 * the stmpe_block_read() call below, imposes to set statmsbreg
372 * with the register located at the lowest address. As STMPE1600
373 * variant is the only one which respect registers address's order
374 * (LSB regs located at lowest address than MSB ones) whereas all
375 * the others have a registers layout with MSB located before the
376 * LSB regs.
377 */
378 if (stmpe->partnum == STMPE1600)
379 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
380 else
381 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
382
Rabin Vincent03f822f2010-07-02 16:52:09 +0530383 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
384 if (ret < 0)
385 return IRQ_NONE;
386
387 for (i = 0; i < num_banks; i++) {
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200388 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
389 num_banks - i - 1;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530390 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
391 unsigned int stat = status[i];
392
393 stat &= enabled;
394 if (!stat)
395 continue;
396
397 while (stat) {
398 int bit = __ffs(stat);
399 int line = bank * 8 + bit;
Linus Walleijfe44e702014-04-15 23:38:56 +0200400 int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
Linus Walleijed05e202013-10-11 19:51:38 +0200401 line);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530402
Linus Walleijed05e202013-10-11 19:51:38 +0200403 handle_nested_irq(child_irq);
Linus Walleij4e2678b2016-09-27 16:11:10 -0700404 stat &= ~BIT(bit);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530405 }
406
Patrice Chotard6936e1f2016-08-10 09:39:09 +0200407 /*
408 * interrupt status register write has no effect on
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200409 * 801/1801/1600, bits are cleared when read.
410 * Edge detect register is not present on 801/1600/1801
Patrice Chotard6936e1f2016-08-10 09:39:09 +0200411 */
Dan Carpenterd1ca19c2016-10-12 09:25:20 +0300412 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
Patrice Chotardc6a05a02016-08-10 09:39:15 +0200413 stmpe->partnum != STMPE1801) {
Patrice Chotard6936e1f2016-08-10 09:39:09 +0200414 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
Patrice Chotard43db2892016-08-10 09:39:12 +0200415 stmpe_reg_write(stmpe,
416 stmpe->regs[STMPE_IDX_GPEDR_LSB + i],
417 status[i]);
Patrice Chotard6936e1f2016-08-10 09:39:09 +0200418 }
Rabin Vincent03f822f2010-07-02 16:52:09 +0530419 }
420
421 return IRQ_HANDLED;
422}
423
Bill Pemberton38363092012-11-19 13:22:34 -0500424static int stmpe_gpio_probe(struct platform_device *pdev)
Rabin Vincent03f822f2010-07-02 16:52:09 +0530425{
426 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
Vipul Kumar Samar86605cf2012-11-26 17:06:51 +0530427 struct device_node *np = pdev->dev.of_node;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530428 struct stmpe_gpio *stmpe_gpio;
429 int ret;
Chris Blair38040c82012-01-26 22:17:15 +0100430 int irq = 0;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530431
Rabin Vincent03f822f2010-07-02 16:52:09 +0530432 irq = platform_get_irq(pdev, 0);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530433
434 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
435 if (!stmpe_gpio)
436 return -ENOMEM;
437
438 mutex_init(&stmpe_gpio->irq_lock);
439
440 stmpe_gpio->dev = &pdev->dev;
441 stmpe_gpio->stmpe = stmpe;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530442 stmpe_gpio->chip = template_chip;
443 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
Linus Walleij58383c72015-11-04 09:56:26 +0100444 stmpe_gpio->chip.parent = &pdev->dev;
Gabriel Fernandez9afd9b72013-03-18 11:45:05 +0100445 stmpe_gpio->chip.of_node = np;
Linus Walleij9e9dc7d2014-05-08 23:16:34 +0200446 stmpe_gpio->chip.base = -1;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530447
Linus Walleij27ec8a92014-10-02 07:55:41 +0200448 if (IS_ENABLED(CONFIG_DEBUG_FS))
449 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
450
Linus Walleij1dfb4a02015-01-13 08:00:29 +0100451 of_property_read_u32(np, "st,norequest-mask",
452 &stmpe_gpio->norequest_mask);
Linus Walleij96b2cca2016-09-27 15:59:12 -0700453 if (stmpe_gpio->norequest_mask)
454 stmpe_gpio->chip.irq_need_valid_mask = true;
Vipul Kumar Samar86605cf2012-11-26 17:06:51 +0530455
Linus Walleij9e9dc7d2014-05-08 23:16:34 +0200456 if (irq < 0)
Chris Blair38040c82012-01-26 22:17:15 +0100457 dev_info(&pdev->dev,
Linus Walleijfe44e702014-04-15 23:38:56 +0200458 "device configured in no-irq mode: "
Chris Blair38040c82012-01-26 22:17:15 +0100459 "irqs are not available\n");
Rabin Vincent03f822f2010-07-02 16:52:09 +0530460
461 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
462 if (ret)
Vasiliy Kulikov02bf0742010-09-12 22:57:19 +0400463 goto out_free;
Rabin Vincent03f822f2010-07-02 16:52:09 +0530464
Linus Walleijb03c04a2015-12-07 14:32:13 +0100465 ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
Linus Walleij3f97d5fc2014-09-26 14:19:52 +0200466 if (ret) {
467 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
468 goto out_disable;
469 }
470
Linus Walleijfe44e702014-04-15 23:38:56 +0200471 if (irq > 0) {
472 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
473 stmpe_gpio_irq, IRQF_ONESHOT,
474 "stmpe-gpio", stmpe_gpio);
Chris Blair38040c82012-01-26 22:17:15 +0100475 if (ret) {
476 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
Lee Jonesfc13d5a2012-12-10 10:07:54 +0000477 goto out_disable;
Chris Blair38040c82012-01-26 22:17:15 +0100478 }
Linus Walleij96b2cca2016-09-27 15:59:12 -0700479 if (stmpe_gpio->norequest_mask) {
480 int i;
481
482 /* Forbid unused lines to be mapped as IRQs */
483 for (i = 0; i < sizeof(u32); i++)
484 if (stmpe_gpio->norequest_mask & BIT(i))
485 clear_bit(i, stmpe_gpio->chip.irq_valid_mask);
486 }
Linus Walleijfe44e702014-04-15 23:38:56 +0200487 ret = gpiochip_irqchip_add(&stmpe_gpio->chip,
488 &stmpe_gpio_irq_chip,
489 0,
490 handle_simple_irq,
491 IRQ_TYPE_NONE);
492 if (ret) {
493 dev_err(&pdev->dev,
494 "could not connect irqchip to gpiochip\n");
Linus Walleij3f97d5fc2014-09-26 14:19:52 +0200495 goto out_disable;
Linus Walleijfe44e702014-04-15 23:38:56 +0200496 }
Rabin Vincent03f822f2010-07-02 16:52:09 +0530497
Linus Walleij3f97d5fc2014-09-26 14:19:52 +0200498 gpiochip_set_chained_irqchip(&stmpe_gpio->chip,
499 &stmpe_gpio_irq_chip,
500 irq,
501 NULL);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530502 }
503
Rabin Vincent03f822f2010-07-02 16:52:09 +0530504 platform_set_drvdata(pdev, stmpe_gpio);
505
506 return 0;
507
Vasiliy Kulikov02bf0742010-09-12 22:57:19 +0400508out_disable:
509 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
Linus Walleij3f97d5fc2014-09-26 14:19:52 +0200510 gpiochip_remove(&stmpe_gpio->chip);
Rabin Vincent03f822f2010-07-02 16:52:09 +0530511out_free:
512 kfree(stmpe_gpio);
513 return ret;
514}
515
Rabin Vincent03f822f2010-07-02 16:52:09 +0530516static struct platform_driver stmpe_gpio_driver = {
Paul Gortmaker3b52bb92016-05-09 19:59:56 -0400517 .driver = {
518 .suppress_bind_attrs = true,
519 .name = "stmpe-gpio",
Paul Gortmaker3b52bb92016-05-09 19:59:56 -0400520 },
Rabin Vincent03f822f2010-07-02 16:52:09 +0530521 .probe = stmpe_gpio_probe,
Rabin Vincent03f822f2010-07-02 16:52:09 +0530522};
523
524static int __init stmpe_gpio_init(void)
525{
526 return platform_driver_register(&stmpe_gpio_driver);
527}
528subsys_initcall(stmpe_gpio_init);