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gerrit-public.fairphone.software / kernel / msm-4.9 / d1d588c181e35d98113f91c8004f77cdac2bf9d5 / . / sound / soc / tegra / tegra20_das.h
blob: be217f3d3a756cb3b89dc32c8b0d70ee130ea613 [file] [log] [blame]
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]1/*
Stephen Warrenef280d32012-04-05 15:54:53 -0600[diff] [blame]2 * tegra20_das.h - Definitions for Tegra20 DAS driver
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]3 *
4 * Author: Stephen Warren <swarren@nvidia.com>
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]5 * Copyright (C) 2010,2012 - NVIDIA, Inc.
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]23#ifndef __TEGRA20_DAS_H__
24#define __TEGRA20_DAS_H__
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]25
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]26/* Register TEGRA20_DAS_DAP_CTRL_SEL */
27#define TEGRA20_DAS_DAP_CTRL_SEL 0x00
28#define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
29#define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
30#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
31#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
32#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
33#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
34#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
35#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
36#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
37#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]38
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]39/* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
40#define TEGRA20_DAS_DAP_SEL_DAC1 0
41#define TEGRA20_DAS_DAP_SEL_DAC2 1
42#define TEGRA20_DAS_DAP_SEL_DAC3 2
43#define TEGRA20_DAS_DAP_SEL_DAP1 16
44#define TEGRA20_DAS_DAP_SEL_DAP2 17
45#define TEGRA20_DAS_DAP_SEL_DAP3 18
46#define TEGRA20_DAS_DAP_SEL_DAP4 19
47#define TEGRA20_DAS_DAP_SEL_DAP5 20
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]48
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]49/* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
50#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
51#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
52#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
53#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
54#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
55#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
56#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
57#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
58#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]59
60/*
61 * Values for:
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]62 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
63 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
64 * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]65 */
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]66#define TEGRA20_DAS_DAC_SEL_DAP1 0
67#define TEGRA20_DAS_DAC_SEL_DAP2 1
68#define TEGRA20_DAS_DAC_SEL_DAP3 2
69#define TEGRA20_DAS_DAC_SEL_DAP4 3
70#define TEGRA20_DAS_DAC_SEL_DAP5 4
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]71
72/*
73 * Names/IDs of the DACs/DAPs.
74 */
75
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]76#define TEGRA20_DAS_DAP_ID_1 0
77#define TEGRA20_DAS_DAP_ID_2 1
78#define TEGRA20_DAS_DAP_ID_3 2
79#define TEGRA20_DAS_DAP_ID_4 3
80#define TEGRA20_DAS_DAP_ID_5 4
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]81
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]82#define TEGRA20_DAS_DAC_ID_1 0
83#define TEGRA20_DAS_DAC_ID_2 1
84#define TEGRA20_DAS_DAC_ID_3 2
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]85
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]86struct tegra20_das {
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]87 struct device *dev;
Stephen Warren7203a622012-04-13 12:14:08 -0600[diff] [blame]88 struct regmap *regmap;
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]89};
90
91/*
92 * Terminology:
93 * DAS: Digital audio switch (HW module controlled by this driver)
94 * DAP: Digital audio port (port/pins on Tegra device)
95 * DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
Stephen Warren7deb2b42012-03-30 17:07:21 -0600[diff] [blame]96 *
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]97 * The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
98 * DAC, or another DAP. When DAPs are connected, one must be the master and
99 * one the slave. Each DAC allows selection of a specific DAP for input, to
100 * cater for the case where N DAPs are connected to 1 DAC for broadcast
101 * output.
102 *
103 * This driver is dumb; no attempt is made to ensure that a valid routing
104 * configuration is programmed.
105 */
106
107/*
108 * Connect a DAP to to a DAC
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]109 * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
110 * dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC*
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]111 */
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]112extern int tegra20_das_connect_dap_to_dac(int dap_id, int dac_sel);
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]113
114/*
115 * Connect a DAP to to another DAP
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]116 * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
117 * other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP*
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]118 * master: Is this DAP the master (1) or slave (0)
119 * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0)
120 * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0)
121 */
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]122extern int tegra20_das_connect_dap_to_dap(int dap_id, int other_dap_sel,
123 int master, int sdata1rx,
124 int sdata2rx);
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]125
126/*
127 * Connect a DAC's input to a DAP
128 * (DAC outputs are selected by the DAP)
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]129 * dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_*
130 * dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP*
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]131 */
Stephen Warren896637a2012-04-06 10:30:52 -0600[diff] [blame]132extern int tegra20_das_connect_dac_to_dap(int dac_id, int dap_sel);
Stephen Warrenf0d8af42011-01-07 22:36:12 -0700[diff] [blame]133
134#endif