blob: 32cda77b31cd2c5625bf8c10eeabb88814ede008 [file] [log] [blame]
Kumar Galaccf06992006-05-20 15:00:15 -07001/*
2 * MPC83xx SPI controller driver.
3 *
4 * Maintainer: Kumar Gala
5 *
6 * Copyright (C) 2006 Polycom, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/completion.h>
18#include <linux/interrupt.h>
19#include <linux/delay.h>
20#include <linux/irq.h>
21#include <linux/device.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/spi_bitbang.h>
24#include <linux/platform_device.h>
25#include <linux/fsl_devices.h>
26
27#include <asm/irq.h>
28#include <asm/io.h>
29
30/* SPI Controller registers */
31struct mpc83xx_spi_reg {
32 u8 res1[0x20];
33 __be32 mode;
34 __be32 event;
35 __be32 mask;
36 __be32 command;
37 __be32 transmit;
38 __be32 receive;
39};
40
41/* SPI Controller mode register definitions */
Anton Vorontsov2a485d72007-07-31 00:38:45 -070042#define SPMODE_LOOP (1 << 30)
Kumar Galaccf06992006-05-20 15:00:15 -070043#define SPMODE_CI_INACTIVEHIGH (1 << 29)
44#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
45#define SPMODE_DIV16 (1 << 27)
46#define SPMODE_REV (1 << 26)
47#define SPMODE_MS (1 << 25)
48#define SPMODE_ENABLE (1 << 24)
49#define SPMODE_LEN(x) ((x) << 20)
50#define SPMODE_PM(x) ((x) << 16)
Joakim Tjernlundf29ba282007-07-17 04:04:12 -070051#define SPMODE_OP (1 << 14)
Kumar Galaccf06992006-05-20 15:00:15 -070052
53/*
54 * Default for SPI Mode:
55 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
56 */
57#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
58 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
59
60/* SPIE register values */
61#define SPIE_NE 0x00000200 /* Not empty */
62#define SPIE_NF 0x00000100 /* Not full */
63
64/* SPIM register values */
65#define SPIM_NE 0x00000200 /* Not empty */
66#define SPIM_NF 0x00000100 /* Not full */
67
68/* SPI Controller driver's private data. */
69struct mpc83xx_spi {
70 /* bitbang has to be first */
71 struct spi_bitbang bitbang;
72 struct completion done;
73
74 struct mpc83xx_spi_reg __iomem *base;
75
76 /* rx & tx bufs from the spi_transfer */
77 const void *tx;
78 void *rx;
79
80 /* functions to deal with different sized buffers */
81 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
82 u32(*get_tx) (struct mpc83xx_spi *);
83
84 unsigned int count;
85 u32 irq;
86
87 unsigned nsecs; /* (clock cycle time)/2 */
88
Anton Vorontsove24a4d12007-08-10 13:01:01 -070089 u32 spibrg; /* SPIBRG input clock */
Joakim Tjernlundf29ba282007-07-17 04:04:12 -070090 u32 rx_shift; /* RX data reg shift when in qe mode */
91 u32 tx_shift; /* TX data reg shift when in qe mode */
92
93 bool qe_mode;
94
Kumar Galaccf06992006-05-20 15:00:15 -070095 void (*activate_cs) (u8 cs, u8 polarity);
96 void (*deactivate_cs) (u8 cs, u8 polarity);
97};
98
99static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
100{
101 out_be32(reg, val);
102}
103
104static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
105{
106 return in_be32(reg);
107}
108
109#define MPC83XX_SPI_RX_BUF(type) \
110void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
111{ \
112 type * rx = mpc83xx_spi->rx; \
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700113 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
Kumar Galaccf06992006-05-20 15:00:15 -0700114 mpc83xx_spi->rx = rx; \
115}
116
117#define MPC83XX_SPI_TX_BUF(type) \
118u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
119{ \
120 u32 data; \
121 const type * tx = mpc83xx_spi->tx; \
David Brownell4b1badf2006-12-29 16:48:39 -0800122 if (!tx) \
123 return 0; \
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700124 data = *tx++ << mpc83xx_spi->tx_shift; \
Kumar Galaccf06992006-05-20 15:00:15 -0700125 mpc83xx_spi->tx = tx; \
126 return data; \
127}
128
129MPC83XX_SPI_RX_BUF(u8)
130MPC83XX_SPI_RX_BUF(u16)
131MPC83XX_SPI_RX_BUF(u32)
132MPC83XX_SPI_TX_BUF(u8)
133MPC83XX_SPI_TX_BUF(u16)
134MPC83XX_SPI_TX_BUF(u32)
135
136static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
137{
138 struct mpc83xx_spi *mpc83xx_spi;
139 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
140
141 mpc83xx_spi = spi_master_get_devdata(spi->master);
142
143 if (value == BITBANG_CS_INACTIVE) {
144 if (mpc83xx_spi->deactivate_cs)
145 mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
146 }
147
148 if (value == BITBANG_CS_ACTIVE) {
149 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
150 u32 len = spi->bits_per_word;
Anton Vorontsova44648b2007-08-10 13:01:02 -0700151 u8 pm;
152
Kumar Galaccf06992006-05-20 15:00:15 -0700153 if (len == 32)
154 len = 0;
155 else
156 len = len - 1;
157
158 /* mask out bits we are going to set */
Anton Vorontsov32421da2007-07-31 00:38:41 -0700159 regval &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
160 | SPMODE_LEN(0xF) | SPMODE_DIV16
Anton Vorontsov2a485d72007-07-31 00:38:45 -0700161 | SPMODE_PM(0xF) | SPMODE_REV | SPMODE_LOOP);
Kumar Galaccf06992006-05-20 15:00:15 -0700162
163 if (spi->mode & SPI_CPHA)
164 regval |= SPMODE_CP_BEGIN_EDGECLK;
165 if (spi->mode & SPI_CPOL)
166 regval |= SPMODE_CI_INACTIVEHIGH;
Anton Vorontsov32421da2007-07-31 00:38:41 -0700167 if (!(spi->mode & SPI_LSB_FIRST))
168 regval |= SPMODE_REV;
Anton Vorontsov2a485d72007-07-31 00:38:45 -0700169 if (spi->mode & SPI_LOOP)
170 regval |= SPMODE_LOOP;
Kumar Galaccf06992006-05-20 15:00:15 -0700171
172 regval |= SPMODE_LEN(len);
173
Anton Vorontsove24a4d12007-08-10 13:01:01 -0700174 if ((mpc83xx_spi->spibrg / spi->max_speed_hz) >= 64) {
Anton Vorontsova44648b2007-08-10 13:01:02 -0700175 pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 64) - 1;
Clifford Wolf698ca472007-07-17 04:04:06 -0700176 if (pm > 0x0f) {
Anton Vorontsove24a4d12007-08-10 13:01:01 -0700177 dev_err(&spi->dev, "Requested speed is too "
178 "low: %d Hz. Will use %d Hz instead.\n",
179 spi->max_speed_hz,
180 mpc83xx_spi->spibrg / 1024);
Clifford Wolf698ca472007-07-17 04:04:06 -0700181 pm = 0x0f;
182 }
Kumar Galaccf06992006-05-20 15:00:15 -0700183 regval |= SPMODE_PM(pm) | SPMODE_DIV16;
184 } else {
Anton Vorontsova44648b2007-08-10 13:01:02 -0700185 pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 4);
186 if (pm)
187 pm--;
Kumar Galaccf06992006-05-20 15:00:15 -0700188 regval |= SPMODE_PM(pm);
189 }
190
Anton Vorontsov49bb2302007-07-31 00:38:40 -0700191 /* Turn off SPI unit prior changing mode */
192 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
Kumar Galaccf06992006-05-20 15:00:15 -0700193 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
194 if (mpc83xx_spi->activate_cs)
195 mpc83xx_spi->activate_cs(spi->chip_select, pol);
196 }
197}
198
199static
200int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
201{
202 struct mpc83xx_spi *mpc83xx_spi;
203 u32 regval;
204 u8 bits_per_word;
205 u32 hz;
206
207 mpc83xx_spi = spi_master_get_devdata(spi->master);
208
209 if (t) {
210 bits_per_word = t->bits_per_word;
211 hz = t->speed_hz;
212 } else {
213 bits_per_word = 0;
214 hz = 0;
215 }
216
217 /* spi_transfer level calls that work per-word */
218 if (!bits_per_word)
219 bits_per_word = spi->bits_per_word;
220
221 /* Make sure its a bit width we support [4..16, 32] */
222 if ((bits_per_word < 4)
223 || ((bits_per_word > 16) && (bits_per_word != 32)))
224 return -EINVAL;
225
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700226 mpc83xx_spi->rx_shift = 0;
227 mpc83xx_spi->tx_shift = 0;
Kumar Galaccf06992006-05-20 15:00:15 -0700228 if (bits_per_word <= 8) {
229 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
230 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700231 if (mpc83xx_spi->qe_mode) {
232 mpc83xx_spi->rx_shift = 16;
233 mpc83xx_spi->tx_shift = 24;
234 }
Kumar Galaccf06992006-05-20 15:00:15 -0700235 } else if (bits_per_word <= 16) {
236 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
237 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700238 if (mpc83xx_spi->qe_mode) {
239 mpc83xx_spi->rx_shift = 16;
240 mpc83xx_spi->tx_shift = 16;
241 }
Kumar Galaccf06992006-05-20 15:00:15 -0700242 } else if (bits_per_word <= 32) {
243 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
244 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
245 } else
246 return -EINVAL;
247
Anton Vorontsov35cc0b92007-07-31 00:38:42 -0700248 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
249 mpc83xx_spi->tx_shift = 0;
250 if (bits_per_word <= 8)
251 mpc83xx_spi->rx_shift = 8;
252 else
253 mpc83xx_spi->rx_shift = 0;
254 }
255
Kumar Galaccf06992006-05-20 15:00:15 -0700256 /* nsecs = (clock period)/2 */
257 if (!hz)
258 hz = spi->max_speed_hz;
259 mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
260 if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
261 return -EINVAL;
262
263 if (bits_per_word == 32)
264 bits_per_word = 0;
265 else
266 bits_per_word = bits_per_word - 1;
267
268 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
269
Anton Vorontsov32421da2007-07-31 00:38:41 -0700270 /* mask out bits we are going to set */
271 regval &= ~(SPMODE_LEN(0xF) | SPMODE_REV);
Kumar Galaccf06992006-05-20 15:00:15 -0700272 regval |= SPMODE_LEN(bits_per_word);
Anton Vorontsov32421da2007-07-31 00:38:41 -0700273 if (!(spi->mode & SPI_LSB_FIRST))
274 regval |= SPMODE_REV;
Kumar Galaccf06992006-05-20 15:00:15 -0700275
Anton Vorontsov49bb2302007-07-31 00:38:40 -0700276 /* Turn off SPI unit prior changing mode */
277 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
Kumar Galaccf06992006-05-20 15:00:15 -0700278 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
279
280 return 0;
281}
282
David Brownelldccd5732007-07-17 04:04:02 -0700283/* the spi->mode bits understood by this driver: */
Anton Vorontsov2a485d72007-07-31 00:38:45 -0700284#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
285 | SPI_LSB_FIRST | SPI_LOOP)
David Brownelldccd5732007-07-17 04:04:02 -0700286
Kumar Galaccf06992006-05-20 15:00:15 -0700287static int mpc83xx_spi_setup(struct spi_device *spi)
288{
289 struct spi_bitbang *bitbang;
290 struct mpc83xx_spi *mpc83xx_spi;
291 int retval;
292
David Brownelldccd5732007-07-17 04:04:02 -0700293 if (spi->mode & ~MODEBITS) {
294 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
295 spi->mode & ~MODEBITS);
296 return -EINVAL;
297 }
298
Kumar Galaccf06992006-05-20 15:00:15 -0700299 if (!spi->max_speed_hz)
300 return -EINVAL;
301
302 bitbang = spi_master_get_devdata(spi->master);
303 mpc83xx_spi = spi_master_get_devdata(spi->master);
304
305 if (!spi->bits_per_word)
306 spi->bits_per_word = 8;
307
308 retval = mpc83xx_spi_setup_transfer(spi, NULL);
309 if (retval < 0)
310 return retval;
311
312 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
313 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
314 spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
315
316 /* NOTE we _need_ to call chipselect() early, ideally with adapter
317 * setup, unless the hardware defaults cooperate to avoid confusion
318 * between normal (active low) and inverted chipselects.
319 */
320
321 /* deselect chip (low or high) */
322 spin_lock(&bitbang->lock);
323 if (!bitbang->busy) {
324 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
325 ndelay(mpc83xx_spi->nsecs);
326 }
327 spin_unlock(&bitbang->lock);
328
329 return 0;
330}
331
332static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
333{
334 struct mpc83xx_spi *mpc83xx_spi;
335 u32 word;
336
337 mpc83xx_spi = spi_master_get_devdata(spi->master);
338
339 mpc83xx_spi->tx = t->tx_buf;
340 mpc83xx_spi->rx = t->rx_buf;
341 mpc83xx_spi->count = t->len;
342 INIT_COMPLETION(mpc83xx_spi->done);
343
344 /* enable rx ints */
345 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
346
347 /* transmit word */
348 word = mpc83xx_spi->get_tx(mpc83xx_spi);
349 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
350
351 wait_for_completion(&mpc83xx_spi->done);
352
353 /* disable rx ints */
354 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
355
356 return t->len - mpc83xx_spi->count;
357}
358
David Howells7d12e782006-10-05 14:55:46 +0100359irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
Kumar Galaccf06992006-05-20 15:00:15 -0700360{
361 struct mpc83xx_spi *mpc83xx_spi = context_data;
362 u32 event;
363 irqreturn_t ret = IRQ_NONE;
364
365 /* Get interrupt events(tx/rx) */
366 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
367
368 /* We need handle RX first */
369 if (event & SPIE_NE) {
370 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
371
372 if (mpc83xx_spi->rx)
373 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
374
375 ret = IRQ_HANDLED;
376 }
377
378 if ((event & SPIE_NF) == 0)
379 /* spin until TX is done */
380 while (((event =
381 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
382 SPIE_NF) == 0)
383 cpu_relax();
384
385 mpc83xx_spi->count -= 1;
386 if (mpc83xx_spi->count) {
Jan Andersson65e213c2007-09-11 15:23:30 -0700387 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
388 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
Kumar Galaccf06992006-05-20 15:00:15 -0700389 } else {
390 complete(&mpc83xx_spi->done);
391 }
392
393 /* Clear the events */
394 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
395
396 return ret;
397}
398
399static int __init mpc83xx_spi_probe(struct platform_device *dev)
400{
401 struct spi_master *master;
402 struct mpc83xx_spi *mpc83xx_spi;
403 struct fsl_spi_platform_data *pdata;
404 struct resource *r;
405 u32 regval;
406 int ret = 0;
407
408 /* Get resources(memory, IRQ) associated with the device */
409 master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
410
411 if (master == NULL) {
412 ret = -ENOMEM;
413 goto err;
414 }
415
416 platform_set_drvdata(dev, master);
417 pdata = dev->dev.platform_data;
418
419 if (pdata == NULL) {
420 ret = -ENODEV;
421 goto free_master;
422 }
423
424 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
425 if (r == NULL) {
426 ret = -ENODEV;
427 goto free_master;
428 }
Kumar Galaccf06992006-05-20 15:00:15 -0700429 mpc83xx_spi = spi_master_get_devdata(master);
430 mpc83xx_spi->bitbang.master = spi_master_get(master);
431 mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
432 mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
433 mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
Kumar Galaccf06992006-05-20 15:00:15 -0700434 mpc83xx_spi->activate_cs = pdata->activate_cs;
435 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700436 mpc83xx_spi->qe_mode = pdata->qe_mode;
Kumar Galaccf06992006-05-20 15:00:15 -0700437 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
438 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
439
Anton Vorontsove24a4d12007-08-10 13:01:01 -0700440 if (mpc83xx_spi->qe_mode)
441 mpc83xx_spi->spibrg = pdata->sysclk / 2;
442 else
443 mpc83xx_spi->spibrg = pdata->sysclk;
444
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700445 mpc83xx_spi->rx_shift = 0;
446 mpc83xx_spi->tx_shift = 0;
447 if (mpc83xx_spi->qe_mode) {
448 mpc83xx_spi->rx_shift = 16;
449 mpc83xx_spi->tx_shift = 24;
450 }
451
Kumar Galaccf06992006-05-20 15:00:15 -0700452 mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
453 init_completion(&mpc83xx_spi->done);
454
455 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
456 if (mpc83xx_spi->base == NULL) {
457 ret = -ENOMEM;
458 goto put_master;
459 }
460
461 mpc83xx_spi->irq = platform_get_irq(dev, 0);
462
463 if (mpc83xx_spi->irq < 0) {
464 ret = -ENXIO;
465 goto unmap_io;
466 }
467
468 /* Register for SPI Interrupt */
469 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
470 0, "mpc83xx_spi", mpc83xx_spi);
471
472 if (ret != 0)
473 goto unmap_io;
474
475 master->bus_num = pdata->bus_num;
476 master->num_chipselect = pdata->max_chipselect;
477
478 /* SPI controller initializations */
479 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
480 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
481 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
482 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
483
484 /* Enable SPI interface */
485 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
Joakim Tjernlundf29ba282007-07-17 04:04:12 -0700486 if (pdata->qe_mode)
487 regval |= SPMODE_OP;
488
Kumar Galaccf06992006-05-20 15:00:15 -0700489 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
490
491 ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
492
493 if (ret != 0)
494 goto free_irq;
495
496 printk(KERN_INFO
497 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
498 dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
499
500 return ret;
501
502free_irq:
503 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
504unmap_io:
505 iounmap(mpc83xx_spi->base);
506put_master:
507 spi_master_put(master);
508free_master:
509 kfree(master);
510err:
511 return ret;
512}
513
514static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
515{
516 struct mpc83xx_spi *mpc83xx_spi;
517 struct spi_master *master;
518
519 master = platform_get_drvdata(dev);
520 mpc83xx_spi = spi_master_get_devdata(master);
521
522 spi_bitbang_stop(&mpc83xx_spi->bitbang);
523 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
524 iounmap(mpc83xx_spi->base);
525 spi_master_put(mpc83xx_spi->bitbang.master);
526
527 return 0;
528}
529
David Brownellfc3ba952007-08-30 23:56:24 -0700530MODULE_ALIAS("mpc83xx_spi"); /* for platform bus hotplug */
Kumar Galaccf06992006-05-20 15:00:15 -0700531static struct platform_driver mpc83xx_spi_driver = {
532 .probe = mpc83xx_spi_probe,
533 .remove = __devexit_p(mpc83xx_spi_remove),
534 .driver = {
535 .name = "mpc83xx_spi",
536 },
537};
538
539static int __init mpc83xx_spi_init(void)
540{
541 return platform_driver_register(&mpc83xx_spi_driver);
542}
543
544static void __exit mpc83xx_spi_exit(void)
545{
546 platform_driver_unregister(&mpc83xx_spi_driver);
547}
548
549module_init(mpc83xx_spi_init);
550module_exit(mpc83xx_spi_exit);
551
552MODULE_AUTHOR("Kumar Gala");
553MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
554MODULE_LICENSE("GPL");