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Vineet Guptacfdbc2e2013-01-18 15:12:20 +05301#
2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License version 2 as
6# published by the Free Software Foundation.
7#
8
9config ARC
10 def_bool y
Vineet Guptaf06d19e2013-11-15 12:08:05 +053011 select BUILDTIME_EXTABLE_SORT
Vineet Guptad7f8a082014-09-10 11:10:54 +053012 select COMMON_CLK
Vineet Gupta4adeefe2013-01-18 15:12:18 +053013 select CLONE_BACKWARDS
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053014 # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
15 select DEVTMPFS if !INITRAMFS_SOURCE=""
16 select GENERIC_ATOMIC64
17 select GENERIC_CLOCKEVENTS
18 select GENERIC_FIND_FIRST_BIT
19 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
20 select GENERIC_IRQ_SHOW
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053021 select GENERIC_PENDING_IRQ if SMP
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053022 select GENERIC_SMP_IDLE_THREAD
Mischa Jonkerf46121b2013-01-18 15:12:24 +053023 select HAVE_ARCH_KGDB
Vineet Gupta547f1122013-01-18 15:12:22 +053024 select HAVE_ARCH_TRACEHOOK
Gilad Ben-Yossef43689022013-01-22 16:48:45 +053025 select HAVE_IOREMAP_PROT
Vineet Gupta4d86dfb2013-01-22 17:03:59 +053026 select HAVE_KPROBES
27 select HAVE_KRETPROBES
Vineet Guptac121c502013-01-18 15:12:20 +053028 select HAVE_MEMBLOCK
Vineet Gupta854a0d92013-01-22 17:03:19 +053029 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
Vineet Gupta769bc1f2013-01-22 17:02:38 +053030 select HAVE_OPROFILE
Vineet Gupta9c575642013-01-18 15:12:24 +053031 select HAVE_PERF_EVENTS
Vineet Gupta999159a2013-01-22 17:00:52 +053032 select IRQ_DOMAIN
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053033 select MODULES_USE_ELF_RELA
Vineet Guptac121c502013-01-18 15:12:20 +053034 select NO_BOOTMEM
Vineet Gupta999159a2013-01-22 17:00:52 +053035 select OF
36 select OF_EARLY_FLATTREE
Vineet Gupta9c575642013-01-18 15:12:24 +053037 select PERF_USE_VMALLOC
Dave Hansend1a1dc02013-07-01 13:04:42 -070038 select HAVE_DEBUG_STACKOVERFLOW
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053039
Vineet Gupta0dafafc2013-09-06 14:18:17 +053040config TRACE_IRQFLAGS_SUPPORT
41 def_bool y
42
43config LOCKDEP_SUPPORT
44 def_bool y
45
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053046config SCHED_OMIT_FRAME_POINTER
47 def_bool y
48
49config GENERIC_CSUM
50 def_bool y
51
52config RWSEM_GENERIC_SPINLOCK
53 def_bool y
54
55config ARCH_FLATMEM_ENABLE
56 def_bool y
57
58config MMU
59 def_bool y
60
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070061config NO_IOPORT_MAP
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053062 def_bool y
63
64config GENERIC_CALIBRATE_DELAY
65 def_bool y
66
67config GENERIC_HWEIGHT
68 def_bool y
69
Vineet Gupta44c8bb92013-01-18 15:12:23 +053070config STACKTRACE_SUPPORT
71 def_bool y
72 select STACKTRACE
73
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053074config HAVE_LATENCYTOP_SUPPORT
75 def_bool y
76
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053077source "init/Kconfig"
78source "kernel/Kconfig.freezer"
79
80menu "ARC Architecture Configuration"
81
Vineet Gupta93ad7002013-01-22 16:51:50 +053082menu "ARC Platform/SoC/Board"
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053083
Vineet Guptafd155792015-02-20 19:12:18 +053084source "arch/arc/plat-sim/Kconfig"
Christian Ruppert072eb692013-04-12 08:40:59 +020085source "arch/arc/plat-tb10x/Kconfig"
Alexey Brodkin556cc1c2014-01-27 14:51:34 +010086source "arch/arc/plat-axs10x/Kconfig"
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053087#New platform adds here
Vineet Gupta93ad7002013-01-22 16:51:50 +053088
Vineet Gupta53d98952013-01-18 15:12:25 +053089endmenu
Vineet Guptacfdbc2e2013-01-18 15:12:20 +053090
Vineet Gupta1f6ccff2013-05-13 18:30:41 +053091choice
92 prompt "ARC Instruction Set"
93 default ISA_ARCOMPACT
94
95config ISA_ARCOMPACT
96 bool "ARCompact ISA"
97 help
98 The original ARC ISA of ARC600/700 cores
99
100### For bisectability, disable ARCv2 support until we have all the bits in place
101#config ISA_ARCV2
102# bool "ARC ISA v2"
103# help
104# ISA for the Next Generation ARC-HS cores
105
106endchoice
107
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530108menu "ARC CPU Configuration"
109
110choice
111 prompt "ARC Core"
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530112 default ARC_CPU_770 if ISA_ARCOMPACT
113 default ARC_CPU_HS if ISA_ARCV2
114
115if ISA_ARCOMPACT
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530116
117config ARC_CPU_750D
118 bool "ARC750D"
119 help
120 Support for ARC750 core
121
122config ARC_CPU_770
123 bool "ARC770"
Vineet Gupta742f8af2013-11-07 14:47:16 +0530124 select ARC_HAS_SWAPE
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530125 help
126 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
127 This core has a bunch of cool new features:
128 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
129 Shared Address Spaces (for sharing TLB entires in MMU)
130 -Caches: New Prog Model, Region Flush
131 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
132
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530133endif #ISA_ARCOMPACT
134
135config ARC_CPU_HS
136 bool "ARC-HS"
137 depends on ISA_ARCV2
138 help
139 Support for ARC HS38x Cores based on ARCv2 ISA
140 The notable features are:
141 - SMP configurations of upto 4 core with coherency
142 - Optional L2 Cache and IO-Coherency
143 - Revised Interrupt Architecture (multiple priorites, reg banks,
144 auto stack switch, auto regfile save/restore)
145 - MMUv4 (PIPT dcache, Huge Pages)
146 - Instructions for
147 * 64bit load/store: LDD, STD
148 * Hardware assisted divide/remainder: DIV, REM
149 * Function prologue/epilogue: ENTER_S, LEAVE_S
150 * IRQ enable/disable: CLRI, SETI
151 * pop count: FFS, FLS
152 * SETcc, BMSKN, XBFU...
153
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530154endchoice
155
156config CPU_BIG_ENDIAN
157 bool "Enable Big Endian Mode"
158 default n
159 help
160 Build kernel for Big Endian Mode of ARC CPU
161
Vineet Gupta41195d22013-01-18 15:12:23 +0530162config SMP
163 bool "Symmetric Multi-Processing (Incomplete)"
164 default n
Vineet Gupta41195d22013-01-18 15:12:23 +0530165 help
166 This enables support for systems with more than one CPU. If you have
Robert Graffham4a474152014-01-23 15:55:29 -0800167 a system with only one CPU, say N. If you have a system with more
168 than one CPU, say Y.
Vineet Gupta41195d22013-01-18 15:12:23 +0530169
170if SMP
171
172config ARC_HAS_COH_CACHES
173 def_bool n
174
Vineet Gupta41195d22013-01-18 15:12:23 +0530175config ARC_HAS_REENTRANT_IRQ_LV2
176 def_bool n
177
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530178endif #SMP
Vineet Gupta41195d22013-01-18 15:12:23 +0530179
180config NR_CPUS
Noam Camus3aa4f802013-06-03 15:19:59 +0300181 int "Maximum number of CPUs (2-4096)"
182 range 2 4096
Vineet Gupta41195d22013-01-18 15:12:23 +0530183 depends on SMP
184 default "2"
185
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530186menuconfig ARC_CACHE
187 bool "Enable Cache Support"
188 default y
Vineet Gupta41195d22013-01-18 15:12:23 +0530189 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
190 depends on !SMP || ARC_HAS_COH_CACHES
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530191
192if ARC_CACHE
193
194config ARC_CACHE_LINE_SHIFT
195 int "Cache Line Length (as power of 2)"
196 range 5 7
197 default "6"
198 help
199 Starting with ARC700 4.9, Cache line length is configurable,
200 This option specifies "N", with Line-len = 2 power N
201 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
202 Linux only supports same line lengths for I and D caches.
203
204config ARC_HAS_ICACHE
205 bool "Use Instruction Cache"
206 default y
207
208config ARC_HAS_DCACHE
209 bool "Use Data Cache"
210 default y
211
212config ARC_CACHE_PAGES
213 bool "Per Page Cache Control"
214 default y
215 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
216 help
217 This can be used to over-ride the global I/D Cache Enable on a
218 per-page basis (but only for pages accessed via MMU such as
219 Kernel Virtual address or User Virtual Address)
220 TLB entries have a per-page Cache Enable Bit.
221 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
222 Global DISABLE + Per Page ENABLE won't work
223
Vineet Gupta4102b532013-05-09 21:54:51 +0530224config ARC_CACHE_VIPT_ALIASING
225 bool "Support VIPT Aliasing D$"
Alexey Brodkin2f9e9962013-06-18 16:40:29 +0400226 depends on ARC_HAS_DCACHE
Vineet Gupta4102b532013-05-09 21:54:51 +0530227 default n
228
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530229endif #ARC_CACHE
230
Vineet Gupta8b5850f2013-01-18 15:12:25 +0530231config ARC_HAS_ICCM
232 bool "Use ICCM"
233 help
234 Single Cycle RAMS to store Fast Path Code
235 default n
236
237config ARC_ICCM_SZ
238 int "ICCM Size in KB"
239 default "64"
240 depends on ARC_HAS_ICCM
241
242config ARC_HAS_DCCM
243 bool "Use DCCM"
244 help
245 Single Cycle RAMS to store Fast Path Data
246 default n
247
248config ARC_DCCM_SZ
249 int "DCCM Size in KB"
250 default "64"
251 depends on ARC_HAS_DCCM
252
253config ARC_DCCM_BASE
254 hex "DCCM map address"
255 default "0xA0000000"
256 depends on ARC_HAS_DCCM
257
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530258config ARC_HAS_HW_MPY
259 bool "Use Hardware Multiplier (Normal or Faster XMAC)"
260 default y
261 help
262 Influences how gcc generates code for MPY operations.
263 If enabled, MPYxx insns are generated, provided by Standard/XMAC
264 Multipler. Otherwise software multipy lib is used
265
266choice
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530267 prompt "MMU Version"
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530268 default ARC_MMU_V3 if ARC_CPU_770
269 default ARC_MMU_V2 if ARC_CPU_750D
Vineet Guptad7a512b2015-04-06 17:22:39 +0530270 default ARC_MMU_V4 if ARC_CPU_HS
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530271
272config ARC_MMU_V1
273 bool "MMU v1"
274 help
275 Orig ARC700 MMU
276
277config ARC_MMU_V2
278 bool "MMU v2"
279 help
280 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
281 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
282
283config ARC_MMU_V3
284 bool "MMU v3"
285 depends on ARC_CPU_770
286 help
287 Introduced with ARC700 4.10: New Features
288 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
289 Shared Address Spaces (SASID)
290
Vineet Guptad7a512b2015-04-06 17:22:39 +0530291config ARC_MMU_V4
292 bool "MMU v4"
293 depends on ISA_ARCV2
294
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530295endchoice
296
297
298choice
299 prompt "MMU Page Size"
300 default ARC_PAGE_SIZE_8K
301
302config ARC_PAGE_SIZE_8K
303 bool "8KB"
304 help
305 Choose between 8k vs 16k
306
307config ARC_PAGE_SIZE_16K
308 bool "16KB"
309 depends on ARC_MMU_V3
310
311config ARC_PAGE_SIZE_4K
312 bool "4KB"
313 depends on ARC_MMU_V3
314
315endchoice
316
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530317if ISA_ARCOMPACT
318
Vineet Gupta4788a592013-01-18 15:12:22 +0530319config ARC_COMPACT_IRQ_LEVELS
320 bool "ARCompact IRQ Priorities: High(2)/Low(1)"
321 default n
322 # Timer HAS to be high priority, for any other high priority config
323 select ARC_IRQ3_LV2
Vineet Gupta41195d22013-01-18 15:12:23 +0530324 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
325 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
Vineet Gupta4788a592013-01-18 15:12:22 +0530326
327if ARC_COMPACT_IRQ_LEVELS
328
329config ARC_IRQ3_LV2
330 bool
331
332config ARC_IRQ5_LV2
333 bool
334
335config ARC_IRQ6_LV2
336 bool
337
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530338endif #ARC_COMPACT_IRQ_LEVELS
Vineet Gupta4788a592013-01-18 15:12:22 +0530339
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530340config ARC_FPU_SAVE_RESTORE
341 bool "Enable FPU state persistence across context switch"
342 default n
343 help
344 Double Precision Floating Point unit had dedictaed regs which
345 need to be saved/restored across context-switch.
346 Note that ARC FPU is overly simplistic, unlike say x86, which has
347 hardware pieces to allow software to conditionally save/restore,
348 based on actual usage of FPU by a task. Thus our implemn does
349 this for all tasks in system.
350
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530351endif #ISA_ARCOMPACT
352
Vineet Guptafbf8e132013-03-30 15:07:47 +0530353config ARC_CANT_LLSC
354 def_bool n
355
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530356config ARC_HAS_LLSC
357 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
358 default y
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530359 depends on !ARC_CPU_750D && !ARC_CANT_LLSC
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530360
361config ARC_HAS_SWAPE
362 bool "Insn: SWAPE (endian-swap)"
363 default y
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530364
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530365if ISA_ARCV2
366
367config ARC_HAS_LL64
368 bool "Insn: 64bit LDD/STD"
369 help
370 Enable gcc to generate 64-bit load/store instructions
371 ISA mandates even/odd registers to allow encoding of two
372 dest operands with 2 possible source operands.
373 default y
374
375config ARC_NUMBER_OF_INTERRUPTS
376 int "Number of interrupts"
377 range 8 240
378 default 32
379 help
380 This defines the number of interrupts on the ARCv2HS core.
381 It affects the size of vector table.
382 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
383 in hardware, it keep things simple for Linux to assume they are always
384 present.
385
386endif # ISA_ARCV2
387
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530388endmenu # "ARC CPU Configuration"
389
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530390config LINUX_LINK_BASE
391 hex "Linux Link Address"
392 default "0x80000000"
393 help
394 ARC700 divides the 32 bit phy address space into two equal halves
395 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
396 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
397 Typically Linux kernel is linked at the start of untransalted addr,
398 hence the default value of 0x8zs.
399 However some customers have peripherals mapped at this addr, so
400 Linux needs to be scooted a bit.
401 If you don't know what the above means, leave this setting alone.
402
Vineet Gupta080c3742013-02-11 19:52:57 +0530403config ARC_CURR_IN_REG
404 bool "Dedicate Register r25 for current_task pointer"
405 default y
406 help
407 This reserved Register R25 to point to Current Task in
408 kernel mode. This saves memory access for each such access
409
Vineet Gupta2e651ea2013-01-23 16:30:36 +0530410
Vineet Gupta1736a562014-09-08 11:18:15 +0530411config ARC_EMUL_UNALIGNED
Vineet Gupta2e651ea2013-01-23 16:30:36 +0530412 bool "Emulate unaligned memory access (userspace only)"
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530413 default N
Vineet Gupta2e651ea2013-01-23 16:30:36 +0530414 select SYSCTL_ARCH_UNALIGN_NO_WARN
415 select SYSCTL_ARCH_UNALIGN_ALLOW
Vineet Gupta1f6ccff2013-05-13 18:30:41 +0530416 depends on ISA_ARCOMPACT
Vineet Gupta2e651ea2013-01-23 16:30:36 +0530417 help
418 This enables misaligned 16 & 32 bit memory access from user space.
419 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
420 potential bugs in code
421
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530422config HZ
423 int "Timer Frequency"
424 default 100
425
Vineet Guptacbe056f2013-01-18 15:12:25 +0530426config ARC_METAWARE_HLINK
427 bool "Support for Metaware debugger assisted Host access"
428 default n
429 help
430 This options allows a Linux userland apps to directly access
431 host file system (open/creat/read/write etc) with help from
432 Metaware Debugger. This can come in handy for Linux-host communication
433 when there is no real usable peripheral such as EMAC.
434
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530435menuconfig ARC_DBG
436 bool "ARC debugging"
437 default y
438
Vineet Gupta854a0d92013-01-22 17:03:19 +0530439config ARC_DW2_UNWIND
440 bool "Enable DWARF specific kernel stack unwind"
441 depends on ARC_DBG
442 default y
443 select KALLSYMS
444 help
445 Compiles the kernel with DWARF unwind information and can be used
446 to get stack backtraces.
447
448 If you say Y here the resulting kernel image will be slightly larger
449 but not slower, and it will give very useful debugging information.
450 If you don't debug the kernel, you can say N, but we may not be able
451 to solve problems without frame unwind information
452
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530453config ARC_DBG_TLB_PARANOIA
454 bool "Paranoia Checks in Low Level TLB Handlers"
Mischa Jonkerf46121b2013-01-18 15:12:24 +0530455 depends on ARC_DBG
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530456 default n
457
458config ARC_DBG_TLB_MISS_COUNT
459 bool "Profile TLB Misses"
460 default n
461 select DEBUG_FS
462 depends on ARC_DBG
463 help
464 Counts number of I and D TLB Misses and exports them via Debugfs
465 The counters can be cleared via Debugfs as well
466
Vineet Gupta036b2c52015-03-09 19:40:09 +0530467config ARC_UBOOT_SUPPORT
468 bool "Support uboot arg Handling"
469 default n
470 help
471 ARC Linux by default checks for uboot provided args as pointers to
472 external cmdline or DTB. This however breaks in absence of uboot,
473 when booting from Metaware debugger directly, as the registers are
474 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
475 registers look like uboot args to kernel which then chokes.
476 So only enable the uboot arg checking/processing if users are sure
477 of uboot being in play.
478
Vineet Gupta999159a2013-01-22 17:00:52 +0530479config ARC_BUILTIN_DTB_NAME
480 string "Built in DTB"
481 help
482 Set the name of the DTB to embed in the vmlinux binary
483 Leaving it blank selects the minimal "skeleton" dtb
484
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530485source "kernel/Kconfig.preempt"
486
Vineet Gupta56288322013-04-06 14:16:20 +0530487menu "Executable file formats"
488source "fs/Kconfig.binfmt"
489endmenu
490
Vineet Guptacfdbc2e2013-01-18 15:12:20 +0530491endmenu # "ARC Architecture Configuration"
492
493source "mm/Kconfig"
494source "net/Kconfig"
495source "drivers/Kconfig"
496source "fs/Kconfig"
497source "arch/arc/Kconfig.debug"
498source "security/Kconfig"
499source "crypto/Kconfig"
500source "lib/Kconfig"
Alexey Brodkin996bad62014-10-29 15:26:25 +0300501source "kernel/power/Kconfig"