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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright (c) 2001-2002 by David Brownell
David Brownell53bd6a62006-08-30 14:50:06 -07003 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __LINUX_EHCI_HCD_H
20#define __LINUX_EHCI_HCD_H
21
22/* definitions used for the EHCI driver */
23
Stefan Roese6dbd6822007-05-01 09:29:37 -070024/*
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
28 *
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
31 */
32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33typedef __u32 __bitwise __hc32;
34typedef __u16 __bitwise __hc16;
35#else
36#define __hc32 __le32
37#define __hc16 __le16
38#endif
39
Linus Torvalds1da177e2005-04-16 15:20:36 -070040/* statistics can be kept for for tuning/monitoring */
41struct ehci_stats {
42 /* irq usage */
43 unsigned long normal;
44 unsigned long error;
45 unsigned long reclaim;
46 unsigned long lost_iaa;
47
48 /* termination of urbs from core */
49 unsigned long complete;
50 unsigned long unlink;
51};
52
53/* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
57 * ehci_qtd: qtd_list
58 *
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
61 */
62
63#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
64
65struct ehci_hcd { /* one per controller */
David Brownell56c1e262005-04-09 09:00:29 -070066 /* glue to PCI and HCD framework */
67 struct ehci_caps __iomem *caps;
68 struct ehci_regs __iomem *regs;
69 struct ehci_dbg_port __iomem *debug;
70
71 __u32 hcs_params; /* cached register copy */
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 spinlock_t lock;
73
Stuart_Hayes@Dell.com196705c2007-05-03 08:58:49 -070074#ifdef CONFIG_CPU_FREQ
75 struct notifier_block cpufreq_transition;
76 int cpufreq_changing;
77 struct list_head split_intr_qhs;
78#endif
79
Linus Torvalds1da177e2005-04-16 15:20:36 -070080 /* async schedule support */
81 struct ehci_qh *async;
82 struct ehci_qh *reclaim;
Greg Kroah-Hartman64f89792006-10-17 13:57:18 -070083 unsigned reclaim_ready : 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 unsigned scanning : 1;
85
86 /* periodic schedule support */
87#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
88 unsigned periodic_size;
Stefan Roese6dbd6822007-05-01 09:29:37 -070089 __hc32 *periodic; /* hw periodic table */
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 dma_addr_t periodic_dma;
91 unsigned i_thresh; /* uframes HC might cache */
92
93 union ehci_shadow *pshadow; /* mirror hw periodic table */
94 int next_uframe; /* scan periodic, start here */
95 unsigned periodic_sched; /* periodic activity count */
96
97 /* per root hub port */
98 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
Alan Stern383975d2007-05-04 11:52:40 -040099
Alan Stern57e06c12007-01-16 11:59:45 -0500100 /* bit vectors (one bit per port) */
101 unsigned long bus_suspended; /* which ports were
102 already suspended at the start of a bus suspend */
103 unsigned long companion_ports; /* which ports are
104 dedicated to the companion controller */
Alan Stern383975d2007-05-04 11:52:40 -0400105 unsigned long owned_ports; /* which ports are
106 owned by the companion during a bus suspend */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
108 /* per-HC memory pools (could be per-bus, but ...) */
109 struct dma_pool *qh_pool; /* qh per active urb */
110 struct dma_pool *qtd_pool; /* one or more per qh */
111 struct dma_pool *itd_pool; /* itd per iso urb */
112 struct dma_pool *sitd_pool; /* sitd per split iso urb */
113
114 struct timer_list watchdog;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 unsigned long actions;
116 unsigned stamp;
117 unsigned long next_statechange;
118 u32 command;
119
Kumar Gala8cd42e92006-01-20 13:57:52 -0800120 /* SILICON QUIRKS */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */
David Brownellf8aeb3b2006-01-20 13:55:14 -0800122 unsigned no_selective_suspend:1;
Kumar Gala8cd42e92006-01-20 13:57:52 -0800123 unsigned has_fsl_port_bug:1; /* FreeScale */
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100124 unsigned big_endian_mmio:1;
Stefan Roese6dbd6822007-05-01 09:29:37 -0700125 unsigned big_endian_desc:1;
Kumar Gala8cd42e92006-01-20 13:57:52 -0800126
David Brownellf8aeb3b2006-01-20 13:55:14 -0800127 u8 sbrn; /* packed release number */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 /* irq statistics */
130#ifdef EHCI_STATS
131 struct ehci_stats stats;
132# define COUNT(x) do { (x)++; } while (0)
133#else
134# define COUNT(x) do {} while (0)
135#endif
136};
137
David Brownell53bd6a62006-08-30 14:50:06 -0700138/* convert between an HCD pointer and the corresponding EHCI_HCD */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
140{
141 return (struct ehci_hcd *) (hcd->hcd_priv);
142}
143static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
144{
145 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
146}
147
148
149enum ehci_timer_action {
150 TIMER_IO_WATCHDOG,
Greg Kroah-Hartman64f89792006-10-17 13:57:18 -0700151 TIMER_IAA_WATCHDOG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 TIMER_ASYNC_SHRINK,
153 TIMER_ASYNC_OFF,
154};
155
156static inline void
157timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
158{
159 clear_bit (action, &ehci->actions);
160}
161
162static inline void
163timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
164{
165 if (!test_and_set_bit (action, &ehci->actions)) {
166 unsigned long t;
167
168 switch (action) {
Greg Kroah-Hartman64f89792006-10-17 13:57:18 -0700169 case TIMER_IAA_WATCHDOG:
170 t = EHCI_IAA_JIFFIES;
171 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 case TIMER_IO_WATCHDOG:
173 t = EHCI_IO_JIFFIES;
174 break;
175 case TIMER_ASYNC_OFF:
176 t = EHCI_ASYNC_JIFFIES;
177 break;
178 // case TIMER_ASYNC_SHRINK:
179 default:
180 t = EHCI_SHRINK_JIFFIES;
181 break;
182 }
183 t += jiffies;
184 // all timings except IAA watchdog can be overridden.
185 // async queue SHRINK often precedes IAA. while it's ready
186 // to go OFF neither can matter, and afterwards the IO
187 // watchdog stops unless there's still periodic traffic.
Greg Kroah-Hartman64f89792006-10-17 13:57:18 -0700188 if (action != TIMER_IAA_WATCHDOG
189 && t > ehci->watchdog.expires
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190 && timer_pending (&ehci->watchdog))
191 return;
192 mod_timer (&ehci->watchdog, t);
193 }
194}
195
196/*-------------------------------------------------------------------------*/
197
198/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
199
200/* Section 2.2 Host Controller Capability Registers */
201struct ehci_caps {
202 /* these fields are specified as 8 and 16 bit registers,
203 * but some hosts can't perform 8 or 16 bit PCI accesses.
204 */
David Brownell56c1e262005-04-09 09:00:29 -0700205 u32 hc_capbase;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
207#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
208 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
209#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
210#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
211#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
212#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
David Brownell53bd6a62006-08-30 14:50:06 -0700213#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
214#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
216
217 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
218#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
219#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
220#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
221#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
222#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
223#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
224 u8 portroute [8]; /* nibbles for routing - offset 0xC */
225} __attribute__ ((packed));
226
227
228/* Section 2.3 Host Controller Operational Registers */
229struct ehci_regs {
230
231 /* USBCMD: offset 0x00 */
232 u32 command;
233/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
234#define CMD_PARK (1<<11) /* enable "park" on async qh */
235#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
236#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
237#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
238#define CMD_ASE (1<<5) /* async schedule enable */
David Brownell53bd6a62006-08-30 14:50:06 -0700239#define CMD_PSE (1<<4) /* periodic schedule enable */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240/* 3:2 is periodic frame list size */
241#define CMD_RESET (1<<1) /* reset HC not bus */
242#define CMD_RUN (1<<0) /* start/stop HC */
243
244 /* USBSTS: offset 0x04 */
245 u32 status;
246#define STS_ASS (1<<15) /* Async Schedule Status */
247#define STS_PSS (1<<14) /* Periodic Schedule Status */
248#define STS_RECL (1<<13) /* Reclamation */
249#define STS_HALT (1<<12) /* Not running (any reason) */
250/* some bits reserved */
251 /* these STS_* flags are also intr_enable bits (USBINTR) */
252#define STS_IAA (1<<5) /* Interrupted on async advance */
253#define STS_FATAL (1<<4) /* such as some PCI access errors */
254#define STS_FLR (1<<3) /* frame list rolled over */
255#define STS_PCD (1<<2) /* port change detect */
256#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
257#define STS_INT (1<<0) /* "normal" completion (short, ...) */
258
259 /* USBINTR: offset 0x08 */
260 u32 intr_enable;
261
262 /* FRINDEX: offset 0x0C */
263 u32 frame_index; /* current microframe number */
264 /* CTRLDSSEGMENT: offset 0x10 */
David Brownell53bd6a62006-08-30 14:50:06 -0700265 u32 segment; /* address bits 63:32 if needed */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266 /* PERIODICLISTBASE: offset 0x14 */
David Brownell53bd6a62006-08-30 14:50:06 -0700267 u32 frame_list; /* points to periodic list */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 /* ASYNCLISTADDR: offset 0x18 */
269 u32 async_next; /* address of next async queue head */
270
271 u32 reserved [9];
272
273 /* CONFIGFLAG: offset 0x40 */
274 u32 configured_flag;
275#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
276
277 /* PORTSC: offset 0x44 */
278 u32 port_status [0]; /* up to N_PORTS */
279/* 31:23 reserved */
280#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
281#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
282#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
283/* 19:16 for port testing */
284#define PORT_LED_OFF (0<<14)
285#define PORT_LED_AMBER (1<<14)
286#define PORT_LED_GREEN (2<<14)
287#define PORT_LED_MASK (3<<14)
288#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
289#define PORT_POWER (1<<12) /* true: has power (see PPC) */
290#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
291/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
292/* 9 reserved */
293#define PORT_RESET (1<<8) /* reset port */
294#define PORT_SUSPEND (1<<7) /* suspend port */
295#define PORT_RESUME (1<<6) /* resume it */
296#define PORT_OCC (1<<5) /* over current change */
297#define PORT_OC (1<<4) /* over current active */
298#define PORT_PEC (1<<3) /* port enable change */
299#define PORT_PE (1<<2) /* port enable */
300#define PORT_CSC (1<<1) /* connect status change */
301#define PORT_CONNECT (1<<0) /* device connected */
David Brownell10f65242005-08-31 10:55:38 -0700302#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303} __attribute__ ((packed));
304
Vladimir Barinovd23a1372007-05-23 20:07:48 +0400305#define USBMODE 0x68 /* USB Device mode */
306#define USBMODE_SDIS (1<<3) /* Stream disable */
307#define USBMODE_BE (1<<2) /* BE/LE endianness select */
308#define USBMODE_CM_HC (3<<0) /* host controller mode */
309#define USBMODE_CM_IDLE (0<<0) /* idle state */
310
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311/* Appendix C, Debug port ... intended for use with special "debug devices"
312 * that can help if there's no serial console. (nonstandard enumeration.)
313 */
314struct ehci_dbg_port {
315 u32 control;
316#define DBGP_OWNER (1<<30)
317#define DBGP_ENABLED (1<<28)
318#define DBGP_DONE (1<<16)
319#define DBGP_INUSE (1<<10)
David Brownell56c1e262005-04-09 09:00:29 -0700320#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321# define DBGP_ERR_BAD 1
322# define DBGP_ERR_SIGNAL 2
323#define DBGP_ERROR (1<<6)
324#define DBGP_GO (1<<5)
325#define DBGP_OUT (1<<4)
326#define DBGP_LEN(x) (((x)>>0)&0x0f)
327 u32 pids;
328#define DBGP_PID_GET(x) (((x)>>16)&0xff)
David Brownell56c1e262005-04-09 09:00:29 -0700329#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330 u32 data03;
331 u32 data47;
332 u32 address;
David Brownell56c1e262005-04-09 09:00:29 -0700333#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334} __attribute__ ((packed));
335
336/*-------------------------------------------------------------------------*/
337
Stefan Roese6dbd6822007-05-01 09:29:37 -0700338#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339
340/*
341 * EHCI Specification 0.95 Section 3.5
David Brownell53bd6a62006-08-30 14:50:06 -0700342 * QTD: describe data transfer components (buffer, direction, ...)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
344 *
345 * These are associated only with "QH" (Queue Head) structures,
346 * used with control, bulk, and interrupt transfers.
347 */
348struct ehci_qtd {
349 /* first part defined by EHCI spec */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700350 __hc32 hw_next; /* see EHCI 3.5.1 */
351 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
352 __hc32 hw_token; /* see EHCI 3.5.3 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353#define QTD_TOGGLE (1 << 31) /* data toggle */
354#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
355#define QTD_IOC (1 << 15) /* interrupt on complete */
356#define QTD_CERR(tok) (((tok)>>10) & 0x3)
357#define QTD_PID(tok) (((tok)>>8) & 0x3)
358#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
359#define QTD_STS_HALT (1 << 6) /* halted on error */
360#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
361#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
362#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
363#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
364#define QTD_STS_STS (1 << 1) /* split transaction state */
365#define QTD_STS_PING (1 << 0) /* issue PING? */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700366
367#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
368#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
369#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
370
371 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
372 __hc32 hw_buf_hi [5]; /* Appendix B */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373
374 /* the rest is HCD-private */
375 dma_addr_t qtd_dma; /* qtd address */
376 struct list_head qtd_list; /* sw qtd list */
377 struct urb *urb; /* qtd's urb */
378 size_t length; /* length of buffer */
379} __attribute__ ((aligned (32)));
380
381/* mask NakCnt+T in qh->hw_alt_next */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700382#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383
384#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
385
386/*-------------------------------------------------------------------------*/
387
388/* type tag from {qh,itd,sitd,fstn}->hw_next */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700389#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390
Stefan Roese6dbd6822007-05-01 09:29:37 -0700391/*
392 * Now the following defines are not converted using the
393 * __constant_cpu_to_le32() macro anymore, since we have to support
394 * "dynamic" switching between be and le support, so that the driver
395 * can be used on one system with SoC EHCI controller using big-endian
396 * descriptors as well as a normal little-endian PCI EHCI controller.
397 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398/* values for that type tag */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700399#define Q_TYPE_ITD (0 << 1)
400#define Q_TYPE_QH (1 << 1)
401#define Q_TYPE_SITD (2 << 1)
402#define Q_TYPE_FSTN (3 << 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403
404/* next async queue entry, or pointer to interrupt/periodic QH */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700405#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406
407/* for periodic/async schedules and qtd lists, mark end of list */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700408#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409
410/*
411 * Entries in periodic shadow table are pointers to one of four kinds
412 * of data structure. That's dictated by the hardware; a type tag is
413 * encoded in the low bits of the hardware's periodic schedule. Use
414 * Q_NEXT_TYPE to get the tag.
415 *
416 * For entries in the async schedule, the type tag always says "qh".
417 */
418union ehci_shadow {
David Brownell53bd6a62006-08-30 14:50:06 -0700419 struct ehci_qh *qh; /* Q_TYPE_QH */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 struct ehci_itd *itd; /* Q_TYPE_ITD */
421 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
422 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700423 __hc32 *hw_next; /* (all types) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 void *ptr;
425};
426
427/*-------------------------------------------------------------------------*/
428
429/*
430 * EHCI Specification 0.95 Section 3.6
431 * QH: describes control/bulk/interrupt endpoints
432 * See Fig 3-7 "Queue Head Structure Layout".
433 *
434 * These appear in both the async and (for interrupt) periodic schedules.
435 */
436
437struct ehci_qh {
438 /* first part defined by EHCI spec */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700439 __hc32 hw_next; /* see EHCI 3.6.1 */
440 __hc32 hw_info1; /* see EHCI 3.6.2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441#define QH_HEAD 0x00008000
Stuart_Hayes@Dell.com196705c2007-05-03 08:58:49 -0700442#define QH_INACTIVATE 0x00000080
Stefan Roese6dbd6822007-05-01 09:29:37 -0700443
444#define INACTIVATE_BIT(ehci) cpu_to_hc32(ehci, QH_INACTIVATE)
445
446 __hc32 hw_info2; /* see EHCI 3.6.2 */
David Brownell7dedacf2005-08-04 18:06:41 -0700447#define QH_SMASK 0x000000ff
448#define QH_CMASK 0x0000ff00
449#define QH_HUBADDR 0x007f0000
450#define QH_HUBPORT 0x3f800000
451#define QH_MULT 0xc0000000
Stefan Roese6dbd6822007-05-01 09:29:37 -0700452 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
David Brownell53bd6a62006-08-30 14:50:06 -0700453
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 /* qtd overlay (hardware parts of a struct ehci_qtd) */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700455 __hc32 hw_qtd_next;
456 __hc32 hw_alt_next;
457 __hc32 hw_token;
458 __hc32 hw_buf [5];
459 __hc32 hw_buf_hi [5];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460
461 /* the rest is HCD-private */
462 dma_addr_t qh_dma; /* address of qh */
463 union ehci_shadow qh_next; /* ptr to qh; or periodic */
464 struct list_head qtd_list; /* sw qtd list */
465 struct ehci_qtd *dummy;
466 struct ehci_qh *reclaim; /* next to reclaim */
467
468 struct ehci_hcd *ehci;
David Brownell9c033e82007-05-17 12:21:19 -0700469
470 /*
471 * Do NOT use atomic operations for QH refcounting. On some CPUs
472 * (PPC7448 for example), atomic operations cannot be performed on
473 * memory that is cache-inhibited (i.e. being used for DMA).
474 * Spinlocks are used to protect all QH fields.
475 */
476 u32 refcount;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477 unsigned stamp;
478
479 u8 qh_state;
480#define QH_STATE_LINKED 1 /* HC sees this */
481#define QH_STATE_UNLINK 2 /* HC may still see this */
482#define QH_STATE_IDLE 3 /* HC doesn't see this */
483#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
484#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
485
486 /* periodic schedule info */
487 u8 usecs; /* intr bandwidth */
488 u8 gap_uf; /* uframes split/csplit gap */
489 u8 c_usecs; /* ... split completion bw */
david-b@pacbell.netd0384202005-08-13 18:44:58 -0700490 u16 tt_usecs; /* tt downstream bandwidth */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491 unsigned short period; /* polling interval */
492 unsigned short start; /* where polling starts */
493#define NO_FRAME ((unsigned short)~0) /* pick new start */
494 struct usb_device *dev; /* access to TT */
Stuart_Hayes@Dell.com196705c2007-05-03 08:58:49 -0700495#ifdef CONFIG_CPU_FREQ
496 struct list_head split_intr_qhs; /* list of split qhs */
497 __le32 was_active; /* active bit before "i" set */
498#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499} __attribute__ ((aligned (32)));
500
501/*-------------------------------------------------------------------------*/
502
503/* description of one iso transaction (up to 3 KB data if highspeed) */
504struct ehci_iso_packet {
505 /* These will be copied to iTD when scheduling */
506 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700507 __hc32 transaction; /* itd->hw_transaction[i] |= */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 u8 cross; /* buf crosses pages */
509 /* for full speed OUT splits */
510 u32 buf1;
511};
512
513/* temporary schedule data for packets from iso urbs (both speeds)
514 * each packet is one logical usb transaction to the device (not TT),
515 * beginning at stream->next_uframe
516 */
517struct ehci_iso_sched {
518 struct list_head td_list;
519 unsigned span;
520 struct ehci_iso_packet packet [0];
521};
522
523/*
524 * ehci_iso_stream - groups all (s)itds for this endpoint.
525 * acts like a qh would, if EHCI had them for ISO.
526 */
527struct ehci_iso_stream {
528 /* first two fields match QH, but info1 == 0 */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700529 __hc32 hw_next;
530 __hc32 hw_info1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531
532 u32 refcount;
533 u8 bEndpointAddress;
534 u8 highspeed;
535 u16 depth; /* depth in uframes */
536 struct list_head td_list; /* queued itds/sitds */
537 struct list_head free_list; /* list of unused itds/sitds */
538 struct usb_device *udev;
David Brownell53bd6a62006-08-30 14:50:06 -0700539 struct usb_host_endpoint *ep;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540
541 /* output of (re)scheduling */
542 unsigned long start; /* jiffies */
543 unsigned long rescheduled;
544 int next_uframe;
Stefan Roese6dbd6822007-05-01 09:29:37 -0700545 __hc32 splits;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546
547 /* the rest is derived from the endpoint descriptor,
548 * trusting urb->interval == f(epdesc->bInterval) and
549 * including the extra info for hw_bufp[0..2]
550 */
551 u8 interval;
552 u8 usecs, c_usecs;
david-b@pacbell.netd0384202005-08-13 18:44:58 -0700553 u16 tt_usecs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700554 u16 maxp;
555 u16 raw_mask;
556 unsigned bandwidth;
557
558 /* This is used to initialize iTD's hw_bufp fields */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700559 __hc32 buf0;
560 __hc32 buf1;
561 __hc32 buf2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562
563 /* this is used to initialize sITD's tt info */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700564 __hc32 address;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565};
566
567/*-------------------------------------------------------------------------*/
568
569/*
570 * EHCI Specification 0.95 Section 3.3
571 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
572 *
573 * Schedule records for high speed iso xfers
574 */
575struct ehci_itd {
576 /* first part defined by EHCI spec */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700577 __hc32 hw_next; /* see EHCI 3.3.1 */
578 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
580#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
581#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
582#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
583#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
584#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
585
Stefan Roese6dbd6822007-05-01 09:29:37 -0700586#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587
Stefan Roese6dbd6822007-05-01 09:29:37 -0700588 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
589 __hc32 hw_bufp_hi [7]; /* Appendix B */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590
591 /* the rest is HCD-private */
592 dma_addr_t itd_dma; /* for this itd */
593 union ehci_shadow itd_next; /* ptr to periodic q entry */
594
595 struct urb *urb;
596 struct ehci_iso_stream *stream; /* endpoint's queue */
597 struct list_head itd_list; /* list of stream's itds */
598
599 /* any/all hw_transactions here may be used by that urb */
600 unsigned frame; /* where scheduled */
601 unsigned pg;
602 unsigned index[8]; /* in urb->iso_frame_desc */
603 u8 usecs[8];
604} __attribute__ ((aligned (32)));
605
606/*-------------------------------------------------------------------------*/
607
608/*
David Brownell53bd6a62006-08-30 14:50:06 -0700609 * EHCI Specification 0.95 Section 3.4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610 * siTD, aka split-transaction isochronous Transfer Descriptor
611 * ... describe full speed iso xfers through TT in hubs
612 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
613 */
614struct ehci_sitd {
615 /* first part defined by EHCI spec */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700616 __hc32 hw_next;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617/* uses bit field macros above - see EHCI 0.95 Table 3-8 */
Stefan Roese6dbd6822007-05-01 09:29:37 -0700618 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
619 __hc32 hw_uframe; /* EHCI table 3-10 */
620 __hc32 hw_results; /* EHCI table 3-11 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621#define SITD_IOC (1 << 31) /* interrupt on completion */
622#define SITD_PAGE (1 << 30) /* buffer 0/1 */
623#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
624#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
625#define SITD_STS_ERR (1 << 6) /* error from TT */
626#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
627#define SITD_STS_BABBLE (1 << 4) /* device was babbling */
628#define SITD_STS_XACT (1 << 3) /* illegal IN response */
629#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
630#define SITD_STS_STS (1 << 1) /* split transaction state */
631
Stefan Roese6dbd6822007-05-01 09:29:37 -0700632#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633
Stefan Roese6dbd6822007-05-01 09:29:37 -0700634 __hc32 hw_buf [2]; /* EHCI table 3-12 */
635 __hc32 hw_backpointer; /* EHCI table 3-13 */
636 __hc32 hw_buf_hi [2]; /* Appendix B */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637
638 /* the rest is HCD-private */
639 dma_addr_t sitd_dma;
640 union ehci_shadow sitd_next; /* ptr to periodic q entry */
641
642 struct urb *urb;
643 struct ehci_iso_stream *stream; /* endpoint's queue */
644 struct list_head sitd_list; /* list of stream's sitds */
645 unsigned frame;
646 unsigned index;
647} __attribute__ ((aligned (32)));
648
649/*-------------------------------------------------------------------------*/
650
651/*
652 * EHCI Specification 0.96 Section 3.7
653 * Periodic Frame Span Traversal Node (FSTN)
654 *
655 * Manages split interrupt transactions (using TT) that span frame boundaries
656 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
657 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
658 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
659 */
660struct ehci_fstn {
Stefan Roese6dbd6822007-05-01 09:29:37 -0700661 __hc32 hw_next; /* any periodic q entry */
662 __hc32 hw_prev; /* qh or EHCI_LIST_END */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663
664 /* the rest is HCD-private */
665 dma_addr_t fstn_dma;
666 union ehci_shadow fstn_next; /* ptr to periodic q entry */
667} __attribute__ ((aligned (32)));
668
669/*-------------------------------------------------------------------------*/
670
671#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
672
673/*
674 * Some EHCI controllers have a Transaction Translator built into the
675 * root hub. This is a non-standard feature. Each controller will need
676 * to add code to the following inline functions, and call them as
677 * needed (mostly in root hub code).
678 */
679
680#define ehci_is_TDI(e) ((e)->is_tdi_rh_tt)
681
682/* Returns the speed of a device attached to a port on the root hub. */
683static inline unsigned int
684ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
685{
686 if (ehci_is_TDI(ehci)) {
687 switch ((portsc>>26)&3) {
688 case 0:
689 return 0;
690 case 1:
691 return (1<<USB_PORT_FEAT_LOWSPEED);
692 case 2:
693 default:
694 return (1<<USB_PORT_FEAT_HIGHSPEED);
695 }
696 }
697 return (1<<USB_PORT_FEAT_HIGHSPEED);
698}
699
700#else
701
702#define ehci_is_TDI(e) (0)
703
704#define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
705#endif
706
707/*-------------------------------------------------------------------------*/
708
Kumar Gala8cd42e92006-01-20 13:57:52 -0800709#ifdef CONFIG_PPC_83xx
710/* Some Freescale processors have an erratum in which the TT
711 * port number in the queue head was 0..N-1 instead of 1..N.
712 */
713#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
714#else
715#define ehci_has_fsl_portno_bug(e) (0)
716#endif
717
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100718/*
719 * While most USB host controllers implement their registers in
720 * little-endian format, a minority (celleb companion chip) implement
721 * them in big endian format.
722 *
723 * This attempts to support either format at compile time without a
724 * runtime penalty, or both formats with the additional overhead
725 * of checking a flag bit.
726 */
727
728#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
729#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
730#else
731#define ehci_big_endian_mmio(e) 0
732#endif
733
Stefan Roese6dbd6822007-05-01 09:29:37 -0700734/*
735 * Big-endian read/write functions are arch-specific.
736 * Other arches can be added if/when they're needed.
737 *
738 * REVISIT: arch/powerpc now has readl/writel_be, so the
739 * definition below can die once the 4xx support is
740 * finally ported over.
741 */
742#if defined(CONFIG_PPC)
743#define readl_be(addr) in_be32((__force unsigned *)addr)
744#define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
745#endif
746
747static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
748 __u32 __iomem * regs)
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100749{
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100750#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100751 return ehci_big_endian_mmio(ehci) ?
Al Viro68f50e52007-02-09 16:40:00 +0000752 readl_be(regs) :
753 readl(regs);
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100754#else
Al Viro68f50e52007-02-09 16:40:00 +0000755 return readl(regs);
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100756#endif
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100757}
758
Stefan Roese6dbd6822007-05-01 09:29:37 -0700759static inline void ehci_writel(const struct ehci_hcd *ehci,
760 const unsigned int val, __u32 __iomem *regs)
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100761{
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100762#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100763 ehci_big_endian_mmio(ehci) ?
Al Viro68f50e52007-02-09 16:40:00 +0000764 writel_be(val, regs) :
765 writel(val, regs);
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100766#else
Al Viro68f50e52007-02-09 16:40:00 +0000767 writel(val, regs);
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100768#endif
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100769}
Kumar Gala8cd42e92006-01-20 13:57:52 -0800770
771/*-------------------------------------------------------------------------*/
772
Stefan Roese6dbd6822007-05-01 09:29:37 -0700773/*
774 * The AMCC 440EPx not only implements its EHCI registers in big-endian
775 * format, but also its DMA data structures (descriptors).
776 *
777 * EHCI controllers accessed through PCI work normally (little-endian
778 * everywhere), so we won't bother supporting a BE-only mode for now.
779 */
780#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
781#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
782
783/* cpu to ehci */
784static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
785{
786 return ehci_big_endian_desc(ehci)
787 ? (__force __hc32)cpu_to_be32(x)
788 : (__force __hc32)cpu_to_le32(x);
789}
790
791/* ehci to cpu */
792static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
793{
794 return ehci_big_endian_desc(ehci)
795 ? be32_to_cpu((__force __be32)x)
796 : le32_to_cpu((__force __le32)x);
797}
798
799static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
800{
801 return ehci_big_endian_desc(ehci)
802 ? be32_to_cpup((__force __be32 *)x)
803 : le32_to_cpup((__force __le32 *)x);
804}
805
806#else
807
808/* cpu to ehci */
809static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
810{
811 return cpu_to_le32(x);
812}
813
814/* ehci to cpu */
815static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
816{
817 return le32_to_cpu(x);
818}
819
820static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
821{
822 return le32_to_cpup(x);
823}
824
825#endif
826
827/*-------------------------------------------------------------------------*/
828
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829#ifndef DEBUG
830#define STUB_DEBUG_FILES
831#endif /* DEBUG */
832
833/*-------------------------------------------------------------------------*/
834
835#endif /* __LINUX_EHCI_HCD_H */