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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sc-rm7k.c: RM7000 cache management functions.
3 *
4 * Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
5 */
6
7#undef DEBUG
8
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/kernel.h>
10#include <linux/mm.h>
Atsushi Nemoto37caa932006-02-15 18:25:48 +090011#include <linux/bitops.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070012
13#include <asm/addrspace.h>
14#include <asm/bcache.h>
15#include <asm/cacheops.h>
16#include <asm/mipsregs.h>
17#include <asm/processor.h>
Ricardo Mendoza745aef52010-07-19 05:00:00 +010018#include <asm/sections.h>
Thiemo Seuferba5187d2005-04-25 16:36:23 +000019#include <asm/cacheflush.h> /* for run_uncached() */
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
21/* Primary cache parameters. */
22#define sc_lsize 32
23#define tc_pagesize (32*128)
24
25/* Secondary cache parameters. */
26#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
27
Ricardo Mendoza745aef52010-07-19 05:00:00 +010028/* Tertiary cache parameters */
29#define tc_lsize 32
30
Linus Torvalds1da177e2005-04-16 15:20:36 -070031extern unsigned long icache_way_size, dcache_way_size;
Ricardo Mendoza543001f2010-08-06 11:12:57 -043032static unsigned long tcache_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34#include <asm/r4kcache.h>
35
Ricardo Mendoza745aef52010-07-19 05:00:00 +010036static int rm7k_tcache_init;
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
38/*
39 * Writeback and invalidate the primary cache dcache before DMA.
40 * (XXX These need to be fixed ...)
41 */
42static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
43{
44 unsigned long end, a;
45
46 pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size);
47
48 /* Catch bad driver code */
49 BUG_ON(size == 0);
50
Atsushi Nemoto37caa932006-02-15 18:25:48 +090051 blast_scache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Ricardo Mendoza745aef52010-07-19 05:00:00 +010053 if (!rm7k_tcache_init)
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 return;
55
56 a = addr & ~(tc_pagesize - 1);
57 end = (addr + size - 1) & ~(tc_pagesize - 1);
58 while(1) {
59 invalidate_tcache_page(a); /* Page_Invalidate_T */
60 if (a == end)
61 break;
62 a += tc_pagesize;
63 }
64}
65
66static void rm7k_sc_inv(unsigned long addr, unsigned long size)
67{
68 unsigned long end, a;
69
70 pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr, size);
71
72 /* Catch bad driver code */
73 BUG_ON(size == 0);
74
Atsushi Nemoto37caa932006-02-15 18:25:48 +090075 blast_inv_scache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -070076
Ricardo Mendoza745aef52010-07-19 05:00:00 +010077 if (!rm7k_tcache_init)
Linus Torvalds1da177e2005-04-16 15:20:36 -070078 return;
79
80 a = addr & ~(tc_pagesize - 1);
81 end = (addr + size - 1) & ~(tc_pagesize - 1);
82 while(1) {
83 invalidate_tcache_page(a); /* Page_Invalidate_T */
84 if (a == end)
85 break;
86 a += tc_pagesize;
87 }
88}
89
Ricardo Mendoza745aef52010-07-19 05:00:00 +010090static void blast_rm7k_tcache(void)
91{
92 unsigned long start = CKSEG0ADDR(0);
93 unsigned long end = start + tcache_size;
94
95 write_c0_taglo(0);
96
97 while (start < end) {
98 cache_op(Page_Invalidate_T, start);
99 start += tc_pagesize;
100 }
101}
102
103/*
104 * This function is executed in uncached address space.
105 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000106static void __rm7k_tc_enable(void)
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100107{
108 int i;
109
110 set_c0_config(RM7K_CONF_TE);
111
112 write_c0_taglo(0);
113 write_c0_taghi(0);
114
115 for (i = 0; i < tcache_size; i += tc_lsize)
116 cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
117}
118
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000119static void rm7k_tc_enable(void)
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100120{
121 if (read_c0_config() & RM7K_CONF_TE)
122 return;
123
124 BUG_ON(tcache_size == 0);
125
126 run_uncached(__rm7k_tc_enable);
127}
128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129/*
Thiemo Seuferba5187d2005-04-25 16:36:23 +0000130 * This function is executed in uncached address space.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000132static void __rm7k_sc_enable(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133{
134 int i;
135
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000136 set_c0_config(RM7K_CONF_SE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137
138 write_c0_taglo(0);
139 write_c0_taghi(0);
140
Ricardo Mendoza58a6d452010-07-19 04:59:59 +0100141 for (i = 0; i < scache_size; i += sc_lsize)
142 cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143}
144
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000145static void rm7k_sc_enable(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146{
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000147 if (read_c0_config() & RM7K_CONF_SE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148 return;
149
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100150 pr_info("Enabling secondary cache...\n");
Thiemo Seuferba5187d2005-04-25 16:36:23 +0000151 run_uncached(__rm7k_sc_enable);
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100152
153 if (rm7k_tcache_init)
154 rm7k_tc_enable();
155}
156
157static void rm7k_tc_disable(void)
158{
159 unsigned long flags;
160
161 local_irq_save(flags);
162 blast_rm7k_tcache();
163 clear_c0_config(RM7K_CONF_TE);
164 local_irq_save(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165}
166
167static void rm7k_sc_disable(void)
168{
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000169 clear_c0_config(RM7K_CONF_SE);
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100170
171 if (rm7k_tcache_init)
172 rm7k_tc_disable();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173}
174
Dmitri Vorobiev12914172009-03-30 22:53:23 +0300175static struct bcache_ops rm7k_sc_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 .bc_enable = rm7k_sc_enable,
177 .bc_disable = rm7k_sc_disable,
178 .bc_wback_inv = rm7k_sc_wback_inv,
179 .bc_inv = rm7k_sc_inv
180};
181
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100182/*
183 * This is a probing function like the one found in c-r4k.c, we look for the
184 * wrap around point with different addresses.
185 */
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000186static void __probe_tcache(void)
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100187{
188 unsigned long flags, addr, begin, end, pow2;
189
190 begin = (unsigned long) &_stext;
191 begin &= ~((8 * 1024 * 1024) - 1);
192 end = begin + (8 * 1024 * 1024);
193
194 local_irq_save(flags);
195
196 set_c0_config(RM7K_CONF_TE);
197
198 /* Fill size-multiple lines with a valid tag */
199 pow2 = (256 * 1024);
200 for (addr = begin; addr <= end; addr = (begin + pow2)) {
201 unsigned long *p = (unsigned long *) addr;
202 __asm__ __volatile__("nop" : : "r" (*p));
203 pow2 <<= 1;
204 }
205
206 /* Load first line with a 0 tag, to check after */
207 write_c0_taglo(0);
208 write_c0_taghi(0);
209 cache_op(Index_Store_Tag_T, begin);
210
211 /* Look for the wrap-around */
212 pow2 = (512 * 1024);
213 for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
214 cache_op(Index_Load_Tag_T, addr);
215 if (!read_c0_taglo())
216 break;
217 pow2 <<= 1;
218 }
219
220 addr -= begin;
221 tcache_size = addr;
222
223 clear_c0_config(RM7K_CONF_TE);
224
225 local_irq_restore(flags);
226}
227
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000228void rm7k_sc_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229{
Atsushi Nemoto37caa932006-02-15 18:25:48 +0900230 struct cpuinfo_mips *c = &current_cpu_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 unsigned int config = read_c0_config();
232
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000233 if ((config & RM7K_CONF_SC))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 return;
235
Atsushi Nemoto37caa932006-02-15 18:25:48 +0900236 c->scache.linesz = sc_lsize;
237 c->scache.ways = 4;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +0900238 c->scache.waybit= __ffs(scache_size / c->scache.ways);
Atsushi Nemoto37caa932006-02-15 18:25:48 +0900239 c->scache.waysize = scache_size / c->scache.ways;
240 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
242 (scache_size >> 10), sc_lsize);
243
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000244 if (!(config & RM7K_CONF_SE))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 rm7k_sc_enable();
246
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100247 bcops = &rm7k_sc_ops;
248
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249 /*
250 * While we're at it let's deal with the tertiary cache.
251 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100253 rm7k_tcache_init = 0;
254 tcache_size = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100256 if (config & RM7K_CONF_TC)
257 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258
Ricardo Mendoza745aef52010-07-19 05:00:00 +0100259 /*
260 * No efficient way to ask the hardware for the size of the tcache,
261 * so must probe for it.
262 */
263 run_uncached(__probe_tcache);
264 rm7k_tc_enable();
265 rm7k_tcache_init = 1;
266 c->tcache.linesz = tc_lsize;
267 c->tcache.ways = 1;
268 pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269}