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Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -05001/*
2 * CXL Flash Device Driver
3 *
4 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
5 * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
6 *
7 * Copyright (C) 2015 IBM Corporation
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#ifndef _CXLFLASH_MAIN_H
16#define _CXLFLASH_MAIN_H
17
18#include <linux/list.h>
19#include <linux/types.h>
20#include <scsi/scsi.h>
21#include <scsi/scsi_device.h>
22
23#define CXLFLASH_NAME "cxlflash"
24#define CXLFLASH_ADAPTER_NAME "IBM POWER CXL Flash Adapter"
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050025
Manoj Kumara2746fb2015-12-14 15:07:43 -060026#define PCI_DEVICE_ID_IBM_CORSA 0x04F0
27#define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050028
29/* Since there is only one target, make it 0 */
30#define CXLFLASH_TARGET 0
31#define CXLFLASH_MAX_CDB_LEN 16
32
33/* Really only one target per bus since the Texan is directly attached */
34#define CXLFLASH_MAX_NUM_TARGETS_PER_BUS 1
35#define CXLFLASH_MAX_NUM_LUNS_PER_TARGET 65536
36
37#define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ)
38
39#define NUM_FC_PORTS CXLFLASH_NUM_FC_PORTS /* ports per AFU */
40
41/* FC defines */
42#define FC_MTIP_CMDCONFIG 0x010
43#define FC_MTIP_STATUS 0x018
44
45#define FC_PNAME 0x300
46#define FC_CONFIG 0x320
47#define FC_CONFIG2 0x328
48#define FC_STATUS 0x330
49#define FC_ERROR 0x380
50#define FC_ERRCAP 0x388
51#define FC_ERRMSK 0x390
52#define FC_CNT_CRCERR 0x538
53#define FC_CRC_THRESH 0x580
54
55#define FC_MTIP_CMDCONFIG_ONLINE 0x20ULL
56#define FC_MTIP_CMDCONFIG_OFFLINE 0x40ULL
57
58#define FC_MTIP_STATUS_MASK 0x30ULL
59#define FC_MTIP_STATUS_ONLINE 0x20ULL
60#define FC_MTIP_STATUS_OFFLINE 0x10ULL
61
62/* TIMEOUT and RETRY definitions */
63
64/* AFU command timeout values */
65#define MC_AFU_SYNC_TIMEOUT 5 /* 5 secs */
66
67/* AFU command room retry limit */
68#define MC_ROOM_RETRY_CNT 10
69
70/* FC CRC clear periodic timer */
71#define MC_CRC_THRESH 100 /* threshold in 5 mins */
72
73#define FC_PORT_STATUS_RETRY_CNT 100 /* 100 100ms retries = 10 seconds */
74#define FC_PORT_STATUS_RETRY_INTERVAL_US 100000 /* microseconds */
75
76/* VPD defines */
77#define CXLFLASH_VPD_LEN 256
78#define WWPN_LEN 16
79#define WWPN_BUF_LEN (WWPN_LEN + 1)
80
81enum undo_level {
Manoj N. Kumar9526f362016-03-25 14:26:34 -050082 UNDO_NOOP = 0,
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050083 FREE_IRQ,
84 UNMAP_ONE,
85 UNMAP_TWO,
Manoj N. Kumar9526f362016-03-25 14:26:34 -050086 UNMAP_THREE
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050087};
88
89struct dev_dependent_vals {
90 u64 max_sectors;
Uma Krishnan96e1b662016-06-15 18:49:38 -050091 u64 flags;
Uma Krishnan704c4b02016-06-15 18:49:57 -050092#define CXLFLASH_NOTIFY_SHUTDOWN 0x0000000000000001ULL
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050093};
94
95struct asyc_intr_info {
96 u64 status;
97 char *desc;
98 u8 port;
99 u8 action;
100#define CLR_FC_ERROR 0x01
101#define LINK_RESET 0x02
Matthew R. Ochsef510742015-10-21 15:13:37 -0500102#define SCAN_HOST 0x04
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500103};
104
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500105#endif /* _CXLFLASH_MAIN_H */