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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * include/asm-ppc/mv64x60.h
3 *
4 * Prototypes, etc. for the Marvell/Galileo MV64x60 host bridge routines.
5 *
6 * Author: Mark A. Greer <mgreer@mvista.com>
7 *
8 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __ASMPPC_MV64x60_H
14#define __ASMPPC_MV64x60_H
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
21#include <asm/byteorder.h>
22#include <asm/io.h>
23#include <asm/irq.h>
24#include <asm/uaccess.h>
25#include <asm/machdep.h>
26#include <asm/pci-bridge.h>
27#include <asm/mv64x60_defs.h>
28
Al Virobbc5b212005-11-01 15:14:05 +000029struct platform_device;
30
Linus Torvalds1da177e2005-04-16 15:20:36 -070031extern u8 mv64x60_pci_exclude_bridge;
32
33extern spinlock_t mv64x60_lock;
34
35/* 32-bit Window table entry defines */
36#define MV64x60_CPU2MEM_0_WIN 0
37#define MV64x60_CPU2MEM_1_WIN 1
38#define MV64x60_CPU2MEM_2_WIN 2
39#define MV64x60_CPU2MEM_3_WIN 3
40#define MV64x60_CPU2DEV_0_WIN 4
41#define MV64x60_CPU2DEV_1_WIN 5
42#define MV64x60_CPU2DEV_2_WIN 6
43#define MV64x60_CPU2DEV_3_WIN 7
44#define MV64x60_CPU2BOOT_WIN 8
45#define MV64x60_CPU2PCI0_IO_WIN 9
46#define MV64x60_CPU2PCI0_MEM_0_WIN 10
47#define MV64x60_CPU2PCI0_MEM_1_WIN 11
48#define MV64x60_CPU2PCI0_MEM_2_WIN 12
49#define MV64x60_CPU2PCI0_MEM_3_WIN 13
50#define MV64x60_CPU2PCI1_IO_WIN 14
51#define MV64x60_CPU2PCI1_MEM_0_WIN 15
52#define MV64x60_CPU2PCI1_MEM_1_WIN 16
53#define MV64x60_CPU2PCI1_MEM_2_WIN 17
54#define MV64x60_CPU2PCI1_MEM_3_WIN 18
55#define MV64x60_CPU2SRAM_WIN 19
56#define MV64x60_CPU2PCI0_IO_REMAP_WIN 20
57#define MV64x60_CPU2PCI1_IO_REMAP_WIN 21
58#define MV64x60_CPU_PROT_0_WIN 22
59#define MV64x60_CPU_PROT_1_WIN 23
60#define MV64x60_CPU_PROT_2_WIN 24
61#define MV64x60_CPU_PROT_3_WIN 25
62#define MV64x60_CPU_SNOOP_0_WIN 26
63#define MV64x60_CPU_SNOOP_1_WIN 27
64#define MV64x60_CPU_SNOOP_2_WIN 28
65#define MV64x60_CPU_SNOOP_3_WIN 29
66#define MV64x60_PCI02MEM_REMAP_0_WIN 30
67#define MV64x60_PCI02MEM_REMAP_1_WIN 31
68#define MV64x60_PCI02MEM_REMAP_2_WIN 32
69#define MV64x60_PCI02MEM_REMAP_3_WIN 33
70#define MV64x60_PCI12MEM_REMAP_0_WIN 34
71#define MV64x60_PCI12MEM_REMAP_1_WIN 35
72#define MV64x60_PCI12MEM_REMAP_2_WIN 36
73#define MV64x60_PCI12MEM_REMAP_3_WIN 37
74#define MV64x60_ENET2MEM_0_WIN 38
75#define MV64x60_ENET2MEM_1_WIN 39
76#define MV64x60_ENET2MEM_2_WIN 40
77#define MV64x60_ENET2MEM_3_WIN 41
78#define MV64x60_ENET2MEM_4_WIN 42
79#define MV64x60_ENET2MEM_5_WIN 43
80#define MV64x60_MPSC2MEM_0_WIN 44
81#define MV64x60_MPSC2MEM_1_WIN 45
82#define MV64x60_MPSC2MEM_2_WIN 46
83#define MV64x60_MPSC2MEM_3_WIN 47
84#define MV64x60_IDMA2MEM_0_WIN 48
85#define MV64x60_IDMA2MEM_1_WIN 49
86#define MV64x60_IDMA2MEM_2_WIN 50
87#define MV64x60_IDMA2MEM_3_WIN 51
88#define MV64x60_IDMA2MEM_4_WIN 52
89#define MV64x60_IDMA2MEM_5_WIN 53
90#define MV64x60_IDMA2MEM_6_WIN 54
91#define MV64x60_IDMA2MEM_7_WIN 55
92
93#define MV64x60_32BIT_WIN_COUNT 56
94
95/* 64-bit Window table entry defines */
96#define MV64x60_CPU2PCI0_MEM_0_REMAP_WIN 0
97#define MV64x60_CPU2PCI0_MEM_1_REMAP_WIN 1
98#define MV64x60_CPU2PCI0_MEM_2_REMAP_WIN 2
99#define MV64x60_CPU2PCI0_MEM_3_REMAP_WIN 3
100#define MV64x60_CPU2PCI1_MEM_0_REMAP_WIN 4
101#define MV64x60_CPU2PCI1_MEM_1_REMAP_WIN 5
102#define MV64x60_CPU2PCI1_MEM_2_REMAP_WIN 6
103#define MV64x60_CPU2PCI1_MEM_3_REMAP_WIN 7
104#define MV64x60_PCI02MEM_ACC_CNTL_0_WIN 8
105#define MV64x60_PCI02MEM_ACC_CNTL_1_WIN 9
106#define MV64x60_PCI02MEM_ACC_CNTL_2_WIN 10
107#define MV64x60_PCI02MEM_ACC_CNTL_3_WIN 11
108#define MV64x60_PCI12MEM_ACC_CNTL_0_WIN 12
109#define MV64x60_PCI12MEM_ACC_CNTL_1_WIN 13
110#define MV64x60_PCI12MEM_ACC_CNTL_2_WIN 14
111#define MV64x60_PCI12MEM_ACC_CNTL_3_WIN 15
112#define MV64x60_PCI02MEM_SNOOP_0_WIN 16
113#define MV64x60_PCI02MEM_SNOOP_1_WIN 17
114#define MV64x60_PCI02MEM_SNOOP_2_WIN 18
115#define MV64x60_PCI02MEM_SNOOP_3_WIN 19
116#define MV64x60_PCI12MEM_SNOOP_0_WIN 20
117#define MV64x60_PCI12MEM_SNOOP_1_WIN 21
118#define MV64x60_PCI12MEM_SNOOP_2_WIN 22
119#define MV64x60_PCI12MEM_SNOOP_3_WIN 23
120
121#define MV64x60_64BIT_WIN_COUNT 24
122
James Chapman3be10212005-08-17 09:01:33 +0200123/* Watchdog Platform Device, Driver Data */
124#define MV64x60_WDT_NAME "wdt"
125
126struct mv64x60_wdt_pdata {
127 int timeout; /* watchdog expiry in seconds, default 10 */
128 int bus_clk; /* bus clock in MHz, default 133 */
129};
130
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131/*
132 * Define a structure that's used to pass in config information to the
133 * core routines.
134 */
135struct mv64x60_pci_window {
136 u32 cpu_base;
137 u32 pci_base_hi;
138 u32 pci_base_lo;
139 u32 size;
140 u32 swap;
141};
142
143struct mv64x60_pci_info {
144 u8 enable_bus; /* allow access to this PCI bus? */
145
146 struct mv64x60_pci_window pci_io;
147 struct mv64x60_pci_window pci_mem[3];
148
149 u32 acc_cntl_options[MV64x60_CPU2MEM_WINDOWS];
150 u32 snoop_options[MV64x60_CPU2MEM_WINDOWS];
151 u16 pci_cmd_bits;
152 u16 latency_timer;
153};
154
155struct mv64x60_setup_info {
156 u32 phys_reg_base;
157 u32 window_preserve_mask_32_hi;
158 u32 window_preserve_mask_32_lo;
159 u32 window_preserve_mask_64;
160
161 u32 cpu_prot_options[MV64x60_CPU2MEM_WINDOWS];
162 u32 cpu_snoop_options[MV64x60_CPU2MEM_WINDOWS];
163 u32 enet_options[MV64x60_CPU2MEM_WINDOWS];
164 u32 mpsc_options[MV64x60_CPU2MEM_WINDOWS];
165 u32 idma_options[MV64x60_CPU2MEM_WINDOWS];
166
167 struct mv64x60_pci_info pci_0;
168 struct mv64x60_pci_info pci_1;
169};
170
171/* Define what the top bits in the extra member of a window entry means. */
172#define MV64x60_EXTRA_INVALID 0x00000000
173#define MV64x60_EXTRA_CPUWIN_ENAB 0x10000000
174#define MV64x60_EXTRA_CPUPROT_ENAB 0x20000000
175#define MV64x60_EXTRA_ENET_ENAB 0x30000000
176#define MV64x60_EXTRA_MPSC_ENAB 0x40000000
177#define MV64x60_EXTRA_IDMA_ENAB 0x50000000
178#define MV64x60_EXTRA_PCIACC_ENAB 0x60000000
179
180#define MV64x60_EXTRA_MASK 0xf0000000
181
182/*
183 * Define the 'handle' struct that will be passed between the 64x60 core
184 * code and the platform-specific code that will use it. The handle
185 * will contain pointers to chip-specific routines & information.
186 */
187struct mv64x60_32bit_window {
188 u32 base_reg;
189 u32 size_reg;
190 u8 base_bits;
191 u8 size_bits;
192 u32 (*get_from_field)(u32 val, u32 num_bits);
193 u32 (*map_to_field)(u32 val, u32 num_bits);
194 u32 extra;
195};
196
197struct mv64x60_64bit_window {
198 u32 base_hi_reg;
199 u32 base_lo_reg;
200 u32 size_reg;
201 u8 base_lo_bits;
202 u8 size_bits;
203 u32 (*get_from_field)(u32 val, u32 num_bits);
204 u32 (*map_to_field)(u32 val, u32 num_bits);
205 u32 extra;
206};
207
208typedef struct mv64x60_handle mv64x60_handle_t;
209struct mv64x60_chip_info {
210 u32 (*translate_size)(u32 base, u32 size, u32 num_bits);
211 u32 (*untranslate_size)(u32 base, u32 size, u32 num_bits);
212 void (*set_pci2mem_window)(struct pci_controller *hose, u32 bus,
213 u32 window, u32 base);
214 void (*set_pci2regs_window)(struct mv64x60_handle *bh,
215 struct pci_controller *hose, u32 bus, u32 base);
216 u32 (*is_enabled_32bit)(mv64x60_handle_t *bh, u32 window);
217 void (*enable_window_32bit)(mv64x60_handle_t *bh, u32 window);
218 void (*disable_window_32bit)(mv64x60_handle_t *bh, u32 window);
219 void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window);
220 void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window);
221 void (*disable_all_windows)(mv64x60_handle_t *bh,
222 struct mv64x60_setup_info *si);
223 void (*config_io2mem_windows)(mv64x60_handle_t *bh,
224 struct mv64x60_setup_info *si,
225 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
226 void (*set_mpsc2regs_window)(struct mv64x60_handle *bh, u32 base);
227 void (*chip_specific_init)(mv64x60_handle_t *bh,
228 struct mv64x60_setup_info *si);
229
230 struct mv64x60_32bit_window *window_tab_32bit;
231 struct mv64x60_64bit_window *window_tab_64bit;
232};
233
234struct mv64x60_handle {
235 u32 type; /* type of bridge */
236 u32 rev; /* revision of bridge */
Al Viroa7625d62005-09-29 00:34:30 +0100237 void __iomem *v_base;/* virtual base addr of bridge regs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 phys_addr_t p_base; /* physical base addr of bridge regs */
239
240 u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/
241 u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/
242
243 u32 io_base_a; /* vaddr of pci 0's I/O space */
244 u32 io_base_b; /* vaddr of pci 1's I/O space */
245
246 struct pci_controller *hose_a;
247 struct pci_controller *hose_b;
248
249 struct mv64x60_chip_info *ci; /* chip/bridge-specific info */
250};
251
252
253/* Define I/O routines for accessing registers on the 64x60 bridge. */
254extern inline void
255mv64x60_write(struct mv64x60_handle *bh, u32 offset, u32 val) {
256 ulong flags;
257
258 spin_lock_irqsave(&mv64x60_lock, flags);
259 out_le32(bh->v_base + offset, val);
260 spin_unlock_irqrestore(&mv64x60_lock, flags);
261}
262
263extern inline u32
264mv64x60_read(struct mv64x60_handle *bh, u32 offset) {
265 ulong flags;
266 u32 reg;
267
268 spin_lock_irqsave(&mv64x60_lock, flags);
269 reg = in_le32(bh->v_base + offset);
270 spin_unlock_irqrestore(&mv64x60_lock, flags);
271 return reg;
272}
273
274extern inline void
275mv64x60_modify(struct mv64x60_handle *bh, u32 offs, u32 data, u32 mask)
276{
277 u32 reg;
278 ulong flags;
279
280 spin_lock_irqsave(&mv64x60_lock, flags);
281 reg = in_le32(bh->v_base + offs) & (~mask);
282 reg |= data & mask;
283 out_le32(bh->v_base + offs, reg);
284 spin_unlock_irqrestore(&mv64x60_lock, flags);
285}
286
287#define mv64x60_set_bits(bh, offs, bits) mv64x60_modify(bh, offs, ~0, bits)
288#define mv64x60_clr_bits(bh, offs, bits) mv64x60_modify(bh, offs, 0, bits)
289
Mark A. Greerd01c08c2005-09-03 15:55:56 -0700290#if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
291#define MV64XXX_DEV_NAME "mv64xxx"
292
293struct mv64xxx_pdata {
294 u32 hs_reg_valid;
295};
296#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297
298/* Externally visible function prototypes */
299int mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si);
300u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type);
301void mv64x60_early_init(struct mv64x60_handle *bh,
302 struct mv64x60_setup_info *si);
303void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr,
304 u32 cfg_data, struct pci_controller **hose);
305int mv64x60_get_type(struct mv64x60_handle *bh);
306int mv64x60_setup_for_chip(struct mv64x60_handle *bh);
Al Viroa7625d62005-09-29 00:34:30 +0100307void __iomem *mv64x60_get_bridge_vbase(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308u32 mv64x60_get_bridge_type(void);
309u32 mv64x60_get_bridge_rev(void);
310void mv64x60_get_mem_windows(struct mv64x60_handle *bh,
311 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
312void mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
313 struct mv64x60_setup_info *si,
314 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
315void mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
316 struct mv64x60_pci_info *pi, u32 bus);
317void mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
318 struct pci_controller *hose, struct mv64x60_pci_info *pi, u32 bus,
319 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
320void mv64x60_config_resources(struct pci_controller *hose,
321 struct mv64x60_pci_info *pi, u32 io_base);
322void mv64x60_config_pci_params(struct pci_controller *hose,
323 struct mv64x60_pci_info *pi);
324void mv64x60_pd_fixup(struct mv64x60_handle *bh,
325 struct platform_device *pd_devs[], u32 entries);
326void mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
327 u32 *base, u32 *size);
328void mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, u32 base,
329 u32 size, u32 other_bits);
330void mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
331 u32 *base_hi, u32 *base_lo, u32 *size);
332void mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
333 u32 base_hi, u32 base_lo, u32 size, u32 other_bits);
334void mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus);
335int mv64x60_pci_exclude_device(u8 bus, u8 devfn);
336
337
338void gt64260_init_irq(void);
Al Viro39e3eb72006-10-09 12:48:42 +0100339int gt64260_get_irq(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340void mv64360_init_irq(void);
Al Viro39e3eb72006-10-09 12:48:42 +0100341int mv64360_get_irq(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342
343u32 mv64x60_mask(u32 val, u32 num_bits);
344u32 mv64x60_shift_left(u32 val, u32 num_bits);
345u32 mv64x60_shift_right(u32 val, u32 num_bits);
346u32 mv64x60_calc_mem_size(struct mv64x60_handle *bh,
347 u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
348
349void mv64x60_progress_init(u32 base);
350void mv64x60_mpsc_progress(char *s, unsigned short hex);
351
352extern struct mv64x60_32bit_window
353 gt64260_32bit_windows[MV64x60_32BIT_WIN_COUNT];
354extern struct mv64x60_64bit_window
355 gt64260_64bit_windows[MV64x60_64BIT_WIN_COUNT];
356extern struct mv64x60_32bit_window
357 mv64360_32bit_windows[MV64x60_32BIT_WIN_COUNT];
358extern struct mv64x60_64bit_window
359 mv64360_64bit_windows[MV64x60_64BIT_WIN_COUNT];
360
361#endif /* __ASMPPC_MV64x60_H */