Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Cadence SPI controller driver (master mode only) |
| 3 | * |
| 4 | * Copyright (C) 2008 - 2014 Xilinx, Inc. |
| 5 | * |
| 6 | * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it under |
| 9 | * the terms of the GNU General Public License version 2 as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/clk.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/of_irq.h> |
| 20 | #include <linux/of_address.h> |
| 21 | #include <linux/platform_device.h> |
Shubhrajyoti Datta | d36ccd9 | 2016-04-05 23:37:52 +0530 | [diff] [blame^] | 22 | #include <linux/pm_runtime.h> |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 23 | #include <linux/spi/spi.h> |
| 24 | |
| 25 | /* Name of this driver */ |
| 26 | #define CDNS_SPI_NAME "cdns-spi" |
| 27 | |
| 28 | /* Register offset definitions */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 29 | #define CDNS_SPI_CR 0x00 /* Configuration Register, RW */ |
| 30 | #define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */ |
| 31 | #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */ |
| 32 | #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */ |
| 33 | #define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */ |
| 34 | #define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */ |
| 35 | #define CDNS_SPI_DR 0x18 /* Delay Register, RW */ |
| 36 | #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */ |
| 37 | #define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */ |
| 38 | #define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */ |
| 39 | #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */ |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 40 | |
Shubhrajyoti Datta | d36ccd9 | 2016-04-05 23:37:52 +0530 | [diff] [blame^] | 41 | #define SPI_AUTOSUSPEND_TIMEOUT 3000 |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 42 | /* |
| 43 | * SPI Configuration Register bit Masks |
| 44 | * |
| 45 | * This register contains various control bits that affect the operation |
| 46 | * of the SPI controller |
| 47 | */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 48 | #define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */ |
| 49 | #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */ |
| 50 | #define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */ |
| 51 | #define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */ |
| 52 | #define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */ |
| 53 | #define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */ |
| 54 | #define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */ |
| 55 | #define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */ |
| 56 | #define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */ |
| 57 | #define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */ |
| 58 | #define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \ |
| 59 | CDNS_SPI_CR_SSCTRL | \ |
| 60 | CDNS_SPI_CR_SSFORCE | \ |
| 61 | CDNS_SPI_CR_BAUD_DIV_4) |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 62 | |
| 63 | /* |
| 64 | * SPI Configuration Register - Baud rate and slave select |
| 65 | * |
| 66 | * These are the values used in the calculation of baud rate divisor and |
| 67 | * setting the slave select. |
| 68 | */ |
| 69 | |
| 70 | #define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ |
| 71 | #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */ |
| 72 | #define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ |
| 73 | #define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */ |
| 74 | #define CDNS_SPI_SS0 0x1 /* Slave Select zero */ |
| 75 | |
| 76 | /* |
| 77 | * SPI Interrupt Registers bit Masks |
| 78 | * |
| 79 | * All the four interrupt registers (Status/Mask/Enable/Disable) have the same |
| 80 | * bit definitions. |
| 81 | */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 82 | #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */ |
| 83 | #define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */ |
| 84 | #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */ |
| 85 | #define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \ |
| 86 | CDNS_SPI_IXR_MODF) |
| 87 | #define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */ |
| 88 | #define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */ |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 89 | |
| 90 | /* |
| 91 | * SPI Enable Register bit Masks |
| 92 | * |
| 93 | * This register is used to enable or disable the SPI controller |
| 94 | */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 95 | #define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */ |
| 96 | #define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */ |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 97 | |
| 98 | /* SPI FIFO depth in bytes */ |
| 99 | #define CDNS_SPI_FIFO_DEPTH 128 |
| 100 | |
| 101 | /* Default number of chip select lines */ |
| 102 | #define CDNS_SPI_DEFAULT_NUM_CS 4 |
| 103 | |
| 104 | /** |
| 105 | * struct cdns_spi - This definition defines spi driver instance |
| 106 | * @regs: Virtual address of the SPI controller registers |
| 107 | * @ref_clk: Pointer to the peripheral clock |
| 108 | * @pclk: Pointer to the APB clock |
| 109 | * @speed_hz: Current SPI bus clock speed in Hz |
| 110 | * @txbuf: Pointer to the TX buffer |
| 111 | * @rxbuf: Pointer to the RX buffer |
| 112 | * @tx_bytes: Number of bytes left to transfer |
| 113 | * @rx_bytes: Number of bytes requested |
| 114 | * @dev_busy: Device busy flag |
| 115 | * @is_decoded_cs: Flag for decoder property set or not |
| 116 | */ |
| 117 | struct cdns_spi { |
| 118 | void __iomem *regs; |
| 119 | struct clk *ref_clk; |
| 120 | struct clk *pclk; |
| 121 | u32 speed_hz; |
| 122 | const u8 *txbuf; |
| 123 | u8 *rxbuf; |
| 124 | int tx_bytes; |
| 125 | int rx_bytes; |
| 126 | u8 dev_busy; |
| 127 | u32 is_decoded_cs; |
| 128 | }; |
| 129 | |
| 130 | /* Macros for the SPI controller read/write */ |
| 131 | static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) |
| 132 | { |
| 133 | return readl_relaxed(xspi->regs + offset); |
| 134 | } |
| 135 | |
| 136 | static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val) |
| 137 | { |
| 138 | writel_relaxed(val, xspi->regs + offset); |
| 139 | } |
| 140 | |
| 141 | /** |
| 142 | * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller |
| 143 | * @xspi: Pointer to the cdns_spi structure |
| 144 | * |
| 145 | * On reset the SPI controller is configured to be in master mode, baud rate |
| 146 | * divisor is set to 4, threshold value for TX FIFO not full interrupt is set |
| 147 | * to 1 and size of the word to be transferred as 8 bit. |
| 148 | * This function initializes the SPI controller to disable and clear all the |
| 149 | * interrupts, enable manual slave select and manual start, deselect all the |
| 150 | * chip select lines, and enable the SPI controller. |
| 151 | */ |
| 152 | static void cdns_spi_init_hw(struct cdns_spi *xspi) |
| 153 | { |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 154 | u32 ctrl_reg = CDNS_SPI_CR_DEFAULT; |
Lars-Peter Clausen | ee0ebe81 | 2014-11-27 16:12:18 +0100 | [diff] [blame] | 155 | |
| 156 | if (xspi->is_decoded_cs) |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 157 | ctrl_reg |= CDNS_SPI_CR_PERI_SEL; |
Lars-Peter Clausen | ee0ebe81 | 2014-11-27 16:12:18 +0100 | [diff] [blame] | 158 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 159 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
| 160 | cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 161 | |
| 162 | /* Clear the RX FIFO */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 163 | while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY) |
| 164 | cdns_spi_read(xspi, CDNS_SPI_RXD); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 165 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 166 | cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL); |
| 167 | cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); |
| 168 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 169 | } |
| 170 | |
| 171 | /** |
| 172 | * cdns_spi_chipselect - Select or deselect the chip select line |
| 173 | * @spi: Pointer to the spi_device structure |
Shubhrajyoti Datta | b403736 | 2016-04-05 23:37:51 +0530 | [diff] [blame] | 174 | * @is_high: Select(0) or deselect (1) the chip select line |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 175 | */ |
| 176 | static void cdns_spi_chipselect(struct spi_device *spi, bool is_high) |
| 177 | { |
| 178 | struct cdns_spi *xspi = spi_master_get_devdata(spi->master); |
| 179 | u32 ctrl_reg; |
| 180 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 181 | ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 182 | |
| 183 | if (is_high) { |
| 184 | /* Deselect the slave */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 185 | ctrl_reg |= CDNS_SPI_CR_SSCTRL; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 186 | } else { |
| 187 | /* Select the slave */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 188 | ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 189 | if (!(xspi->is_decoded_cs)) |
| 190 | ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << |
| 191 | CDNS_SPI_SS_SHIFT) & |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 192 | CDNS_SPI_CR_SSCTRL; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 193 | else |
| 194 | ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 195 | CDNS_SPI_CR_SSCTRL; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 196 | } |
| 197 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 198 | cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | /** |
| 202 | * cdns_spi_config_clock_mode - Sets clock polarity and phase |
| 203 | * @spi: Pointer to the spi_device structure |
| 204 | * |
| 205 | * Sets the requested clock polarity and phase. |
| 206 | */ |
| 207 | static void cdns_spi_config_clock_mode(struct spi_device *spi) |
| 208 | { |
| 209 | struct cdns_spi *xspi = spi_master_get_devdata(spi->master); |
Lars-Peter Clausen | a39e65e | 2014-07-10 11:26:28 +0200 | [diff] [blame] | 210 | u32 ctrl_reg, new_ctrl_reg; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 211 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 212 | new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 213 | |
| 214 | /* Set the SPI clock phase and clock polarity */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 215 | new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 216 | if (spi->mode & SPI_CPHA) |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 217 | new_ctrl_reg |= CDNS_SPI_CR_CPHA; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 218 | if (spi->mode & SPI_CPOL) |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 219 | new_ctrl_reg |= CDNS_SPI_CR_CPOL; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 220 | |
Lars-Peter Clausen | a39e65e | 2014-07-10 11:26:28 +0200 | [diff] [blame] | 221 | if (new_ctrl_reg != ctrl_reg) { |
| 222 | /* |
| 223 | * Just writing the CR register does not seem to apply the clock |
| 224 | * setting changes. This is problematic when changing the clock |
| 225 | * polarity as it will cause the SPI slave to see spurious clock |
| 226 | * transitions. To workaround the issue toggle the ER register. |
| 227 | */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 228 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
| 229 | cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg); |
| 230 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); |
Lars-Peter Clausen | a39e65e | 2014-07-10 11:26:28 +0200 | [diff] [blame] | 231 | } |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 232 | } |
| 233 | |
| 234 | /** |
| 235 | * cdns_spi_config_clock_freq - Sets clock frequency |
| 236 | * @spi: Pointer to the spi_device structure |
| 237 | * @transfer: Pointer to the spi_transfer structure which provides |
| 238 | * information about next transfer setup parameters |
| 239 | * |
| 240 | * Sets the requested clock frequency. |
| 241 | * Note: If the requested frequency is not an exact match with what can be |
| 242 | * obtained using the prescalar value the driver sets the clock frequency which |
| 243 | * is lower than the requested frequency (maximum lower) for the transfer. If |
| 244 | * the requested frequency is higher or lower than that is supported by the SPI |
| 245 | * controller the driver will set the highest or lowest frequency supported by |
| 246 | * controller. |
| 247 | */ |
| 248 | static void cdns_spi_config_clock_freq(struct spi_device *spi, |
| 249 | struct spi_transfer *transfer) |
| 250 | { |
| 251 | struct cdns_spi *xspi = spi_master_get_devdata(spi->master); |
| 252 | u32 ctrl_reg, baud_rate_val; |
| 253 | unsigned long frequency; |
| 254 | |
| 255 | frequency = clk_get_rate(xspi->ref_clk); |
| 256 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 257 | ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 258 | |
| 259 | /* Set the clock frequency */ |
| 260 | if (xspi->speed_hz != transfer->speed_hz) { |
| 261 | /* first valid value is 1 */ |
| 262 | baud_rate_val = CDNS_SPI_BAUD_DIV_MIN; |
| 263 | while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) && |
| 264 | (frequency / (2 << baud_rate_val)) > transfer->speed_hz) |
| 265 | baud_rate_val++; |
| 266 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 267 | ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 268 | ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT; |
| 269 | |
| 270 | xspi->speed_hz = frequency / (2 << baud_rate_val); |
| 271 | } |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 272 | cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | /** |
| 276 | * cdns_spi_setup_transfer - Configure SPI controller for specified transfer |
| 277 | * @spi: Pointer to the spi_device structure |
| 278 | * @transfer: Pointer to the spi_transfer structure which provides |
| 279 | * information about next transfer setup parameters |
| 280 | * |
| 281 | * Sets the operational mode of SPI controller for the next SPI transfer and |
| 282 | * sets the requested clock frequency. |
| 283 | * |
| 284 | * Return: Always 0 |
| 285 | */ |
| 286 | static int cdns_spi_setup_transfer(struct spi_device *spi, |
| 287 | struct spi_transfer *transfer) |
| 288 | { |
| 289 | struct cdns_spi *xspi = spi_master_get_devdata(spi->master); |
| 290 | |
| 291 | cdns_spi_config_clock_freq(spi, transfer); |
| 292 | |
| 293 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n", |
| 294 | __func__, spi->mode, spi->bits_per_word, |
| 295 | xspi->speed_hz); |
| 296 | |
| 297 | return 0; |
| 298 | } |
| 299 | |
| 300 | /** |
| 301 | * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible |
| 302 | * @xspi: Pointer to the cdns_spi structure |
| 303 | */ |
| 304 | static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi) |
| 305 | { |
| 306 | unsigned long trans_cnt = 0; |
| 307 | |
| 308 | while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) && |
| 309 | (xspi->tx_bytes > 0)) { |
| 310 | if (xspi->txbuf) |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 311 | cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 312 | else |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 313 | cdns_spi_write(xspi, CDNS_SPI_TXD, 0); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 314 | |
| 315 | xspi->tx_bytes--; |
| 316 | trans_cnt++; |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | /** |
| 321 | * cdns_spi_irq - Interrupt service routine of the SPI controller |
| 322 | * @irq: IRQ number |
| 323 | * @dev_id: Pointer to the xspi structure |
| 324 | * |
| 325 | * This function handles TX empty and Mode Fault interrupts only. |
| 326 | * On TX empty interrupt this function reads the received data from RX FIFO and |
| 327 | * fills the TX FIFO if there is any data remaining to be transferred. |
| 328 | * On Mode Fault interrupt this function indicates that transfer is completed, |
| 329 | * the SPI subsystem will identify the error as the remaining bytes to be |
| 330 | * transferred is non-zero. |
| 331 | * |
| 332 | * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise. |
| 333 | */ |
| 334 | static irqreturn_t cdns_spi_irq(int irq, void *dev_id) |
| 335 | { |
| 336 | struct spi_master *master = dev_id; |
| 337 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
| 338 | u32 intr_status, status; |
| 339 | |
| 340 | status = IRQ_NONE; |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 341 | intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR); |
| 342 | cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 343 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 344 | if (intr_status & CDNS_SPI_IXR_MODF) { |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 345 | /* Indicate that transfer is completed, the SPI subsystem will |
| 346 | * identify the error as the remaining bytes to be |
| 347 | * transferred is non-zero |
| 348 | */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 349 | cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 350 | spi_finalize_current_transfer(master); |
| 351 | status = IRQ_HANDLED; |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 352 | } else if (intr_status & CDNS_SPI_IXR_TXOW) { |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 353 | unsigned long trans_cnt; |
| 354 | |
| 355 | trans_cnt = xspi->rx_bytes - xspi->tx_bytes; |
| 356 | |
| 357 | /* Read out the data from the RX FIFO */ |
| 358 | while (trans_cnt) { |
| 359 | u8 data; |
| 360 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 361 | data = cdns_spi_read(xspi, CDNS_SPI_RXD); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 362 | if (xspi->rxbuf) |
| 363 | *xspi->rxbuf++ = data; |
| 364 | |
| 365 | xspi->rx_bytes--; |
| 366 | trans_cnt--; |
| 367 | } |
| 368 | |
| 369 | if (xspi->tx_bytes) { |
| 370 | /* There is more data to send */ |
| 371 | cdns_spi_fill_tx_fifo(xspi); |
| 372 | } else { |
| 373 | /* Transfer is completed */ |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 374 | cdns_spi_write(xspi, CDNS_SPI_IDR, |
| 375 | CDNS_SPI_IXR_DEFAULT); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 376 | spi_finalize_current_transfer(master); |
| 377 | } |
| 378 | status = IRQ_HANDLED; |
| 379 | } |
| 380 | |
| 381 | return status; |
| 382 | } |
Lars-Peter Clausen | b48b948 | 2014-07-10 11:26:29 +0200 | [diff] [blame] | 383 | static int cdns_prepare_message(struct spi_master *master, |
| 384 | struct spi_message *msg) |
| 385 | { |
| 386 | cdns_spi_config_clock_mode(msg->spi); |
| 387 | return 0; |
| 388 | } |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 389 | |
| 390 | /** |
| 391 | * cdns_transfer_one - Initiates the SPI transfer |
| 392 | * @master: Pointer to spi_master structure |
| 393 | * @spi: Pointer to the spi_device structure |
| 394 | * @transfer: Pointer to the spi_transfer structure which provides |
| 395 | * information about next transfer parameters |
| 396 | * |
| 397 | * This function fills the TX FIFO, starts the SPI transfer and |
| 398 | * returns a positive transfer count so that core will wait for completion. |
| 399 | * |
| 400 | * Return: Number of bytes transferred in the last transfer |
| 401 | */ |
| 402 | static int cdns_transfer_one(struct spi_master *master, |
| 403 | struct spi_device *spi, |
| 404 | struct spi_transfer *transfer) |
| 405 | { |
| 406 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
| 407 | |
| 408 | xspi->txbuf = transfer->tx_buf; |
| 409 | xspi->rxbuf = transfer->rx_buf; |
| 410 | xspi->tx_bytes = transfer->len; |
| 411 | xspi->rx_bytes = transfer->len; |
| 412 | |
| 413 | cdns_spi_setup_transfer(spi, transfer); |
| 414 | |
| 415 | cdns_spi_fill_tx_fifo(xspi); |
| 416 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 417 | cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 418 | return transfer->len; |
| 419 | } |
| 420 | |
| 421 | /** |
| 422 | * cdns_prepare_transfer_hardware - Prepares hardware for transfer. |
| 423 | * @master: Pointer to the spi_master structure which provides |
| 424 | * information about the controller. |
| 425 | * |
| 426 | * This function enables SPI master controller. |
| 427 | * |
| 428 | * Return: 0 always |
| 429 | */ |
| 430 | static int cdns_prepare_transfer_hardware(struct spi_master *master) |
| 431 | { |
| 432 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
| 433 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 434 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 435 | |
| 436 | return 0; |
| 437 | } |
| 438 | |
| 439 | /** |
| 440 | * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer |
| 441 | * @master: Pointer to the spi_master structure which provides |
| 442 | * information about the controller. |
| 443 | * |
| 444 | * This function disables the SPI master controller. |
| 445 | * |
| 446 | * Return: 0 always |
| 447 | */ |
| 448 | static int cdns_unprepare_transfer_hardware(struct spi_master *master) |
| 449 | { |
| 450 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
| 451 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 452 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 453 | |
| 454 | return 0; |
| 455 | } |
| 456 | |
| 457 | /** |
| 458 | * cdns_spi_probe - Probe method for the SPI driver |
| 459 | * @pdev: Pointer to the platform_device structure |
| 460 | * |
| 461 | * This function initializes the driver data structures and the hardware. |
| 462 | * |
| 463 | * Return: 0 on success and error value on error |
| 464 | */ |
| 465 | static int cdns_spi_probe(struct platform_device *pdev) |
| 466 | { |
| 467 | int ret = 0, irq; |
| 468 | struct spi_master *master; |
| 469 | struct cdns_spi *xspi; |
| 470 | struct resource *res; |
| 471 | u32 num_cs; |
| 472 | |
| 473 | master = spi_alloc_master(&pdev->dev, sizeof(*xspi)); |
Shubhrajyoti Datta | 15a1c50 | 2016-04-05 23:37:48 +0530 | [diff] [blame] | 474 | if (!master) |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 475 | return -ENOMEM; |
| 476 | |
| 477 | xspi = spi_master_get_devdata(master); |
| 478 | master->dev.of_node = pdev->dev.of_node; |
| 479 | platform_set_drvdata(pdev, master); |
| 480 | |
| 481 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 482 | xspi->regs = devm_ioremap_resource(&pdev->dev, res); |
| 483 | if (IS_ERR(xspi->regs)) { |
| 484 | ret = PTR_ERR(xspi->regs); |
| 485 | goto remove_master; |
| 486 | } |
| 487 | |
| 488 | xspi->pclk = devm_clk_get(&pdev->dev, "pclk"); |
| 489 | if (IS_ERR(xspi->pclk)) { |
| 490 | dev_err(&pdev->dev, "pclk clock not found.\n"); |
| 491 | ret = PTR_ERR(xspi->pclk); |
| 492 | goto remove_master; |
| 493 | } |
| 494 | |
| 495 | xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk"); |
| 496 | if (IS_ERR(xspi->ref_clk)) { |
| 497 | dev_err(&pdev->dev, "ref_clk clock not found.\n"); |
| 498 | ret = PTR_ERR(xspi->ref_clk); |
| 499 | goto remove_master; |
| 500 | } |
| 501 | |
| 502 | ret = clk_prepare_enable(xspi->pclk); |
| 503 | if (ret) { |
| 504 | dev_err(&pdev->dev, "Unable to enable APB clock.\n"); |
| 505 | goto remove_master; |
| 506 | } |
| 507 | |
| 508 | ret = clk_prepare_enable(xspi->ref_clk); |
| 509 | if (ret) { |
| 510 | dev_err(&pdev->dev, "Unable to enable device clock.\n"); |
| 511 | goto clk_dis_apb; |
| 512 | } |
| 513 | |
Shubhrajyoti Datta | d36ccd9 | 2016-04-05 23:37:52 +0530 | [diff] [blame^] | 514 | pm_runtime_enable(&pdev->dev); |
| 515 | pm_runtime_use_autosuspend(&pdev->dev); |
| 516 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); |
| 517 | pm_runtime_set_active(&pdev->dev); |
| 518 | |
Paul Cercueil | 3cc2910 | 2014-11-27 16:12:17 +0100 | [diff] [blame] | 519 | ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); |
| 520 | if (ret < 0) |
| 521 | master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS; |
| 522 | else |
| 523 | master->num_chipselect = num_cs; |
| 524 | |
| 525 | ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs", |
| 526 | &xspi->is_decoded_cs); |
| 527 | if (ret < 0) |
| 528 | xspi->is_decoded_cs = 0; |
| 529 | |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 530 | /* SPI controller initializations */ |
| 531 | cdns_spi_init_hw(xspi); |
| 532 | |
Shubhrajyoti Datta | d36ccd9 | 2016-04-05 23:37:52 +0530 | [diff] [blame^] | 533 | pm_runtime_mark_last_busy(&pdev->dev); |
| 534 | pm_runtime_put_autosuspend(&pdev->dev); |
| 535 | |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 536 | irq = platform_get_irq(pdev, 0); |
| 537 | if (irq <= 0) { |
| 538 | ret = -ENXIO; |
| 539 | dev_err(&pdev->dev, "irq number is invalid\n"); |
Shubhrajyoti Datta | 50ac697 | 2016-04-05 23:37:50 +0530 | [diff] [blame] | 540 | goto clk_dis_all; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 541 | } |
| 542 | |
| 543 | ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq, |
| 544 | 0, pdev->name, master); |
| 545 | if (ret != 0) { |
| 546 | ret = -ENXIO; |
| 547 | dev_err(&pdev->dev, "request_irq failed\n"); |
Shubhrajyoti Datta | 50ac697 | 2016-04-05 23:37:50 +0530 | [diff] [blame] | 548 | goto clk_dis_all; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 549 | } |
| 550 | |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 551 | master->prepare_transfer_hardware = cdns_prepare_transfer_hardware; |
Lars-Peter Clausen | b48b948 | 2014-07-10 11:26:29 +0200 | [diff] [blame] | 552 | master->prepare_message = cdns_prepare_message; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 553 | master->transfer_one = cdns_transfer_one; |
| 554 | master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; |
| 555 | master->set_cs = cdns_spi_chipselect; |
Shubhrajyoti Datta | d36ccd9 | 2016-04-05 23:37:52 +0530 | [diff] [blame^] | 556 | master->auto_runtime_pm = true; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 557 | master->mode_bits = SPI_CPOL | SPI_CPHA; |
| 558 | |
| 559 | /* Set to default valid value */ |
| 560 | master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4; |
| 561 | xspi->speed_hz = master->max_speed_hz; |
| 562 | |
| 563 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
| 564 | |
| 565 | ret = spi_register_master(master); |
| 566 | if (ret) { |
| 567 | dev_err(&pdev->dev, "spi_register_master failed\n"); |
| 568 | goto clk_dis_all; |
| 569 | } |
| 570 | |
| 571 | return ret; |
| 572 | |
| 573 | clk_dis_all: |
Shubhrajyoti Datta | d36ccd9 | 2016-04-05 23:37:52 +0530 | [diff] [blame^] | 574 | pm_runtime_set_suspended(&pdev->dev); |
| 575 | pm_runtime_disable(&pdev->dev); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 576 | clk_disable_unprepare(xspi->ref_clk); |
| 577 | clk_dis_apb: |
| 578 | clk_disable_unprepare(xspi->pclk); |
| 579 | remove_master: |
| 580 | spi_master_put(master); |
| 581 | return ret; |
| 582 | } |
| 583 | |
| 584 | /** |
| 585 | * cdns_spi_remove - Remove method for the SPI driver |
| 586 | * @pdev: Pointer to the platform_device structure |
| 587 | * |
| 588 | * This function is called if a device is physically removed from the system or |
| 589 | * if the driver module is being unloaded. It frees all resources allocated to |
| 590 | * the device. |
| 591 | * |
| 592 | * Return: 0 on success and error value on error |
| 593 | */ |
| 594 | static int cdns_spi_remove(struct platform_device *pdev) |
| 595 | { |
| 596 | struct spi_master *master = platform_get_drvdata(pdev); |
| 597 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
| 598 | |
Shubhrajyoti Datta | 2474667 | 2016-04-05 23:37:49 +0530 | [diff] [blame] | 599 | cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 600 | |
| 601 | clk_disable_unprepare(xspi->ref_clk); |
| 602 | clk_disable_unprepare(xspi->pclk); |
Shubhrajyoti Datta | d36ccd9 | 2016-04-05 23:37:52 +0530 | [diff] [blame^] | 603 | pm_runtime_set_suspended(&pdev->dev); |
| 604 | pm_runtime_disable(&pdev->dev); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 605 | |
| 606 | spi_unregister_master(master); |
| 607 | |
| 608 | return 0; |
| 609 | } |
| 610 | |
| 611 | /** |
| 612 | * cdns_spi_suspend - Suspend method for the SPI driver |
| 613 | * @dev: Address of the platform_device structure |
| 614 | * |
| 615 | * This function disables the SPI controller and |
| 616 | * changes the driver state to "suspend" |
| 617 | * |
| 618 | * Return: Always 0 |
| 619 | */ |
| 620 | static int __maybe_unused cdns_spi_suspend(struct device *dev) |
| 621 | { |
Geliang Tang | 9033a5f | 2016-01-01 20:28:59 +0800 | [diff] [blame] | 622 | struct platform_device *pdev = to_platform_device(dev); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 623 | struct spi_master *master = platform_get_drvdata(pdev); |
| 624 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
| 625 | |
| 626 | spi_master_suspend(master); |
| 627 | |
| 628 | clk_disable_unprepare(xspi->ref_clk); |
| 629 | |
| 630 | clk_disable_unprepare(xspi->pclk); |
| 631 | |
| 632 | return 0; |
| 633 | } |
| 634 | |
| 635 | /** |
| 636 | * cdns_spi_resume - Resume method for the SPI driver |
| 637 | * @dev: Address of the platform_device structure |
| 638 | * |
| 639 | * This function changes the driver state to "ready" |
| 640 | * |
| 641 | * Return: 0 on success and error value on error |
| 642 | */ |
| 643 | static int __maybe_unused cdns_spi_resume(struct device *dev) |
| 644 | { |
Geliang Tang | 9033a5f | 2016-01-01 20:28:59 +0800 | [diff] [blame] | 645 | struct platform_device *pdev = to_platform_device(dev); |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 646 | struct spi_master *master = platform_get_drvdata(pdev); |
| 647 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
| 648 | int ret = 0; |
| 649 | |
| 650 | ret = clk_prepare_enable(xspi->pclk); |
| 651 | if (ret) { |
| 652 | dev_err(dev, "Cannot enable APB clock.\n"); |
| 653 | return ret; |
| 654 | } |
| 655 | |
| 656 | ret = clk_prepare_enable(xspi->ref_clk); |
| 657 | if (ret) { |
| 658 | dev_err(dev, "Cannot enable device clock.\n"); |
| 659 | clk_disable(xspi->pclk); |
| 660 | return ret; |
| 661 | } |
| 662 | spi_master_resume(master); |
| 663 | |
| 664 | return 0; |
| 665 | } |
| 666 | |
Shubhrajyoti Datta | d36ccd9 | 2016-04-05 23:37:52 +0530 | [diff] [blame^] | 667 | /** |
| 668 | * cdns_spi_runtime_resume - Runtime resume method for the SPI driver |
| 669 | * @dev: Address of the platform_device structure |
| 670 | * |
| 671 | * This function enables the clocks |
| 672 | * |
| 673 | * Return: 0 on success and error value on error |
| 674 | */ |
| 675 | static int cnds_runtime_resume(struct device *dev) |
| 676 | { |
| 677 | struct spi_master *master = dev_get_drvdata(dev); |
| 678 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
| 679 | int ret; |
| 680 | |
| 681 | ret = clk_prepare_enable(xspi->pclk); |
| 682 | if (ret) { |
| 683 | dev_err(dev, "Cannot enable APB clock.\n"); |
| 684 | return ret; |
| 685 | } |
| 686 | |
| 687 | ret = clk_prepare_enable(xspi->ref_clk); |
| 688 | if (ret) { |
| 689 | dev_err(dev, "Cannot enable device clock.\n"); |
| 690 | clk_disable(xspi->pclk); |
| 691 | return ret; |
| 692 | } |
| 693 | return 0; |
| 694 | } |
| 695 | |
| 696 | /** |
| 697 | * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver |
| 698 | * @dev: Address of the platform_device structure |
| 699 | * |
| 700 | * This function disables the clocks |
| 701 | * |
| 702 | * Return: Always 0 |
| 703 | */ |
| 704 | static int cnds_runtime_suspend(struct device *dev) |
| 705 | { |
| 706 | struct spi_master *master = dev_get_drvdata(dev); |
| 707 | struct cdns_spi *xspi = spi_master_get_devdata(master); |
| 708 | |
| 709 | clk_disable_unprepare(xspi->ref_clk); |
| 710 | clk_disable_unprepare(xspi->pclk); |
| 711 | |
| 712 | return 0; |
| 713 | } |
| 714 | |
| 715 | static const struct dev_pm_ops cdns_spi_dev_pm_ops = { |
| 716 | SET_RUNTIME_PM_OPS(cnds_runtime_suspend, |
| 717 | cnds_runtime_resume, NULL) |
| 718 | SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume) |
| 719 | }; |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 720 | |
Jingoo Han | f7f994a | 2014-06-03 21:01:40 +0900 | [diff] [blame] | 721 | static const struct of_device_id cdns_spi_of_match[] = { |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 722 | { .compatible = "xlnx,zynq-spi-r1p6" }, |
| 723 | { .compatible = "cdns,spi-r1p6" }, |
| 724 | { /* end of table */ } |
| 725 | }; |
| 726 | MODULE_DEVICE_TABLE(of, cdns_spi_of_match); |
| 727 | |
| 728 | /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */ |
| 729 | static struct platform_driver cdns_spi_driver = { |
| 730 | .probe = cdns_spi_probe, |
| 731 | .remove = cdns_spi_remove, |
| 732 | .driver = { |
| 733 | .name = CDNS_SPI_NAME, |
Harini Katakam | c474b38 | 2014-04-14 14:36:53 +0530 | [diff] [blame] | 734 | .of_match_table = cdns_spi_of_match, |
| 735 | .pm = &cdns_spi_dev_pm_ops, |
| 736 | }, |
| 737 | }; |
| 738 | |
| 739 | module_platform_driver(cdns_spi_driver); |
| 740 | |
| 741 | MODULE_AUTHOR("Xilinx, Inc."); |
| 742 | MODULE_DESCRIPTION("Cadence SPI driver"); |
| 743 | MODULE_LICENSE("GPL"); |