blob: b4bb1ef77ddc967d060d0de226ffb1cf80f26468 [file] [log] [blame]
Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Chris Wilson5eddb702010-09-11 13:48:45 +010028#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29
Jesse Barnes585fb112008-07-29 11:54:06 -070030/*
31 * The Bridge device's PCI config space has information about the
32 * fb aperture size and the amount of pre-reserved memory.
Daniel Vetter95375b72010-09-24 20:54:39 +020033 * This is all handled in the intel-gtt.ko module. i915.ko only
34 * cares about the vga bit for the vga rbiter.
Jesse Barnes585fb112008-07-29 11:54:06 -070035 */
36#define INTEL_GMCH_CTRL 0x52
Dave Airlie28d52042009-09-21 14:33:58 +100037#define INTEL_GMCH_VGA_DISABLE (1 << 1)
Zhenyu Wang14bc4902009-11-11 01:25:25 +080038
Jesse Barnes585fb112008-07-29 11:54:06 -070039/* PCI config space */
40
41#define HPLLCC 0xc0 /* 855 only */
Jesse Barnes652c3932009-08-17 13:31:43 -070042#define GC_CLOCK_CONTROL_MASK (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -070043#define GC_CLOCK_133_200 (0 << 0)
44#define GC_CLOCK_100_200 (1 << 0)
45#define GC_CLOCK_100_133 (2 << 0)
46#define GC_CLOCK_166_250 (3 << 0)
Jesse Barnesf97108d2010-01-29 11:27:07 -080047#define GCFGC2 0xda
Jesse Barnes585fb112008-07-29 11:54:06 -070048#define GCFGC 0xf0 /* 915+ only */
49#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
50#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
51#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
52#define GC_DISPLAY_CLOCK_MASK (7 << 4)
Jesse Barnes652c3932009-08-17 13:31:43 -070053#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
54#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
55#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
56#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
57#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
58#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
59#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
60#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
61#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
62#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
63#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
64#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
65#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
66#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
67#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
68#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
69#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -070072#define LBB 0xf4
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070073
74/* Graphics reset regs */
Kenneth Graunke0573ed42010-09-11 03:17:19 -070075#define I965_GDRST 0xc0 /* PCI config register */
76#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
Kenneth Graunkeeeccdca2010-09-11 01:24:50 -070077#define GRDOM_FULL (0<<2)
78#define GRDOM_RENDER (1<<2)
79#define GRDOM_MEDIA (3<<2)
Jesse Barnes585fb112008-07-29 11:54:06 -070080
Jesse Barnes07b7ddd2011-08-03 11:28:44 -070081#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
82#define GEN6_MBC_SNPCR_SHIFT 21
83#define GEN6_MBC_SNPCR_MASK (3<<21)
84#define GEN6_MBC_SNPCR_MAX (0<<21)
85#define GEN6_MBC_SNPCR_MED (1<<21)
86#define GEN6_MBC_SNPCR_LOW (2<<21)
87#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
88
Daniel Vetter5eb719c2012-02-09 17:15:48 +010089#define GEN6_MBCTL 0x0907c
90#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
91#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
92#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
93#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
94#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
95
Eric Anholtcff458c2010-11-18 09:31:14 +080096#define GEN6_GDRST 0x941c
97#define GEN6_GRDOM_FULL (1 << 0)
98#define GEN6_GRDOM_RENDER (1 << 1)
99#define GEN6_GRDOM_MEDIA (1 << 2)
100#define GEN6_GRDOM_BLT (1 << 3)
101
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100102/* PPGTT stuff */
103#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
104
105#define GEN6_PDE_VALID (1 << 0)
106#define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */
107/* gen6+ has bit 11-4 for physical addr bit 39-32 */
108#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
109
110#define GEN6_PTE_VALID (1 << 0)
111#define GEN6_PTE_UNCACHED (1 << 1)
112#define GEN6_PTE_CACHE_LLC (2 << 1)
113#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
114#define GEN6_PTE_CACHE_BITS (3 << 1)
115#define GEN6_PTE_GFDT (1 << 3)
116#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
117
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100118#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
119#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
120#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
121#define PP_DIR_DCLV_2G 0xffffffff
122
123#define GAM_ECOCHK 0x4090
124#define ECOCHK_SNB_BIT (1<<10)
125#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
126#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
127
Jesse Barnes585fb112008-07-29 11:54:06 -0700128/* VGA stuff */
129
130#define VGA_ST01_MDA 0x3ba
131#define VGA_ST01_CGA 0x3da
132
133#define VGA_MSR_WRITE 0x3c2
134#define VGA_MSR_READ 0x3cc
135#define VGA_MSR_MEM_EN (1<<1)
136#define VGA_MSR_CGA_MODE (1<<0)
137
138#define VGA_SR_INDEX 0x3c4
139#define VGA_SR_DATA 0x3c5
140
141#define VGA_AR_INDEX 0x3c0
142#define VGA_AR_VID_EN (1<<5)
143#define VGA_AR_DATA_WRITE 0x3c0
144#define VGA_AR_DATA_READ 0x3c1
145
146#define VGA_GR_INDEX 0x3ce
147#define VGA_GR_DATA 0x3cf
148/* GR05 */
149#define VGA_GR_MEM_READ_MODE_SHIFT 3
150#define VGA_GR_MEM_READ_MODE_PLANE 1
151/* GR06 */
152#define VGA_GR_MEM_MODE_MASK 0xc
153#define VGA_GR_MEM_MODE_SHIFT 2
154#define VGA_GR_MEM_A0000_AFFFF 0
155#define VGA_GR_MEM_A0000_BFFFF 1
156#define VGA_GR_MEM_B0000_B7FFF 2
157#define VGA_GR_MEM_B0000_BFFFF 3
158
159#define VGA_DACMASK 0x3c6
160#define VGA_DACRX 0x3c7
161#define VGA_DACWX 0x3c8
162#define VGA_DACDATA 0x3c9
163
164#define VGA_CR_INDEX_MDA 0x3b4
165#define VGA_CR_DATA_MDA 0x3b5
166#define VGA_CR_INDEX_CGA 0x3d4
167#define VGA_CR_DATA_CGA 0x3d5
168
169/*
170 * Memory interface instructions used by the kernel
171 */
172#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
173
174#define MI_NOOP MI_INSTR(0, 0)
175#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
176#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200177#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
Jesse Barnes585fb112008-07-29 11:54:06 -0700178#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
179#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
180#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
181#define MI_FLUSH MI_INSTR(0x04, 0)
182#define MI_READ_FLUSH (1 << 0)
183#define MI_EXE_FLUSH (1 << 1)
184#define MI_NO_WRITE_FLUSH (1 << 2)
185#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
186#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
Zou Nan hai1cafd342010-06-25 13:40:24 +0800187#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
Jesse Barnes585fb112008-07-29 11:54:06 -0700188#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
Jesse Barnes88271da2011-01-05 12:01:24 -0800189#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
190#define MI_SUSPEND_FLUSH_EN (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700191#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
Akshay Joshi0206e352011-08-16 15:34:10 -0400192#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
Daniel Vetter02e792f2009-09-15 22:57:34 +0200193#define MI_OVERLAY_CONTINUE (0x0<<21)
194#define MI_OVERLAY_ON (0x1<<21)
195#define MI_OVERLAY_OFF (0x2<<21)
Jesse Barnes585fb112008-07-29 11:54:06 -0700196#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500197#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700198#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500199#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800200#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
201#define MI_MM_SPACE_GTT (1<<8)
202#define MI_MM_SPACE_PHYSICAL (0<<8)
203#define MI_SAVE_EXT_STATE_EN (1<<3)
204#define MI_RESTORE_EXT_STATE_EN (1<<2)
Jesse Barnes88271da2011-01-05 12:01:24 -0800205#define MI_FORCE_RESTORE (1<<1)
Zou Nan haiaa40d6b2010-06-25 13:40:23 +0800206#define MI_RESTORE_INHIBIT (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700207#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
208#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
209#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
210#define MI_STORE_DWORD_INDEX_SHIFT 2
Daniel Vetterc6642782010-11-12 13:46:18 +0000211/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
212 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
213 * simply ignores the register load under certain conditions.
214 * - One can actually load arbitrary many arbitrary registers: Simply issue x
215 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
216 */
217#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
Chris Wilson71a77e02011-02-02 12:13:49 +0000218#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
219#define MI_INVALIDATE_TLB (1<<18)
220#define MI_INVALIDATE_BSD (1<<7)
Jesse Barnes585fb112008-07-29 11:54:06 -0700221#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
222#define MI_BATCH_NON_SECURE (1)
223#define MI_BATCH_NON_SECURE_I965 (1<<8)
224#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000225#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
226#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
227#define MI_SEMAPHORE_UPDATE (1<<21)
228#define MI_SEMAPHORE_COMPARE (1<<20)
229#define MI_SEMAPHORE_REGISTER (1<<18)
Ben Widawskyc8c99b02011-09-14 20:32:47 -0700230#define MI_SEMAPHORE_SYNC_RV (2<<16)
231#define MI_SEMAPHORE_SYNC_RB (0<<16)
232#define MI_SEMAPHORE_SYNC_VR (0<<16)
233#define MI_SEMAPHORE_SYNC_VB (2<<16)
234#define MI_SEMAPHORE_SYNC_BR (2<<16)
235#define MI_SEMAPHORE_SYNC_BV (0<<16)
236#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700237/*
238 * 3D instructions used by the kernel
239 */
240#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
241
242#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
243#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
244#define SC_UPDATE_SCISSOR (0x1<<1)
245#define SC_ENABLE_MASK (0x1<<0)
246#define SC_ENABLE (0x1<<0)
247#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
248#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
249#define SCI_YMIN_MASK (0xffff<<16)
250#define SCI_XMIN_MASK (0xffff<<0)
251#define SCI_YMAX_MASK (0xffff<<16)
252#define SCI_XMAX_MASK (0xffff<<0)
253#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
254#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
255#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
256#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
257#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
258#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
259#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
260#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
261#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
262#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
263#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
264#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
265#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
266#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
267#define BLT_DEPTH_8 (0<<24)
268#define BLT_DEPTH_16_565 (1<<24)
269#define BLT_DEPTH_16_1555 (2<<24)
270#define BLT_DEPTH_32 (3<<24)
271#define BLT_ROP_GXCOPY (0xcc<<16)
272#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
273#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
274#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
275#define ASYNC_FLIP (1<<22)
276#define DISPLAY_PLANE_A (0<<20)
277#define DISPLAY_PLANE_B (1<<20)
Kenneth Graunkefcbc34e2011-10-11 23:41:08 +0200278#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
Jesse Barnes8d315282011-10-16 10:23:31 +0200279#define PIPE_CONTROL_CS_STALL (1<<20)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200280#define PIPE_CONTROL_QW_WRITE (1<<14)
281#define PIPE_CONTROL_DEPTH_STALL (1<<13)
282#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
Jesse Barnes8d315282011-10-16 10:23:31 +0200283#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200284#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
285#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
286#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
287#define PIPE_CONTROL_NOTIFY (1<<8)
Jesse Barnes8d315282011-10-16 10:23:31 +0200288#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
289#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
290#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
Kenneth Graunke9d971b32011-10-11 23:41:09 +0200291#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
Jesse Barnes8d315282011-10-16 10:23:31 +0200292#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
Jesse Barnese552eb72010-04-21 11:39:23 -0700293#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
Jesse Barnes585fb112008-07-29 11:54:06 -0700294
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100295
296/*
297 * Reset registers
298 */
299#define DEBUG_RESET_I830 0x6070
300#define DEBUG_RESET_FULL (1<<7)
301#define DEBUG_RESET_RENDER (1<<8)
302#define DEBUG_RESET_DISPLAY (1<<9)
303
304
Jesse Barnes585fb112008-07-29 11:54:06 -0700305/*
Jesse Barnesde151cf2008-11-12 10:03:55 -0800306 * Fence registers
307 */
308#define FENCE_REG_830_0 0x2000
Eric Anholtdc529a42009-03-10 22:34:49 -0700309#define FENCE_REG_945_8 0x3000
Jesse Barnesde151cf2008-11-12 10:03:55 -0800310#define I830_FENCE_START_MASK 0x07f80000
311#define I830_FENCE_TILING_Y_SHIFT 12
Jesse Barnes0f973f22009-01-26 17:10:45 -0800312#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800313#define I830_FENCE_PITCH_SHIFT 4
314#define I830_FENCE_REG_VALID (1<<0)
Daniel Vetterc36a2a62010-04-17 15:12:03 +0200315#define I915_FENCE_MAX_PITCH_VAL 4
Eric Anholte76a16d2009-05-26 17:44:56 -0700316#define I830_FENCE_MAX_PITCH_VAL 6
Daniel Vetter8d7773a2009-03-29 14:09:41 +0200317#define I830_FENCE_MAX_SIZE_VAL (1<<8)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800318
319#define I915_FENCE_START_MASK 0x0ff00000
Jesse Barnes0f973f22009-01-26 17:10:45 -0800320#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
Jesse Barnesde151cf2008-11-12 10:03:55 -0800321
322#define FENCE_REG_965_0 0x03000
323#define I965_FENCE_PITCH_SHIFT 2
324#define I965_FENCE_TILING_Y_SHIFT 1
325#define I965_FENCE_REG_VALID (1<<0)
Daniel Vetter8d7773a2009-03-29 14:09:41 +0200326#define I965_FENCE_MAX_PITCH_VAL 0x0400
Jesse Barnesde151cf2008-11-12 10:03:55 -0800327
Eric Anholt4e901fd2009-10-26 16:44:17 -0700328#define FENCE_REG_SANDYBRIDGE_0 0x100000
329#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
330
Daniel Vetterf691e2f2012-02-02 09:58:12 +0100331/* control register for cpu gtt access */
332#define TILECTL 0x101000
333#define TILECTL_SWZCTL (1 << 0)
334#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
335#define TILECTL_BACKSNOOP_DIS (1 << 3)
336
Jesse Barnesde151cf2008-11-12 10:03:55 -0800337/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700338 * Instruction and interrupt control regs
339 */
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700340#define PGTBL_ER 0x02024
Daniel Vetter333e9fe2010-08-02 16:24:01 +0200341#define RENDER_RING_BASE 0x02000
342#define BSD_RING_BASE 0x04000
343#define GEN6_BSD_RING_BASE 0x12000
Chris Wilson549f7362010-10-19 11:19:32 +0100344#define BLT_RING_BASE 0x22000
Daniel Vetter3d281d82010-09-24 21:14:22 +0200345#define RING_TAIL(base) ((base)+0x30)
346#define RING_HEAD(base) ((base)+0x34)
347#define RING_START(base) ((base)+0x38)
348#define RING_CTL(base) ((base)+0x3c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000349#define RING_SYNC_0(base) ((base)+0x40)
350#define RING_SYNC_1(base) ((base)+0x44)
Ben Widawskyc8c99b02011-09-14 20:32:47 -0700351#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
352#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
353#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
354#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
355#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
356#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
Chris Wilson8fd26852010-12-08 18:40:43 +0000357#define RING_MAX_IDLE(base) ((base)+0x54)
Daniel Vetter3d281d82010-09-24 21:14:22 +0200358#define RING_HWS_PGA(base) ((base)+0x80)
359#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
Daniel Vetterf691e2f2012-02-02 09:58:12 +0100360#define ARB_MODE 0x04030
361#define ARB_MODE_SWIZZLE_SNB (1<<4)
362#define ARB_MODE_SWIZZLE_IVB (1<<5)
363#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x)
364#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x)
Eric Anholt45930102011-05-06 17:12:35 -0700365#define RENDER_HWS_PGA_GEN7 (0x04080)
Daniel Vetter33f3f512011-12-14 13:57:39 +0100366#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
367#define DONE_REG 0x40b0
Eric Anholt45930102011-05-06 17:12:35 -0700368#define BSD_HWS_PGA_GEN7 (0x04180)
369#define BLT_HWS_PGA_GEN7 (0x04280)
Daniel Vetter3d281d82010-09-24 21:14:22 +0200370#define RING_ACTHD(base) ((base)+0x74)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000371#define RING_NOPID(base) ((base)+0x94)
Chris Wilson0f468322011-01-04 17:35:21 +0000372#define RING_IMR(base) ((base)+0xa8)
Jesse Barnes585fb112008-07-29 11:54:06 -0700373#define TAIL_ADDR 0x001FFFF8
374#define HEAD_WRAP_COUNT 0xFFE00000
375#define HEAD_WRAP_ONE 0x00200000
376#define HEAD_ADDR 0x001FFFFC
377#define RING_NR_PAGES 0x001FF000
378#define RING_REPORT_MASK 0x00000006
379#define RING_REPORT_64K 0x00000002
380#define RING_REPORT_128K 0x00000004
381#define RING_NO_REPORT 0x00000000
382#define RING_VALID_MASK 0x00000001
383#define RING_VALID 0x00000001
384#define RING_INVALID 0x00000000
Chris Wilson4b60e5c2010-08-08 11:53:53 +0100385#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
386#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000387#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
Chris Wilson8168bd42010-11-11 17:54:52 +0000388#if 0
389#define PRB0_TAIL 0x02030
390#define PRB0_HEAD 0x02034
391#define PRB0_START 0x02038
392#define PRB0_CTL 0x0203c
Jesse Barnes585fb112008-07-29 11:54:06 -0700393#define PRB1_TAIL 0x02040 /* 915+ only */
394#define PRB1_HEAD 0x02044 /* 915+ only */
395#define PRB1_START 0x02048 /* 915+ only */
396#define PRB1_CTL 0x0204c /* 915+ only */
Chris Wilson8168bd42010-11-11 17:54:52 +0000397#endif
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700398#define IPEIR_I965 0x02064
399#define IPEHR_I965 0x02068
400#define INSTDONE_I965 0x0206c
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100401#define RING_IPEIR(base) ((base)+0x64)
402#define RING_IPEHR(base) ((base)+0x68)
403#define RING_INSTDONE(base) ((base)+0x6c)
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100404#define RING_INSTPS(base) ((base)+0x70)
405#define RING_DMA_FADD(base) ((base)+0x78)
406#define RING_INSTPM(base) ((base)+0xc0)
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700407#define INSTPS 0x02070 /* 965+ only */
408#define INSTDONE1 0x0207c /* 965+ only */
Jesse Barnes585fb112008-07-29 11:54:06 -0700409#define ACTHD_I965 0x02074
410#define HWS_PGA 0x02080
411#define HWS_ADDRESS_MASK 0xfffff000
412#define HWS_START_ADDRESS_SHIFT 4
Jesse Barnes97f5ab62009-10-08 10:16:48 -0700413#define PWRCTXA 0x2088 /* 965GM+ only */
414#define PWRCTX_EN (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700415#define IPEIR 0x02088
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700416#define IPEHR 0x0208c
417#define INSTDONE 0x02090
Jesse Barnes585fb112008-07-29 11:54:06 -0700418#define NOPID 0x02094
419#define HWSTAM 0x02098
Eric Anholt71cf39b2010-03-08 23:41:55 -0800420
Chris Wilsonf4068392010-10-27 20:36:41 +0100421#define ERROR_GEN6 0x040a0
422
Eric Anholtde6e2ea2010-11-06 14:53:32 -0700423/* GM45+ chicken bits -- debug workaround bits that may be required
424 * for various sorts of correct behavior. The top 16 bits of each are
425 * the enables for writing to the corresponding low bit.
426 */
427#define _3D_CHICKEN 0x02084
428#define _3D_CHICKEN2 0x0208c
429/* Disables pipelining of read flushes past the SF-WIZ interface.
430 * Required on all Ironlake steppings according to the B-Spec, but the
431 * particular danger of not doing so is not specified.
432 */
433# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
434#define _3D_CHICKEN3 0x02090
435
Eric Anholt71cf39b2010-03-08 23:41:55 -0800436#define MI_MODE 0x0209c
437# define VS_TIMER_DISPATCH (1 << 6)
Eric Anholtfc74d8e2012-01-19 10:50:06 -0800438# define MI_FLUSH_ENABLE (1 << 12)
Eric Anholt71cf39b2010-03-08 23:41:55 -0800439
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000440#define GFX_MODE 0x02520
Jesse Barnesb095cd02011-08-12 15:28:32 -0700441#define GFX_MODE_GEN7 0x0229c
Daniel Vetter5eb719c2012-02-09 17:15:48 +0100442#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000443#define GFX_RUN_LIST_ENABLE (1<<15)
444#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
445#define GFX_SURFACE_FAULT_ENABLE (1<<12)
446#define GFX_REPLAY_MODE (1<<11)
447#define GFX_PSMI_GRANULARITY (1<<10)
448#define GFX_PPGTT_ENABLE (1<<9)
449
Jesse Barnesb095cd02011-08-12 15:28:32 -0700450#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
451#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
452
Jesse Barnes585fb112008-07-29 11:54:06 -0700453#define SCPD0 0x0209c /* 915+ only */
454#define IER 0x020a0
455#define IIR 0x020a4
456#define IMR 0x020a8
457#define ISR 0x020ac
458#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
459#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
460#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
Jesse Barnesf97108d2010-01-29 11:27:07 -0800461#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
Jesse Barnes585fb112008-07-29 11:54:06 -0700462#define I915_HWB_OOM_INTERRUPT (1<<13)
463#define I915_SYNC_STATUS_INTERRUPT (1<<12)
464#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
465#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
466#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
467#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
468#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
469#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
470#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
471#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
472#define I915_DEBUG_INTERRUPT (1<<2)
473#define I915_USER_INTERRUPT (1<<1)
474#define I915_ASLE_INTERRUPT (1<<0)
Zou Nan haid1b851f2010-05-21 09:08:57 +0800475#define I915_BSD_USER_INTERRUPT (1<<25)
Jesse Barnes585fb112008-07-29 11:54:06 -0700476#define EIR 0x020b0
477#define EMR 0x020b4
478#define ESR 0x020b8
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700479#define GM45_ERROR_PAGE_TABLE (1<<5)
480#define GM45_ERROR_MEM_PRIV (1<<4)
481#define I915_ERROR_PAGE_TABLE (1<<4)
482#define GM45_ERROR_CP_PRIV (1<<3)
483#define I915_ERROR_MEMORY_REFRESH (1<<1)
484#define I915_ERROR_INSTRUCTION (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700485#define INSTPM 0x020c0
Li Pengee980b82010-01-27 19:01:11 +0800486#define INSTPM_SELF_EN (1<<12) /* 915GM only */
Chris Wilson8692d00e2011-02-05 10:08:21 +0000487#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
488 will not assert AGPBUSY# and will only
489 be delivered when out of C3. */
Ben Widawsky84f9f932011-12-12 19:21:58 -0800490#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
Jesse Barnes585fb112008-07-29 11:54:06 -0700491#define ACTHD 0x020c8
492#define FW_BLC 0x020d8
Chris Wilson8692d00e2011-02-05 10:08:21 +0000493#define FW_BLC2 0x020dc
Jesse Barnes585fb112008-07-29 11:54:06 -0700494#define FW_BLC_SELF 0x020e0 /* 915+ only */
Li Pengee980b82010-01-27 19:01:11 +0800495#define FW_BLC_SELF_EN_MASK (1<<31)
496#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
497#define FW_BLC_SELF_EN (1<<15) /* 945 only */
Shaohua Li7662c8b2009-06-26 11:23:55 +0800498#define MM_BURST_LENGTH 0x00700000
499#define MM_FIFO_WATERMARK 0x0001F000
500#define LM_BURST_LENGTH 0x00000700
501#define LM_FIFO_WATERMARK 0x0000001F
Jesse Barnes585fb112008-07-29 11:54:06 -0700502#define MI_ARB_STATE 0x020e4 /* 915+ only */
Keith Packard45503de2010-07-19 21:12:35 -0700503#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
504
505/* Make render/texture TLB fetches lower priorty than associated data
506 * fetches. This is not turned on by default
507 */
508#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
509
510/* Isoch request wait on GTT enable (Display A/B/C streams).
511 * Make isoch requests stall on the TLB update. May cause
512 * display underruns (test mode only)
513 */
514#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
515
516/* Block grant count for isoch requests when block count is
517 * set to a finite value.
518 */
519#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
520#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
521#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
522#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
523#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
524
525/* Enable render writes to complete in C2/C3/C4 power states.
526 * If this isn't enabled, render writes are prevented in low
527 * power states. That seems bad to me.
528 */
529#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
530
531/* This acknowledges an async flip immediately instead
532 * of waiting for 2TLB fetches.
533 */
534#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
535
536/* Enables non-sequential data reads through arbiter
537 */
Akshay Joshi0206e352011-08-16 15:34:10 -0400538#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
Keith Packard45503de2010-07-19 21:12:35 -0700539
540/* Disable FSB snooping of cacheable write cycles from binner/render
541 * command stream
542 */
543#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
544
545/* Arbiter time slice for non-isoch streams */
546#define MI_ARB_TIME_SLICE_MASK (7 << 5)
547#define MI_ARB_TIME_SLICE_1 (0 << 5)
548#define MI_ARB_TIME_SLICE_2 (1 << 5)
549#define MI_ARB_TIME_SLICE_4 (2 << 5)
550#define MI_ARB_TIME_SLICE_6 (3 << 5)
551#define MI_ARB_TIME_SLICE_8 (4 << 5)
552#define MI_ARB_TIME_SLICE_10 (5 << 5)
553#define MI_ARB_TIME_SLICE_14 (6 << 5)
554#define MI_ARB_TIME_SLICE_16 (7 << 5)
555
556/* Low priority grace period page size */
557#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
558#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
559
560/* Disable display A/B trickle feed */
561#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
562
563/* Set display plane priority */
564#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
565#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
566
Jesse Barnes585fb112008-07-29 11:54:06 -0700567#define CACHE_MODE_0 0x02120 /* 915+ only */
568#define CM0_MASK_SHIFT 16
569#define CM0_IZ_OPT_DISABLE (1<<6)
570#define CM0_ZR_OPT_DISABLE (1<<5)
571#define CM0_DEPTH_EVICT_DISABLE (1<<4)
572#define CM0_COLOR_EVICT_DISABLE (1<<3)
573#define CM0_DEPTH_WRITE_DISABLE (1<<1)
574#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
Chris Wilson9df30792010-02-18 10:24:56 +0000575#define BB_ADDR 0x02140 /* 8 bytes */
Jesse Barnes585fb112008-07-29 11:54:06 -0700576#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
Jesse Barnes1afe3e92010-03-26 10:35:20 -0700577#define ECOSKPD 0x021d0
578#define ECO_GATING_CX_ONLY (1<<3)
579#define ECO_FLIP_DONE (1<<0)
Jesse Barnes585fb112008-07-29 11:54:06 -0700580
Zhenyu Wanga1786bd2010-05-27 10:26:43 +0800581/* GEN6 interrupt control */
582#define GEN6_RENDER_HWSTAM 0x2098
583#define GEN6_RENDER_IMR 0x20a8
584#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
585#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
Nicolas Kaiser7aa69d22010-06-08 21:18:06 +0200586#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
Zhenyu Wanga1786bd2010-05-27 10:26:43 +0800587#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
588#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
589#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
590#define GEN6_RENDER_SYNC_STATUS (1 << 2)
591#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
592#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
593
594#define GEN6_BLITTER_HWSTAM 0x22098
595#define GEN6_BLITTER_IMR 0x220a8
596#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
597#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
598#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
599#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100600
Jesse Barnes4efe0702011-01-18 11:25:41 -0800601#define GEN6_BLITTER_ECOSKPD 0x221d0
602#define GEN6_BLITTER_LOCK_SHIFT 16
603#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
604
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100605#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
606#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
607#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
608#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
609#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
610
Chris Wilsonec6a8902011-06-21 18:37:59 +0100611#define GEN6_BSD_HWSTAM 0x12098
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100612#define GEN6_BSD_IMR 0x120a8
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000613#define GEN6_BSD_USER_INTERRUPT (1 << 12)
Xiang, Haihao881f47b2010-09-19 14:40:43 +0100614
615#define GEN6_BSD_RNCID 0x12198
616
617/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700618 * Framebuffer compression (915+ only)
619 */
620
621#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
622#define FBC_LL_BASE 0x03204 /* 4k page aligned */
623#define FBC_CONTROL 0x03208
624#define FBC_CTL_EN (1<<31)
625#define FBC_CTL_PERIODIC (1<<30)
626#define FBC_CTL_INTERVAL_SHIFT (16)
627#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
Priit Laes49677902010-03-02 11:37:00 +0200628#define FBC_CTL_C3_IDLE (1<<13)
Jesse Barnes585fb112008-07-29 11:54:06 -0700629#define FBC_CTL_STRIDE_SHIFT (5)
630#define FBC_CTL_FENCENO (1<<0)
631#define FBC_COMMAND 0x0320c
632#define FBC_CMD_COMPRESS (1<<0)
633#define FBC_STATUS 0x03210
634#define FBC_STAT_COMPRESSING (1<<31)
635#define FBC_STAT_COMPRESSED (1<<30)
636#define FBC_STAT_MODIFIED (1<<29)
637#define FBC_STAT_CURRENT_LINE (1<<0)
638#define FBC_CONTROL2 0x03214
639#define FBC_CTL_FENCE_DBL (0<<4)
640#define FBC_CTL_IDLE_IMM (0<<2)
641#define FBC_CTL_IDLE_FULL (1<<2)
642#define FBC_CTL_IDLE_LINE (2<<2)
643#define FBC_CTL_IDLE_DEBUG (3<<2)
644#define FBC_CTL_CPU_FENCE (1<<1)
645#define FBC_CTL_PLANEA (0<<0)
646#define FBC_CTL_PLANEB (1<<0)
647#define FBC_FENCE_OFF 0x0321b
Jesse Barnes80824002009-09-10 15:28:06 -0700648#define FBC_TAG 0x03300
Jesse Barnes585fb112008-07-29 11:54:06 -0700649
650#define FBC_LL_SIZE (1536)
651
Jesse Barnes74dff282009-09-14 15:39:40 -0700652/* Framebuffer compression for GM45+ */
653#define DPFC_CB_BASE 0x3200
654#define DPFC_CONTROL 0x3208
655#define DPFC_CTL_EN (1<<31)
656#define DPFC_CTL_PLANEA (0<<30)
657#define DPFC_CTL_PLANEB (1<<30)
658#define DPFC_CTL_FENCE_EN (1<<29)
Chris Wilson9ce9d062011-07-08 12:22:40 +0100659#define DPFC_CTL_PERSISTENT_MODE (1<<25)
Jesse Barnes74dff282009-09-14 15:39:40 -0700660#define DPFC_SR_EN (1<<10)
661#define DPFC_CTL_LIMIT_1X (0<<6)
662#define DPFC_CTL_LIMIT_2X (1<<6)
663#define DPFC_CTL_LIMIT_4X (2<<6)
664#define DPFC_RECOMP_CTL 0x320c
665#define DPFC_RECOMP_STALL_EN (1<<27)
666#define DPFC_RECOMP_STALL_WM_SHIFT (16)
667#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
668#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
669#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
670#define DPFC_STATUS 0x3210
671#define DPFC_INVAL_SEG_SHIFT (16)
672#define DPFC_INVAL_SEG_MASK (0x07ff0000)
673#define DPFC_COMP_SEG_SHIFT (0)
674#define DPFC_COMP_SEG_MASK (0x000003ff)
675#define DPFC_STATUS2 0x3214
676#define DPFC_FENCE_YOFF 0x3218
677#define DPFC_CHICKEN 0x3224
678#define DPFC_HT_MODIFY (1<<31)
679
Zhao Yakuib52eb4d2010-06-12 14:32:27 +0800680/* Framebuffer compression for Ironlake */
681#define ILK_DPFC_CB_BASE 0x43200
682#define ILK_DPFC_CONTROL 0x43208
683/* The bit 28-8 is reserved */
684#define DPFC_RESERVED (0x1FFFFF00)
685#define ILK_DPFC_RECOMP_CTL 0x4320c
686#define ILK_DPFC_STATUS 0x43210
687#define ILK_DPFC_FENCE_YOFF 0x43218
688#define ILK_DPFC_CHICKEN 0x43224
689#define ILK_FBC_RT_BASE 0x2128
690#define ILK_FBC_RT_VALID (1<<0)
691
692#define ILK_DISPLAY_CHICKEN1 0x42000
693#define ILK_FBCQ_DIS (1<<22)
Akshay Joshi0206e352011-08-16 15:34:10 -0400694#define ILK_PABSTRETCH_DIS (1<<21)
Yuanhan Liu13982612010-12-15 15:42:31 +0800695
Zhao Yakuib52eb4d2010-06-12 14:32:27 +0800696
Jesse Barnes585fb112008-07-29 11:54:06 -0700697/*
Yuanhan Liu9c04f012010-12-15 15:42:32 +0800698 * Framebuffer compression for Sandybridge
699 *
700 * The following two registers are of type GTTMMADR
701 */
702#define SNB_DPFC_CTL_SA 0x100100
703#define SNB_CPU_FENCE_ENABLE (1<<29)
704#define DPFC_CPU_FENCE_OFFSET 0x100104
705
706
707/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700708 * GPIO regs
709 */
710#define GPIOA 0x5010
711#define GPIOB 0x5014
712#define GPIOC 0x5018
713#define GPIOD 0x501c
714#define GPIOE 0x5020
715#define GPIOF 0x5024
716#define GPIOG 0x5028
717#define GPIOH 0x502c
718# define GPIO_CLOCK_DIR_MASK (1 << 0)
719# define GPIO_CLOCK_DIR_IN (0 << 1)
720# define GPIO_CLOCK_DIR_OUT (1 << 1)
721# define GPIO_CLOCK_VAL_MASK (1 << 2)
722# define GPIO_CLOCK_VAL_OUT (1 << 3)
723# define GPIO_CLOCK_VAL_IN (1 << 4)
724# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
725# define GPIO_DATA_DIR_MASK (1 << 8)
726# define GPIO_DATA_DIR_IN (0 << 9)
727# define GPIO_DATA_DIR_OUT (1 << 9)
728# define GPIO_DATA_VAL_MASK (1 << 10)
729# define GPIO_DATA_VAL_OUT (1 << 11)
730# define GPIO_DATA_VAL_IN (1 << 12)
731# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
732
Chris Wilsonf899fc62010-07-20 15:44:45 -0700733#define GMBUS0 0x5100 /* clock/port select */
734#define GMBUS_RATE_100KHZ (0<<8)
735#define GMBUS_RATE_50KHZ (1<<8)
736#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
737#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
738#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
739#define GMBUS_PORT_DISABLED 0
740#define GMBUS_PORT_SSC 1
741#define GMBUS_PORT_VGADDC 2
742#define GMBUS_PORT_PANEL 3
743#define GMBUS_PORT_DPC 4 /* HDMIC */
744#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
745 /* 6 reserved */
746#define GMBUS_PORT_DPD 7 /* HDMID */
747#define GMBUS_NUM_PORTS 8
748#define GMBUS1 0x5104 /* command/status */
749#define GMBUS_SW_CLR_INT (1<<31)
750#define GMBUS_SW_RDY (1<<30)
751#define GMBUS_ENT (1<<29) /* enable timeout */
752#define GMBUS_CYCLE_NONE (0<<25)
753#define GMBUS_CYCLE_WAIT (1<<25)
754#define GMBUS_CYCLE_INDEX (2<<25)
755#define GMBUS_CYCLE_STOP (4<<25)
756#define GMBUS_BYTE_COUNT_SHIFT 16
757#define GMBUS_SLAVE_INDEX_SHIFT 8
758#define GMBUS_SLAVE_ADDR_SHIFT 1
759#define GMBUS_SLAVE_READ (1<<0)
760#define GMBUS_SLAVE_WRITE (0<<0)
761#define GMBUS2 0x5108 /* status */
762#define GMBUS_INUSE (1<<15)
763#define GMBUS_HW_WAIT_PHASE (1<<14)
764#define GMBUS_STALL_TIMEOUT (1<<13)
765#define GMBUS_INT (1<<12)
766#define GMBUS_HW_RDY (1<<11)
767#define GMBUS_SATOER (1<<10)
768#define GMBUS_ACTIVE (1<<9)
769#define GMBUS3 0x510c /* data buffer bytes 3-0 */
770#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
771#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
772#define GMBUS_NAK_EN (1<<3)
773#define GMBUS_IDLE_EN (1<<2)
774#define GMBUS_HW_WAIT_EN (1<<1)
775#define GMBUS_HW_RDY_EN (1<<0)
776#define GMBUS5 0x5120 /* byte index */
777#define GMBUS_2BYTE_INDEX_EN (1<<31)
Eric Anholtf0217c42009-12-01 11:56:30 -0800778
Jesse Barnes585fb112008-07-29 11:54:06 -0700779/*
780 * Clock control & power management
781 */
782
783#define VGA0 0x6000
784#define VGA1 0x6004
785#define VGA_PD 0x6010
786#define VGA0_PD_P2_DIV_4 (1 << 7)
787#define VGA0_PD_P1_DIV_2 (1 << 5)
788#define VGA0_PD_P1_SHIFT 0
789#define VGA0_PD_P1_MASK (0x1f << 0)
790#define VGA1_PD_P2_DIV_4 (1 << 15)
791#define VGA1_PD_P1_DIV_2 (1 << 13)
792#define VGA1_PD_P1_SHIFT 8
793#define VGA1_PD_P1_MASK (0x1f << 8)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800794#define _DPLL_A 0x06014
795#define _DPLL_B 0x06018
796#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
Jesse Barnes585fb112008-07-29 11:54:06 -0700797#define DPLL_VCO_ENABLE (1 << 31)
798#define DPLL_DVO_HIGH_SPEED (1 << 30)
799#define DPLL_SYNCLOCK_ENABLE (1 << 29)
800#define DPLL_VGA_MODE_DIS (1 << 28)
801#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
802#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
803#define DPLL_MODE_MASK (3 << 26)
804#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
805#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
806#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
807#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
808#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
809#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500810#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
Jesse Barnes585fb112008-07-29 11:54:06 -0700811
Jesse Barnes585fb112008-07-29 11:54:06 -0700812#define SRX_INDEX 0x3c4
813#define SRX_DATA 0x3c5
814#define SR01 1
815#define SR01_SCREEN_OFF (1<<5)
816
817#define PPCR 0x61204
818#define PPCR_ON (1<<0)
819
820#define DVOB 0x61140
821#define DVOB_ON (1<<31)
822#define DVOC 0x61160
823#define DVOC_ON (1<<31)
824#define LVDS 0x61180
825#define LVDS_ON (1<<31)
826
Jesse Barnes585fb112008-07-29 11:54:06 -0700827/* Scratch pad debug 0 reg:
828 */
829#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
830/*
831 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
832 * this field (only one bit may be set).
833 */
834#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
835#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500836#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
Jesse Barnes585fb112008-07-29 11:54:06 -0700837/* i830, required in DVO non-gang */
838#define PLL_P2_DIVIDE_BY_4 (1 << 23)
839#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
840#define PLL_REF_INPUT_DREFCLK (0 << 13)
841#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
842#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
843#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
844#define PLL_REF_INPUT_MASK (3 << 13)
845#define PLL_LOAD_PULSE_PHASE_SHIFT 9
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500846/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +0800847# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
848# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
849# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
850# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
851# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
852
Jesse Barnes585fb112008-07-29 11:54:06 -0700853/*
854 * Parallel to Serial Load Pulse phase selection.
855 * Selects the phase for the 10X DPLL clock for the PCIe
856 * digital display port. The range is 4 to 13; 10 or more
857 * is just a flip delay. The default is 6
858 */
859#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
860#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
861/*
862 * SDVO multiplier for 945G/GM. Not used on 965.
863 */
864#define SDVO_MULTIPLIER_MASK 0x000000ff
865#define SDVO_MULTIPLIER_SHIFT_HIRES 4
866#define SDVO_MULTIPLIER_SHIFT_VGA 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800867#define _DPLL_A_MD 0x0601c /* 965+ only */
Jesse Barnes585fb112008-07-29 11:54:06 -0700868/*
869 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
870 *
871 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
872 */
873#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
874#define DPLL_MD_UDI_DIVIDER_SHIFT 24
875/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
876#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
877#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
878/*
879 * SDVO/UDI pixel multiplier.
880 *
881 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
882 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
883 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
884 * dummy bytes in the datastream at an increased clock rate, with both sides of
885 * the link knowing how many bytes are fill.
886 *
887 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
888 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
889 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
890 * through an SDVO command.
891 *
892 * This register field has values of multiplication factor minus 1, with
893 * a maximum multiplier of 5 for SDVO.
894 */
895#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
896#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
897/*
898 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
899 * This best be set to the default value (3) or the CRT won't work. No,
900 * I don't entirely understand what this does...
901 */
902#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
903#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800904#define _DPLL_B_MD 0x06020 /* 965+ only */
905#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
906#define _FPA0 0x06040
907#define _FPA1 0x06044
908#define _FPB0 0x06048
909#define _FPB1 0x0604c
910#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
911#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
Jesse Barnes585fb112008-07-29 11:54:06 -0700912#define FP_N_DIV_MASK 0x003f0000
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500913#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
Jesse Barnes585fb112008-07-29 11:54:06 -0700914#define FP_N_DIV_SHIFT 16
915#define FP_M1_DIV_MASK 0x00003f00
916#define FP_M1_DIV_SHIFT 8
917#define FP_M2_DIV_MASK 0x0000003f
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500918#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
Jesse Barnes585fb112008-07-29 11:54:06 -0700919#define FP_M2_DIV_SHIFT 0
920#define DPLL_TEST 0x606c
921#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
922#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
923#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
924#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
925#define DPLLB_TEST_N_BYPASS (1 << 19)
926#define DPLLB_TEST_M_BYPASS (1 << 18)
927#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
928#define DPLLA_TEST_N_BYPASS (1 << 3)
929#define DPLLA_TEST_M_BYPASS (1 << 2)
930#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
931#define D_STATE 0x6104
Chris Wilsondc96e9b2010-10-01 12:05:06 +0100932#define DSTATE_GFX_RESET_I830 (1<<6)
Jesse Barnes652c3932009-08-17 13:31:43 -0700933#define DSTATE_PLL_D3_OFF (1<<3)
934#define DSTATE_GFX_CLOCK_GATING (1<<1)
935#define DSTATE_DOT_CLOCK_GATING (1<<0)
936#define DSPCLK_GATE_D 0x6200
937# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
938# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
939# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
940# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
941# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
942# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
943# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
944# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
945# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
946# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
947# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
948# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
949# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
950# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
951# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
952# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
953# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
954# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
955# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
956# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
957# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
958# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
959# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
960# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
961# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
962# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
963# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
964# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
965/**
966 * This bit must be set on the 830 to prevent hangs when turning off the
967 * overlay scaler.
968 */
969# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
970# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
971# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
972# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
973# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
974
975#define RENCLK_GATE_D1 0x6204
976# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
977# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
978# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
979# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
980# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
981# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
982# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
983# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
984# define MAG_CLOCK_GATE_DISABLE (1 << 5)
985/** This bit must be unset on 855,865 */
986# define MECI_CLOCK_GATE_DISABLE (1 << 4)
987# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
988# define MEC_CLOCK_GATE_DISABLE (1 << 2)
989# define MECO_CLOCK_GATE_DISABLE (1 << 1)
990/** This bit must be set on 855,865. */
991# define SV_CLOCK_GATE_DISABLE (1 << 0)
992# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
993# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
994# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
995# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
996# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
997# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
998# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
999# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1000# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1001# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1002# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1003# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1004# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1005# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1006# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1007# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1008# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1009
1010# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1011/** This bit must always be set on 965G/965GM */
1012# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1013# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1014# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1015# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1016# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1017# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1018/** This bit must always be set on 965G */
1019# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1020# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1021# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1022# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1023# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1024# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1025# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1026# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1027# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1028# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1029# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1030# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1031# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1032# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1033# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1034# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1035# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1036# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1037# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1038
1039#define RENCLK_GATE_D2 0x6208
1040#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1041#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1042#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1043#define RAMCLK_GATE_D 0x6210 /* CRL only */
1044#define DEUC 0x6214 /* CRL only */
Jesse Barnes585fb112008-07-29 11:54:06 -07001045
1046/*
1047 * Palette regs
1048 */
1049
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001050#define _PALETTE_A 0x0a000
1051#define _PALETTE_B 0x0a800
1052#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
Jesse Barnes585fb112008-07-29 11:54:06 -07001053
Eric Anholt673a3942008-07-30 12:06:12 -07001054/* MCH MMIO space */
1055
1056/*
1057 * MCHBAR mirror.
1058 *
1059 * This mirrors the MCHBAR MMIO space whose location is determined by
1060 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1061 * every way. It is not accessible from the CP register read instructions.
1062 *
1063 */
1064#define MCHBAR_MIRROR_BASE 0x10000
1065
Yuanhan Liu13982612010-12-15 15:42:31 +08001066#define MCHBAR_MIRROR_BASE_SNB 0x140000
1067
Eric Anholt673a3942008-07-30 12:06:12 -07001068/** 915-945 and GM965 MCH register controlling DRAM channel access */
1069#define DCC 0x10200
1070#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1071#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1072#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1073#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1074#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -08001075#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Eric Anholt673a3942008-07-30 12:06:12 -07001076
Li Peng95534262010-05-18 18:58:44 +08001077/** Pineview MCH register contains DDR3 setting */
1078#define CSHRDDR3CTL 0x101a8
1079#define CSHRDDR3CTL_DDR3 (1 << 2)
1080
Eric Anholt673a3942008-07-30 12:06:12 -07001081/** 965 MCH register controlling DRAM channel configuration */
1082#define C0DRB3 0x10206
1083#define C1DRB3 0x10606
1084
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001085/** snb MCH registers for reading the DRAM channel configuration */
1086#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1087#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1088#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1089#define MAD_DIMM_ECC_MASK (0x3 << 24)
1090#define MAD_DIMM_ECC_OFF (0x0 << 24)
1091#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1092#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1093#define MAD_DIMM_ECC_ON (0x3 << 24)
1094#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1095#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1096#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1097#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1098#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1099#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1100#define MAD_DIMM_A_SELECT (0x1 << 16)
1101/* DIMM sizes are in multiples of 256mb. */
1102#define MAD_DIMM_B_SIZE_SHIFT 8
1103#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1104#define MAD_DIMM_A_SIZE_SHIFT 0
1105#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1106
1107
Keith Packardb11248d2009-06-11 22:28:56 -07001108/* Clocking configuration register */
1109#define CLKCFG 0x10c00
Shaohua Li7662c8b2009-06-26 11:23:55 +08001110#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
Keith Packardb11248d2009-06-11 22:28:56 -07001111#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1112#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1113#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1114#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1115#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001116/* Note, below two are guess */
Keith Packardb11248d2009-06-11 22:28:56 -07001117#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08001118#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
Keith Packardb11248d2009-06-11 22:28:56 -07001119#define CLKCFG_FSB_MASK (7 << 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08001120#define CLKCFG_MEM_533 (1 << 4)
1121#define CLKCFG_MEM_667 (2 << 4)
1122#define CLKCFG_MEM_800 (3 << 4)
1123#define CLKCFG_MEM_MASK (7 << 4)
1124
Jesse Barnesea056c12010-09-10 10:02:13 -07001125#define TSC1 0x11001
1126#define TSE (1<<0)
Jesse Barnes7648fa92010-05-20 14:28:11 -07001127#define TR1 0x11006
1128#define TSFS 0x11020
1129#define TSFS_SLOPE_MASK 0x0000ff00
1130#define TSFS_SLOPE_SHIFT 8
1131#define TSFS_INTR_MASK 0x000000ff
1132
Jesse Barnesf97108d2010-01-29 11:27:07 -08001133#define CRSTANDVID 0x11100
1134#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1135#define PXVFREQ_PX_MASK 0x7f000000
1136#define PXVFREQ_PX_SHIFT 24
1137#define VIDFREQ_BASE 0x11110
1138#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1139#define VIDFREQ2 0x11114
1140#define VIDFREQ3 0x11118
1141#define VIDFREQ4 0x1111c
1142#define VIDFREQ_P0_MASK 0x1f000000
1143#define VIDFREQ_P0_SHIFT 24
1144#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1145#define VIDFREQ_P0_CSCLK_SHIFT 20
1146#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1147#define VIDFREQ_P0_CRCLK_SHIFT 16
1148#define VIDFREQ_P1_MASK 0x00001f00
1149#define VIDFREQ_P1_SHIFT 8
1150#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1151#define VIDFREQ_P1_CSCLK_SHIFT 4
1152#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1153#define INTTOEXT_BASE_ILK 0x11300
1154#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1155#define INTTOEXT_MAP3_SHIFT 24
1156#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1157#define INTTOEXT_MAP2_SHIFT 16
1158#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1159#define INTTOEXT_MAP1_SHIFT 8
1160#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1161#define INTTOEXT_MAP0_SHIFT 0
1162#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1163#define MEMSWCTL 0x11170 /* Ironlake only */
1164#define MEMCTL_CMD_MASK 0xe000
1165#define MEMCTL_CMD_SHIFT 13
1166#define MEMCTL_CMD_RCLK_OFF 0
1167#define MEMCTL_CMD_RCLK_ON 1
1168#define MEMCTL_CMD_CHFREQ 2
1169#define MEMCTL_CMD_CHVID 3
1170#define MEMCTL_CMD_VMMOFF 4
1171#define MEMCTL_CMD_VMMON 5
1172#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1173 when command complete */
1174#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1175#define MEMCTL_FREQ_SHIFT 8
1176#define MEMCTL_SFCAVM (1<<7)
1177#define MEMCTL_TGT_VID_MASK 0x007f
1178#define MEMIHYST 0x1117c
1179#define MEMINTREN 0x11180 /* 16 bits */
1180#define MEMINT_RSEXIT_EN (1<<8)
1181#define MEMINT_CX_SUPR_EN (1<<7)
1182#define MEMINT_CONT_BUSY_EN (1<<6)
1183#define MEMINT_AVG_BUSY_EN (1<<5)
1184#define MEMINT_EVAL_CHG_EN (1<<4)
1185#define MEMINT_MON_IDLE_EN (1<<3)
1186#define MEMINT_UP_EVAL_EN (1<<2)
1187#define MEMINT_DOWN_EVAL_EN (1<<1)
1188#define MEMINT_SW_CMD_EN (1<<0)
1189#define MEMINTRSTR 0x11182 /* 16 bits */
1190#define MEM_RSEXIT_MASK 0xc000
1191#define MEM_RSEXIT_SHIFT 14
1192#define MEM_CONT_BUSY_MASK 0x3000
1193#define MEM_CONT_BUSY_SHIFT 12
1194#define MEM_AVG_BUSY_MASK 0x0c00
1195#define MEM_AVG_BUSY_SHIFT 10
1196#define MEM_EVAL_CHG_MASK 0x0300
1197#define MEM_EVAL_BUSY_SHIFT 8
1198#define MEM_MON_IDLE_MASK 0x00c0
1199#define MEM_MON_IDLE_SHIFT 6
1200#define MEM_UP_EVAL_MASK 0x0030
1201#define MEM_UP_EVAL_SHIFT 4
1202#define MEM_DOWN_EVAL_MASK 0x000c
1203#define MEM_DOWN_EVAL_SHIFT 2
1204#define MEM_SW_CMD_MASK 0x0003
1205#define MEM_INT_STEER_GFX 0
1206#define MEM_INT_STEER_CMR 1
1207#define MEM_INT_STEER_SMI 2
1208#define MEM_INT_STEER_SCI 3
1209#define MEMINTRSTS 0x11184
1210#define MEMINT_RSEXIT (1<<7)
1211#define MEMINT_CONT_BUSY (1<<6)
1212#define MEMINT_AVG_BUSY (1<<5)
1213#define MEMINT_EVAL_CHG (1<<4)
1214#define MEMINT_MON_IDLE (1<<3)
1215#define MEMINT_UP_EVAL (1<<2)
1216#define MEMINT_DOWN_EVAL (1<<1)
1217#define MEMINT_SW_CMD (1<<0)
1218#define MEMMODECTL 0x11190
1219#define MEMMODE_BOOST_EN (1<<31)
1220#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1221#define MEMMODE_BOOST_FREQ_SHIFT 24
1222#define MEMMODE_IDLE_MODE_MASK 0x00030000
1223#define MEMMODE_IDLE_MODE_SHIFT 16
1224#define MEMMODE_IDLE_MODE_EVAL 0
1225#define MEMMODE_IDLE_MODE_CONT 1
1226#define MEMMODE_HWIDLE_EN (1<<15)
1227#define MEMMODE_SWMODE_EN (1<<14)
1228#define MEMMODE_RCLK_GATE (1<<13)
1229#define MEMMODE_HW_UPDATE (1<<12)
1230#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1231#define MEMMODE_FSTART_SHIFT 8
1232#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1233#define MEMMODE_FMAX_SHIFT 4
1234#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1235#define RCBMAXAVG 0x1119c
1236#define MEMSWCTL2 0x1119e /* Cantiga only */
1237#define SWMEMCMD_RENDER_OFF (0 << 13)
1238#define SWMEMCMD_RENDER_ON (1 << 13)
1239#define SWMEMCMD_SWFREQ (2 << 13)
1240#define SWMEMCMD_TARVID (3 << 13)
1241#define SWMEMCMD_VRM_OFF (4 << 13)
1242#define SWMEMCMD_VRM_ON (5 << 13)
1243#define CMDSTS (1<<12)
1244#define SFCAVM (1<<11)
1245#define SWFREQ_MASK 0x0380 /* P0-7 */
1246#define SWFREQ_SHIFT 7
1247#define TARVID_MASK 0x001f
1248#define MEMSTAT_CTG 0x111a0
1249#define RCBMINAVG 0x111a0
1250#define RCUPEI 0x111b0
1251#define RCDNEI 0x111b4
Jesse Barnes88271da2011-01-05 12:01:24 -08001252#define RSTDBYCTL 0x111b8
1253#define RS1EN (1<<31)
1254#define RS2EN (1<<30)
1255#define RS3EN (1<<29)
1256#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1257#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1258#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1259#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1260#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1261#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1262#define RSX_STATUS_MASK (7<<20)
1263#define RSX_STATUS_ON (0<<20)
1264#define RSX_STATUS_RC1 (1<<20)
1265#define RSX_STATUS_RC1E (2<<20)
1266#define RSX_STATUS_RS1 (3<<20)
1267#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1268#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1269#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1270#define RSX_STATUS_RSVD2 (7<<20)
1271#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1272#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1273#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1274#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1275#define RS1CONTSAV_MASK (3<<14)
1276#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1277#define RS1CONTSAV_RSVD (1<<14)
1278#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1279#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1280#define NORMSLEXLAT_MASK (3<<12)
1281#define SLOW_RS123 (0<<12)
1282#define SLOW_RS23 (1<<12)
1283#define SLOW_RS3 (2<<12)
1284#define NORMAL_RS123 (3<<12)
1285#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1286#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1287#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1288#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1289#define RS_CSTATE_MASK (3<<4)
1290#define RS_CSTATE_C367_RS1 (0<<4)
1291#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1292#define RS_CSTATE_RSVD (2<<4)
1293#define RS_CSTATE_C367_RS2 (3<<4)
1294#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1295#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
Jesse Barnesf97108d2010-01-29 11:27:07 -08001296#define VIDCTL 0x111c0
1297#define VIDSTS 0x111c8
1298#define VIDSTART 0x111cc /* 8 bits */
1299#define MEMSTAT_ILK 0x111f8
1300#define MEMSTAT_VID_MASK 0x7f00
1301#define MEMSTAT_VID_SHIFT 8
1302#define MEMSTAT_PSTATE_MASK 0x00f8
1303#define MEMSTAT_PSTATE_SHIFT 3
1304#define MEMSTAT_MON_ACTV (1<<2)
1305#define MEMSTAT_SRC_CTL_MASK 0x0003
1306#define MEMSTAT_SRC_CTL_CORE 0
1307#define MEMSTAT_SRC_CTL_TRB 1
1308#define MEMSTAT_SRC_CTL_THM 2
1309#define MEMSTAT_SRC_CTL_STDBY 3
1310#define RCPREVBSYTUPAVG 0x113b8
1311#define RCPREVBSYTDNAVG 0x113bc
Jesse Barnesea056c12010-09-10 10:02:13 -07001312#define PMMISC 0x11214
1313#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
Jesse Barnes7648fa92010-05-20 14:28:11 -07001314#define SDEW 0x1124c
1315#define CSIEW0 0x11250
1316#define CSIEW1 0x11254
1317#define CSIEW2 0x11258
1318#define PEW 0x1125c
1319#define DEW 0x11270
1320#define MCHAFE 0x112c0
1321#define CSIEC 0x112e0
1322#define DMIEC 0x112e4
1323#define DDREC 0x112e8
1324#define PEG0EC 0x112ec
1325#define PEG1EC 0x112f0
1326#define GFXEC 0x112f4
1327#define RPPREVBSYTUPAVG 0x113b8
1328#define RPPREVBSYTDNAVG 0x113bc
1329#define ECR 0x11600
1330#define ECR_GPFE (1<<31)
1331#define ECR_IMONE (1<<30)
1332#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1333#define OGW0 0x11608
1334#define OGW1 0x1160c
1335#define EG0 0x11610
1336#define EG1 0x11614
1337#define EG2 0x11618
1338#define EG3 0x1161c
1339#define EG4 0x11620
1340#define EG5 0x11624
1341#define EG6 0x11628
1342#define EG7 0x1162c
1343#define PXW 0x11664
1344#define PXWL 0x11680
1345#define LCFUSE02 0x116c0
1346#define LCFUSE_HIV_MASK 0x000000ff
1347#define CSIPLL0 0x12c10
1348#define DDRMPLL1 0X12c20
Eric Anholt7d573822009-01-02 13:33:00 -08001349#define PEG_BAND_GAP_DATA 0x14d68
1350
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001351#define GEN6_GT_PERF_STATUS 0x145948
1352#define GEN6_RP_STATE_LIMITS 0x145994
1353#define GEN6_RP_STATE_CAP 0x145998
1354
Jesse Barnes585fb112008-07-29 11:54:06 -07001355/*
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08001356 * Logical Context regs
1357 */
1358#define CCID 0x2180
1359#define CCID_EN (1<<0)
1360/*
Jesse Barnes585fb112008-07-29 11:54:06 -07001361 * Overlay regs
1362 */
1363
1364#define OVADD 0x30000
1365#define DOVSTA 0x30008
1366#define OC_BUF (0x3<<20)
1367#define OGAMC5 0x30010
1368#define OGAMC4 0x30014
1369#define OGAMC3 0x30018
1370#define OGAMC2 0x3001c
1371#define OGAMC1 0x30020
1372#define OGAMC0 0x30024
1373
1374/*
1375 * Display engine regs
1376 */
1377
1378/* Pipe A timing regs */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001379#define _HTOTAL_A 0x60000
1380#define _HBLANK_A 0x60004
1381#define _HSYNC_A 0x60008
1382#define _VTOTAL_A 0x6000c
1383#define _VBLANK_A 0x60010
1384#define _VSYNC_A 0x60014
1385#define _PIPEASRC 0x6001c
1386#define _BCLRPAT_A 0x60020
Daniel Vetter0529a0d2012-01-28 14:49:24 +01001387#define _VSYNCSHIFT_A 0x60028
Jesse Barnes585fb112008-07-29 11:54:06 -07001388
1389/* Pipe B timing regs */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001390#define _HTOTAL_B 0x61000
1391#define _HBLANK_B 0x61004
1392#define _HSYNC_B 0x61008
1393#define _VTOTAL_B 0x6100c
1394#define _VBLANK_B 0x61010
1395#define _VSYNC_B 0x61014
1396#define _PIPEBSRC 0x6101c
1397#define _BCLRPAT_B 0x61020
Daniel Vetter0529a0d2012-01-28 14:49:24 +01001398#define _VSYNCSHIFT_B 0x61028
1399
Jesse Barnes585fb112008-07-29 11:54:06 -07001400
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001401#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1402#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1403#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1404#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1405#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1406#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1407#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
Daniel Vetter0529a0d2012-01-28 14:49:24 +01001408#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01001409
Jesse Barnes585fb112008-07-29 11:54:06 -07001410/* VGA port control */
1411#define ADPA 0x61100
1412#define ADPA_DAC_ENABLE (1<<31)
1413#define ADPA_DAC_DISABLE 0
1414#define ADPA_PIPE_SELECT_MASK (1<<30)
1415#define ADPA_PIPE_A_SELECT 0
1416#define ADPA_PIPE_B_SELECT (1<<30)
Keith Packard1519b992011-08-06 10:35:34 -07001417#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -07001418#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1419#define ADPA_SETS_HVPOLARITY 0
1420#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1421#define ADPA_VSYNC_CNTL_ENABLE 0
1422#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1423#define ADPA_HSYNC_CNTL_ENABLE 0
1424#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1425#define ADPA_VSYNC_ACTIVE_LOW 0
1426#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1427#define ADPA_HSYNC_ACTIVE_LOW 0
1428#define ADPA_DPMS_MASK (~(3<<10))
1429#define ADPA_DPMS_ON (0<<10)
1430#define ADPA_DPMS_SUSPEND (1<<10)
1431#define ADPA_DPMS_STANDBY (2<<10)
1432#define ADPA_DPMS_OFF (3<<10)
1433
Chris Wilson939fe4d2010-10-09 10:33:26 +01001434
Jesse Barnes585fb112008-07-29 11:54:06 -07001435/* Hotplug control (945+ only) */
1436#define PORT_HOTPLUG_EN 0x61110
Eric Anholt7d573822009-01-02 13:33:00 -08001437#define HDMIB_HOTPLUG_INT_EN (1 << 29)
Keith Packard040d87f2009-05-30 20:42:33 -07001438#define DPB_HOTPLUG_INT_EN (1 << 29)
Eric Anholt7d573822009-01-02 13:33:00 -08001439#define HDMIC_HOTPLUG_INT_EN (1 << 28)
Keith Packard040d87f2009-05-30 20:42:33 -07001440#define DPC_HOTPLUG_INT_EN (1 << 28)
Eric Anholt7d573822009-01-02 13:33:00 -08001441#define HDMID_HOTPLUG_INT_EN (1 << 27)
Keith Packard040d87f2009-05-30 20:42:33 -07001442#define DPD_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07001443#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1444#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1445#define TV_HOTPLUG_INT_EN (1 << 18)
1446#define CRT_HOTPLUG_INT_EN (1 << 9)
1447#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
Zhao Yakui771cb082009-03-03 18:07:52 +08001448#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1449/* must use period 64 on GM45 according to docs */
1450#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1451#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1452#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1453#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1454#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1455#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1456#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1457#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1458#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1459#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1460#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1461#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07001462
1463#define PORT_HOTPLUG_STAT 0x61114
Eric Anholt7d573822009-01-02 13:33:00 -08001464#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
Keith Packard040d87f2009-05-30 20:42:33 -07001465#define DPB_HOTPLUG_INT_STATUS (1 << 29)
Eric Anholt7d573822009-01-02 13:33:00 -08001466#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
Keith Packard040d87f2009-05-30 20:42:33 -07001467#define DPC_HOTPLUG_INT_STATUS (1 << 28)
Eric Anholt7d573822009-01-02 13:33:00 -08001468#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
Keith Packard040d87f2009-05-30 20:42:33 -07001469#define DPD_HOTPLUG_INT_STATUS (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -07001470#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1471#define TV_HOTPLUG_INT_STATUS (1 << 10)
1472#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1473#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1474#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1475#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1476#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1477#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1478
1479/* SDVO port control */
1480#define SDVOB 0x61140
1481#define SDVOC 0x61160
1482#define SDVO_ENABLE (1 << 31)
1483#define SDVO_PIPE_B_SELECT (1 << 30)
1484#define SDVO_STALL_SELECT (1 << 29)
1485#define SDVO_INTERRUPT_ENABLE (1 << 26)
1486/**
1487 * 915G/GM SDVO pixel multiplier.
1488 *
1489 * Programmed value is multiplier - 1, up to 5x.
1490 *
1491 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1492 */
1493#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1494#define SDVO_PORT_MULTIPLY_SHIFT 23
1495#define SDVO_PHASE_SELECT_MASK (15 << 19)
1496#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1497#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1498#define SDVOC_GANG_MODE (1 << 16)
Eric Anholt7d573822009-01-02 13:33:00 -08001499#define SDVO_ENCODING_SDVO (0x0 << 10)
1500#define SDVO_ENCODING_HDMI (0x2 << 10)
1501/** Requird for HDMI operation */
1502#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
Chris Wilsone953fd72011-02-21 22:23:52 +00001503#define SDVO_COLOR_RANGE_16_235 (1 << 8)
Jesse Barnes585fb112008-07-29 11:54:06 -07001504#define SDVO_BORDER_ENABLE (1 << 7)
Eric Anholt7d573822009-01-02 13:33:00 -08001505#define SDVO_AUDIO_ENABLE (1 << 6)
1506/** New with 965, default is to be set */
1507#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1508/** New with 965, default is to be set */
1509#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
Jesse Barnes585fb112008-07-29 11:54:06 -07001510#define SDVOB_PCIE_CONCURRENCY (1 << 3)
1511#define SDVO_DETECTED (1 << 2)
1512/* Bits to be preserved when writing */
1513#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1514#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1515
1516/* DVO port control */
1517#define DVOA 0x61120
1518#define DVOB 0x61140
1519#define DVOC 0x61160
1520#define DVO_ENABLE (1 << 31)
1521#define DVO_PIPE_B_SELECT (1 << 30)
1522#define DVO_PIPE_STALL_UNUSED (0 << 28)
1523#define DVO_PIPE_STALL (1 << 28)
1524#define DVO_PIPE_STALL_TV (2 << 28)
1525#define DVO_PIPE_STALL_MASK (3 << 28)
1526#define DVO_USE_VGA_SYNC (1 << 15)
1527#define DVO_DATA_ORDER_I740 (0 << 14)
1528#define DVO_DATA_ORDER_FP (1 << 14)
1529#define DVO_VSYNC_DISABLE (1 << 11)
1530#define DVO_HSYNC_DISABLE (1 << 10)
1531#define DVO_VSYNC_TRISTATE (1 << 9)
1532#define DVO_HSYNC_TRISTATE (1 << 8)
1533#define DVO_BORDER_ENABLE (1 << 7)
1534#define DVO_DATA_ORDER_GBRG (1 << 6)
1535#define DVO_DATA_ORDER_RGGB (0 << 6)
1536#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1537#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1538#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1539#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1540#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1541#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1542#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1543#define DVO_PRESERVE_MASK (0x7<<24)
1544#define DVOA_SRCDIM 0x61124
1545#define DVOB_SRCDIM 0x61144
1546#define DVOC_SRCDIM 0x61164
1547#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1548#define DVO_SRCDIM_VERTICAL_SHIFT 0
1549
1550/* LVDS port control */
1551#define LVDS 0x61180
1552/*
1553 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1554 * the DPLL semantics change when the LVDS is assigned to that pipe.
1555 */
1556#define LVDS_PORT_EN (1 << 31)
1557/* Selects pipe B for LVDS data. Must be set on pre-965. */
1558#define LVDS_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001559#define LVDS_PIPE_MASK (1 << 30)
Keith Packard1519b992011-08-06 10:35:34 -07001560#define LVDS_PIPE(pipe) ((pipe) << 30)
Zhao Yakui898822c2010-01-04 16:29:30 +08001561/* LVDS dithering flag on 965/g4x platform */
1562#define LVDS_ENABLE_DITHER (1 << 25)
Bryan Freedaa9b5002011-01-12 13:43:19 -08001563/* LVDS sync polarity flags. Set to invert (i.e. negative) */
1564#define LVDS_VSYNC_POLARITY (1 << 21)
1565#define LVDS_HSYNC_POLARITY (1 << 20)
1566
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08001567/* Enable border for unscaled (or aspect-scaled) display */
1568#define LVDS_BORDER_ENABLE (1 << 15)
Jesse Barnes585fb112008-07-29 11:54:06 -07001569/*
1570 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1571 * pixel.
1572 */
1573#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1574#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1575#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1576/*
1577 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1578 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1579 * on.
1580 */
1581#define LVDS_A3_POWER_MASK (3 << 6)
1582#define LVDS_A3_POWER_DOWN (0 << 6)
1583#define LVDS_A3_POWER_UP (3 << 6)
1584/*
1585 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1586 * is set.
1587 */
1588#define LVDS_CLKB_POWER_MASK (3 << 4)
1589#define LVDS_CLKB_POWER_DOWN (0 << 4)
1590#define LVDS_CLKB_POWER_UP (3 << 4)
1591/*
1592 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1593 * setting for whether we are in dual-channel mode. The B3 pair will
1594 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1595 */
1596#define LVDS_B0B3_POWER_MASK (3 << 2)
1597#define LVDS_B0B3_POWER_DOWN (0 << 2)
1598#define LVDS_B0B3_POWER_UP (3 << 2)
1599
David Härdeman3c17fe42010-09-24 21:44:32 +02001600/* Video Data Island Packet control */
1601#define VIDEO_DIP_DATA 0x61178
1602#define VIDEO_DIP_CTL 0x61170
1603#define VIDEO_DIP_ENABLE (1 << 31)
1604#define VIDEO_DIP_PORT_B (1 << 29)
1605#define VIDEO_DIP_PORT_C (2 << 29)
1606#define VIDEO_DIP_ENABLE_AVI (1 << 21)
1607#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1608#define VIDEO_DIP_ENABLE_SPD (8 << 21)
1609#define VIDEO_DIP_SELECT_AVI (0 << 19)
1610#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1611#define VIDEO_DIP_SELECT_SPD (3 << 19)
Jesse Barnes45187ac2011-08-03 09:22:55 -07001612#define VIDEO_DIP_SELECT_MASK (3 << 19)
David Härdeman3c17fe42010-09-24 21:44:32 +02001613#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1614#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1615#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1616
Jesse Barnes585fb112008-07-29 11:54:06 -07001617/* Panel power sequencing */
1618#define PP_STATUS 0x61200
1619#define PP_ON (1 << 31)
1620/*
1621 * Indicates that all dependencies of the panel are on:
1622 *
1623 * - PLL enabled
1624 * - pipe enabled
1625 * - LVDS/DVOB/DVOC on
1626 */
1627#define PP_READY (1 << 30)
1628#define PP_SEQUENCE_NONE (0 << 28)
Keith Packard99ea7122011-11-01 19:57:50 -07001629#define PP_SEQUENCE_POWER_UP (1 << 28)
1630#define PP_SEQUENCE_POWER_DOWN (2 << 28)
1631#define PP_SEQUENCE_MASK (3 << 28)
1632#define PP_SEQUENCE_SHIFT 28
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001633#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001634#define PP_SEQUENCE_STATE_MASK 0x0000000f
Keith Packard99ea7122011-11-01 19:57:50 -07001635#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
1636#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
1637#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
1638#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
1639#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
1640#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
1641#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
1642#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
1643#define PP_SEQUENCE_STATE_RESET (0xf << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001644#define PP_CONTROL 0x61204
1645#define POWER_TARGET_ON (1 << 0)
1646#define PP_ON_DELAYS 0x61208
1647#define PP_OFF_DELAYS 0x6120c
1648#define PP_DIVISOR 0x61210
1649
1650/* Panel fitting */
1651#define PFIT_CONTROL 0x61230
1652#define PFIT_ENABLE (1 << 31)
1653#define PFIT_PIPE_MASK (3 << 29)
1654#define PFIT_PIPE_SHIFT 29
1655#define VERT_INTERP_DISABLE (0 << 10)
1656#define VERT_INTERP_BILINEAR (1 << 10)
1657#define VERT_INTERP_MASK (3 << 10)
1658#define VERT_AUTO_SCALE (1 << 9)
1659#define HORIZ_INTERP_DISABLE (0 << 6)
1660#define HORIZ_INTERP_BILINEAR (1 << 6)
1661#define HORIZ_INTERP_MASK (3 << 6)
1662#define HORIZ_AUTO_SCALE (1 << 5)
1663#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08001664#define PFIT_FILTER_FUZZY (0 << 24)
1665#define PFIT_SCALING_AUTO (0 << 26)
1666#define PFIT_SCALING_PROGRAMMED (1 << 26)
1667#define PFIT_SCALING_PILLAR (2 << 26)
1668#define PFIT_SCALING_LETTER (3 << 26)
Jesse Barnes585fb112008-07-29 11:54:06 -07001669#define PFIT_PGM_RATIOS 0x61234
1670#define PFIT_VERT_SCALE_MASK 0xfff00000
1671#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
Zhao Yakui3fbe18d2009-06-22 15:31:25 +08001672/* Pre-965 */
1673#define PFIT_VERT_SCALE_SHIFT 20
1674#define PFIT_VERT_SCALE_MASK 0xfff00000
1675#define PFIT_HORIZ_SCALE_SHIFT 4
1676#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1677/* 965+ */
1678#define PFIT_VERT_SCALE_SHIFT_965 16
1679#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1680#define PFIT_HORIZ_SCALE_SHIFT_965 0
1681#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1682
Jesse Barnes585fb112008-07-29 11:54:06 -07001683#define PFIT_AUTO_RATIOS 0x61238
1684
1685/* Backlight control */
1686#define BLC_PWM_CTL 0x61254
Takashi Iwaiba3820a2011-03-10 14:02:12 +01001687#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
Jesse Barnes585fb112008-07-29 11:54:06 -07001688#define BLC_PWM_CTL2 0x61250 /* 965+ only */
Takashi Iwaiba3820a2011-03-10 14:02:12 +01001689#define BLM_COMBINATION_MODE (1 << 30)
1690/*
1691 * This is the most significant 15 bits of the number of backlight cycles in a
1692 * complete cycle of the modulated backlight control.
1693 *
1694 * The actual value is this field multiplied by two.
1695 */
1696#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1697#define BLM_LEGACY_MODE (1 << 16)
Jesse Barnes585fb112008-07-29 11:54:06 -07001698/*
1699 * This is the number of cycles out of the backlight modulation cycle for which
1700 * the backlight is on.
1701 *
1702 * This field must be no greater than the number of cycles in the complete
1703 * backlight modulation cycle.
1704 */
1705#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1706#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1707
Jesse Barnes0eb96d62009-10-14 12:33:41 -07001708#define BLC_HIST_CTL 0x61260
1709
Jesse Barnes585fb112008-07-29 11:54:06 -07001710/* TV port control */
1711#define TV_CTL 0x68000
1712/** Enables the TV encoder */
1713# define TV_ENC_ENABLE (1 << 31)
1714/** Sources the TV encoder input from pipe B instead of A. */
1715# define TV_ENC_PIPEB_SELECT (1 << 30)
1716/** Outputs composite video (DAC A only) */
1717# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1718/** Outputs SVideo video (DAC B/C) */
1719# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1720/** Outputs Component video (DAC A/B/C) */
1721# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1722/** Outputs Composite and SVideo (DAC A/B/C) */
1723# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1724# define TV_TRILEVEL_SYNC (1 << 21)
1725/** Enables slow sync generation (945GM only) */
1726# define TV_SLOW_SYNC (1 << 20)
1727/** Selects 4x oversampling for 480i and 576p */
1728# define TV_OVERSAMPLE_4X (0 << 18)
1729/** Selects 2x oversampling for 720p and 1080i */
1730# define TV_OVERSAMPLE_2X (1 << 18)
1731/** Selects no oversampling for 1080p */
1732# define TV_OVERSAMPLE_NONE (2 << 18)
1733/** Selects 8x oversampling */
1734# define TV_OVERSAMPLE_8X (3 << 18)
1735/** Selects progressive mode rather than interlaced */
1736# define TV_PROGRESSIVE (1 << 17)
1737/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1738# define TV_PAL_BURST (1 << 16)
1739/** Field for setting delay of Y compared to C */
1740# define TV_YC_SKEW_MASK (7 << 12)
1741/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1742# define TV_ENC_SDP_FIX (1 << 11)
1743/**
1744 * Enables a fix for the 915GM only.
1745 *
1746 * Not sure what it does.
1747 */
1748# define TV_ENC_C0_FIX (1 << 10)
1749/** Bits that must be preserved by software */
Zhenyu Wangd2d9f232009-03-04 19:36:02 +08001750# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
Jesse Barnes585fb112008-07-29 11:54:06 -07001751# define TV_FUSE_STATE_MASK (3 << 4)
1752/** Read-only state that reports all features enabled */
1753# define TV_FUSE_STATE_ENABLED (0 << 4)
1754/** Read-only state that reports that Macrovision is disabled in hardware*/
1755# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1756/** Read-only state that reports that TV-out is disabled in hardware. */
1757# define TV_FUSE_STATE_DISABLED (2 << 4)
1758/** Normal operation */
1759# define TV_TEST_MODE_NORMAL (0 << 0)
1760/** Encoder test pattern 1 - combo pattern */
1761# define TV_TEST_MODE_PATTERN_1 (1 << 0)
1762/** Encoder test pattern 2 - full screen vertical 75% color bars */
1763# define TV_TEST_MODE_PATTERN_2 (2 << 0)
1764/** Encoder test pattern 3 - full screen horizontal 75% color bars */
1765# define TV_TEST_MODE_PATTERN_3 (3 << 0)
1766/** Encoder test pattern 4 - random noise */
1767# define TV_TEST_MODE_PATTERN_4 (4 << 0)
1768/** Encoder test pattern 5 - linear color ramps */
1769# define TV_TEST_MODE_PATTERN_5 (5 << 0)
1770/**
1771 * This test mode forces the DACs to 50% of full output.
1772 *
1773 * This is used for load detection in combination with TVDAC_SENSE_MASK
1774 */
1775# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1776# define TV_TEST_MODE_MASK (7 << 0)
1777
1778#define TV_DAC 0x68004
Chris Wilsonb8ed2a42010-09-05 00:43:42 +01001779# define TV_DAC_SAVE 0x00ffff00
Jesse Barnes585fb112008-07-29 11:54:06 -07001780/**
1781 * Reports that DAC state change logic has reported change (RO).
1782 *
1783 * This gets cleared when TV_DAC_STATE_EN is cleared
1784*/
1785# define TVDAC_STATE_CHG (1 << 31)
1786# define TVDAC_SENSE_MASK (7 << 28)
1787/** Reports that DAC A voltage is above the detect threshold */
1788# define TVDAC_A_SENSE (1 << 30)
1789/** Reports that DAC B voltage is above the detect threshold */
1790# define TVDAC_B_SENSE (1 << 29)
1791/** Reports that DAC C voltage is above the detect threshold */
1792# define TVDAC_C_SENSE (1 << 28)
1793/**
1794 * Enables DAC state detection logic, for load-based TV detection.
1795 *
1796 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1797 * to off, for load detection to work.
1798 */
1799# define TVDAC_STATE_CHG_EN (1 << 27)
1800/** Sets the DAC A sense value to high */
1801# define TVDAC_A_SENSE_CTL (1 << 26)
1802/** Sets the DAC B sense value to high */
1803# define TVDAC_B_SENSE_CTL (1 << 25)
1804/** Sets the DAC C sense value to high */
1805# define TVDAC_C_SENSE_CTL (1 << 24)
1806/** Overrides the ENC_ENABLE and DAC voltage levels */
1807# define DAC_CTL_OVERRIDE (1 << 7)
1808/** Sets the slew rate. Must be preserved in software */
1809# define ENC_TVDAC_SLEW_FAST (1 << 6)
1810# define DAC_A_1_3_V (0 << 4)
1811# define DAC_A_1_1_V (1 << 4)
1812# define DAC_A_0_7_V (2 << 4)
Ma Lingcb66c692009-05-31 16:58:32 +08001813# define DAC_A_MASK (3 << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -07001814# define DAC_B_1_3_V (0 << 2)
1815# define DAC_B_1_1_V (1 << 2)
1816# define DAC_B_0_7_V (2 << 2)
Ma Lingcb66c692009-05-31 16:58:32 +08001817# define DAC_B_MASK (3 << 2)
Jesse Barnes585fb112008-07-29 11:54:06 -07001818# define DAC_C_1_3_V (0 << 0)
1819# define DAC_C_1_1_V (1 << 0)
1820# define DAC_C_0_7_V (2 << 0)
Ma Lingcb66c692009-05-31 16:58:32 +08001821# define DAC_C_MASK (3 << 0)
Jesse Barnes585fb112008-07-29 11:54:06 -07001822
1823/**
1824 * CSC coefficients are stored in a floating point format with 9 bits of
1825 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1826 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1827 * -1 (0x3) being the only legal negative value.
1828 */
1829#define TV_CSC_Y 0x68010
1830# define TV_RY_MASK 0x07ff0000
1831# define TV_RY_SHIFT 16
1832# define TV_GY_MASK 0x00000fff
1833# define TV_GY_SHIFT 0
1834
1835#define TV_CSC_Y2 0x68014
1836# define TV_BY_MASK 0x07ff0000
1837# define TV_BY_SHIFT 16
1838/**
1839 * Y attenuation for component video.
1840 *
1841 * Stored in 1.9 fixed point.
1842 */
1843# define TV_AY_MASK 0x000003ff
1844# define TV_AY_SHIFT 0
1845
1846#define TV_CSC_U 0x68018
1847# define TV_RU_MASK 0x07ff0000
1848# define TV_RU_SHIFT 16
1849# define TV_GU_MASK 0x000007ff
1850# define TV_GU_SHIFT 0
1851
1852#define TV_CSC_U2 0x6801c
1853# define TV_BU_MASK 0x07ff0000
1854# define TV_BU_SHIFT 16
1855/**
1856 * U attenuation for component video.
1857 *
1858 * Stored in 1.9 fixed point.
1859 */
1860# define TV_AU_MASK 0x000003ff
1861# define TV_AU_SHIFT 0
1862
1863#define TV_CSC_V 0x68020
1864# define TV_RV_MASK 0x0fff0000
1865# define TV_RV_SHIFT 16
1866# define TV_GV_MASK 0x000007ff
1867# define TV_GV_SHIFT 0
1868
1869#define TV_CSC_V2 0x68024
1870# define TV_BV_MASK 0x07ff0000
1871# define TV_BV_SHIFT 16
1872/**
1873 * V attenuation for component video.
1874 *
1875 * Stored in 1.9 fixed point.
1876 */
1877# define TV_AV_MASK 0x000007ff
1878# define TV_AV_SHIFT 0
1879
1880#define TV_CLR_KNOBS 0x68028
1881/** 2s-complement brightness adjustment */
1882# define TV_BRIGHTNESS_MASK 0xff000000
1883# define TV_BRIGHTNESS_SHIFT 24
1884/** Contrast adjustment, as a 2.6 unsigned floating point number */
1885# define TV_CONTRAST_MASK 0x00ff0000
1886# define TV_CONTRAST_SHIFT 16
1887/** Saturation adjustment, as a 2.6 unsigned floating point number */
1888# define TV_SATURATION_MASK 0x0000ff00
1889# define TV_SATURATION_SHIFT 8
1890/** Hue adjustment, as an integer phase angle in degrees */
1891# define TV_HUE_MASK 0x000000ff
1892# define TV_HUE_SHIFT 0
1893
1894#define TV_CLR_LEVEL 0x6802c
1895/** Controls the DAC level for black */
1896# define TV_BLACK_LEVEL_MASK 0x01ff0000
1897# define TV_BLACK_LEVEL_SHIFT 16
1898/** Controls the DAC level for blanking */
1899# define TV_BLANK_LEVEL_MASK 0x000001ff
1900# define TV_BLANK_LEVEL_SHIFT 0
1901
1902#define TV_H_CTL_1 0x68030
1903/** Number of pixels in the hsync. */
1904# define TV_HSYNC_END_MASK 0x1fff0000
1905# define TV_HSYNC_END_SHIFT 16
1906/** Total number of pixels minus one in the line (display and blanking). */
1907# define TV_HTOTAL_MASK 0x00001fff
1908# define TV_HTOTAL_SHIFT 0
1909
1910#define TV_H_CTL_2 0x68034
1911/** Enables the colorburst (needed for non-component color) */
1912# define TV_BURST_ENA (1 << 31)
1913/** Offset of the colorburst from the start of hsync, in pixels minus one. */
1914# define TV_HBURST_START_SHIFT 16
1915# define TV_HBURST_START_MASK 0x1fff0000
1916/** Length of the colorburst */
1917# define TV_HBURST_LEN_SHIFT 0
1918# define TV_HBURST_LEN_MASK 0x0001fff
1919
1920#define TV_H_CTL_3 0x68038
1921/** End of hblank, measured in pixels minus one from start of hsync */
1922# define TV_HBLANK_END_SHIFT 16
1923# define TV_HBLANK_END_MASK 0x1fff0000
1924/** Start of hblank, measured in pixels minus one from start of hsync */
1925# define TV_HBLANK_START_SHIFT 0
1926# define TV_HBLANK_START_MASK 0x0001fff
1927
1928#define TV_V_CTL_1 0x6803c
1929/** XXX */
1930# define TV_NBR_END_SHIFT 16
1931# define TV_NBR_END_MASK 0x07ff0000
1932/** XXX */
1933# define TV_VI_END_F1_SHIFT 8
1934# define TV_VI_END_F1_MASK 0x00003f00
1935/** XXX */
1936# define TV_VI_END_F2_SHIFT 0
1937# define TV_VI_END_F2_MASK 0x0000003f
1938
1939#define TV_V_CTL_2 0x68040
1940/** Length of vsync, in half lines */
1941# define TV_VSYNC_LEN_MASK 0x07ff0000
1942# define TV_VSYNC_LEN_SHIFT 16
1943/** Offset of the start of vsync in field 1, measured in one less than the
1944 * number of half lines.
1945 */
1946# define TV_VSYNC_START_F1_MASK 0x00007f00
1947# define TV_VSYNC_START_F1_SHIFT 8
1948/**
1949 * Offset of the start of vsync in field 2, measured in one less than the
1950 * number of half lines.
1951 */
1952# define TV_VSYNC_START_F2_MASK 0x0000007f
1953# define TV_VSYNC_START_F2_SHIFT 0
1954
1955#define TV_V_CTL_3 0x68044
1956/** Enables generation of the equalization signal */
1957# define TV_EQUAL_ENA (1 << 31)
1958/** Length of vsync, in half lines */
1959# define TV_VEQ_LEN_MASK 0x007f0000
1960# define TV_VEQ_LEN_SHIFT 16
1961/** Offset of the start of equalization in field 1, measured in one less than
1962 * the number of half lines.
1963 */
1964# define TV_VEQ_START_F1_MASK 0x0007f00
1965# define TV_VEQ_START_F1_SHIFT 8
1966/**
1967 * Offset of the start of equalization in field 2, measured in one less than
1968 * the number of half lines.
1969 */
1970# define TV_VEQ_START_F2_MASK 0x000007f
1971# define TV_VEQ_START_F2_SHIFT 0
1972
1973#define TV_V_CTL_4 0x68048
1974/**
1975 * Offset to start of vertical colorburst, measured in one less than the
1976 * number of lines from vertical start.
1977 */
1978# define TV_VBURST_START_F1_MASK 0x003f0000
1979# define TV_VBURST_START_F1_SHIFT 16
1980/**
1981 * Offset to the end of vertical colorburst, measured in one less than the
1982 * number of lines from the start of NBR.
1983 */
1984# define TV_VBURST_END_F1_MASK 0x000000ff
1985# define TV_VBURST_END_F1_SHIFT 0
1986
1987#define TV_V_CTL_5 0x6804c
1988/**
1989 * Offset to start of vertical colorburst, measured in one less than the
1990 * number of lines from vertical start.
1991 */
1992# define TV_VBURST_START_F2_MASK 0x003f0000
1993# define TV_VBURST_START_F2_SHIFT 16
1994/**
1995 * Offset to the end of vertical colorburst, measured in one less than the
1996 * number of lines from the start of NBR.
1997 */
1998# define TV_VBURST_END_F2_MASK 0x000000ff
1999# define TV_VBURST_END_F2_SHIFT 0
2000
2001#define TV_V_CTL_6 0x68050
2002/**
2003 * Offset to start of vertical colorburst, measured in one less than the
2004 * number of lines from vertical start.
2005 */
2006# define TV_VBURST_START_F3_MASK 0x003f0000
2007# define TV_VBURST_START_F3_SHIFT 16
2008/**
2009 * Offset to the end of vertical colorburst, measured in one less than the
2010 * number of lines from the start of NBR.
2011 */
2012# define TV_VBURST_END_F3_MASK 0x000000ff
2013# define TV_VBURST_END_F3_SHIFT 0
2014
2015#define TV_V_CTL_7 0x68054
2016/**
2017 * Offset to start of vertical colorburst, measured in one less than the
2018 * number of lines from vertical start.
2019 */
2020# define TV_VBURST_START_F4_MASK 0x003f0000
2021# define TV_VBURST_START_F4_SHIFT 16
2022/**
2023 * Offset to the end of vertical colorburst, measured in one less than the
2024 * number of lines from the start of NBR.
2025 */
2026# define TV_VBURST_END_F4_MASK 0x000000ff
2027# define TV_VBURST_END_F4_SHIFT 0
2028
2029#define TV_SC_CTL_1 0x68060
2030/** Turns on the first subcarrier phase generation DDA */
2031# define TV_SC_DDA1_EN (1 << 31)
2032/** Turns on the first subcarrier phase generation DDA */
2033# define TV_SC_DDA2_EN (1 << 30)
2034/** Turns on the first subcarrier phase generation DDA */
2035# define TV_SC_DDA3_EN (1 << 29)
2036/** Sets the subcarrier DDA to reset frequency every other field */
2037# define TV_SC_RESET_EVERY_2 (0 << 24)
2038/** Sets the subcarrier DDA to reset frequency every fourth field */
2039# define TV_SC_RESET_EVERY_4 (1 << 24)
2040/** Sets the subcarrier DDA to reset frequency every eighth field */
2041# define TV_SC_RESET_EVERY_8 (2 << 24)
2042/** Sets the subcarrier DDA to never reset the frequency */
2043# define TV_SC_RESET_NEVER (3 << 24)
2044/** Sets the peak amplitude of the colorburst.*/
2045# define TV_BURST_LEVEL_MASK 0x00ff0000
2046# define TV_BURST_LEVEL_SHIFT 16
2047/** Sets the increment of the first subcarrier phase generation DDA */
2048# define TV_SCDDA1_INC_MASK 0x00000fff
2049# define TV_SCDDA1_INC_SHIFT 0
2050
2051#define TV_SC_CTL_2 0x68064
2052/** Sets the rollover for the second subcarrier phase generation DDA */
2053# define TV_SCDDA2_SIZE_MASK 0x7fff0000
2054# define TV_SCDDA2_SIZE_SHIFT 16
2055/** Sets the increent of the second subcarrier phase generation DDA */
2056# define TV_SCDDA2_INC_MASK 0x00007fff
2057# define TV_SCDDA2_INC_SHIFT 0
2058
2059#define TV_SC_CTL_3 0x68068
2060/** Sets the rollover for the third subcarrier phase generation DDA */
2061# define TV_SCDDA3_SIZE_MASK 0x7fff0000
2062# define TV_SCDDA3_SIZE_SHIFT 16
2063/** Sets the increent of the third subcarrier phase generation DDA */
2064# define TV_SCDDA3_INC_MASK 0x00007fff
2065# define TV_SCDDA3_INC_SHIFT 0
2066
2067#define TV_WIN_POS 0x68070
2068/** X coordinate of the display from the start of horizontal active */
2069# define TV_XPOS_MASK 0x1fff0000
2070# define TV_XPOS_SHIFT 16
2071/** Y coordinate of the display from the start of vertical active (NBR) */
2072# define TV_YPOS_MASK 0x00000fff
2073# define TV_YPOS_SHIFT 0
2074
2075#define TV_WIN_SIZE 0x68074
2076/** Horizontal size of the display window, measured in pixels*/
2077# define TV_XSIZE_MASK 0x1fff0000
2078# define TV_XSIZE_SHIFT 16
2079/**
2080 * Vertical size of the display window, measured in pixels.
2081 *
2082 * Must be even for interlaced modes.
2083 */
2084# define TV_YSIZE_MASK 0x00000fff
2085# define TV_YSIZE_SHIFT 0
2086
2087#define TV_FILTER_CTL_1 0x68080
2088/**
2089 * Enables automatic scaling calculation.
2090 *
2091 * If set, the rest of the registers are ignored, and the calculated values can
2092 * be read back from the register.
2093 */
2094# define TV_AUTO_SCALE (1 << 31)
2095/**
2096 * Disables the vertical filter.
2097 *
2098 * This is required on modes more than 1024 pixels wide */
2099# define TV_V_FILTER_BYPASS (1 << 29)
2100/** Enables adaptive vertical filtering */
2101# define TV_VADAPT (1 << 28)
2102# define TV_VADAPT_MODE_MASK (3 << 26)
2103/** Selects the least adaptive vertical filtering mode */
2104# define TV_VADAPT_MODE_LEAST (0 << 26)
2105/** Selects the moderately adaptive vertical filtering mode */
2106# define TV_VADAPT_MODE_MODERATE (1 << 26)
2107/** Selects the most adaptive vertical filtering mode */
2108# define TV_VADAPT_MODE_MOST (3 << 26)
2109/**
2110 * Sets the horizontal scaling factor.
2111 *
2112 * This should be the fractional part of the horizontal scaling factor divided
2113 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2114 *
2115 * (src width - 1) / ((oversample * dest width) - 1)
2116 */
2117# define TV_HSCALE_FRAC_MASK 0x00003fff
2118# define TV_HSCALE_FRAC_SHIFT 0
2119
2120#define TV_FILTER_CTL_2 0x68084
2121/**
2122 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2123 *
2124 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2125 */
2126# define TV_VSCALE_INT_MASK 0x00038000
2127# define TV_VSCALE_INT_SHIFT 15
2128/**
2129 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2130 *
2131 * \sa TV_VSCALE_INT_MASK
2132 */
2133# define TV_VSCALE_FRAC_MASK 0x00007fff
2134# define TV_VSCALE_FRAC_SHIFT 0
2135
2136#define TV_FILTER_CTL_3 0x68088
2137/**
2138 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2139 *
2140 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2141 *
2142 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2143 */
2144# define TV_VSCALE_IP_INT_MASK 0x00038000
2145# define TV_VSCALE_IP_INT_SHIFT 15
2146/**
2147 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2148 *
2149 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2150 *
2151 * \sa TV_VSCALE_IP_INT_MASK
2152 */
2153# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2154# define TV_VSCALE_IP_FRAC_SHIFT 0
2155
2156#define TV_CC_CONTROL 0x68090
2157# define TV_CC_ENABLE (1 << 31)
2158/**
2159 * Specifies which field to send the CC data in.
2160 *
2161 * CC data is usually sent in field 0.
2162 */
2163# define TV_CC_FID_MASK (1 << 27)
2164# define TV_CC_FID_SHIFT 27
2165/** Sets the horizontal position of the CC data. Usually 135. */
2166# define TV_CC_HOFF_MASK 0x03ff0000
2167# define TV_CC_HOFF_SHIFT 16
2168/** Sets the vertical position of the CC data. Usually 21 */
2169# define TV_CC_LINE_MASK 0x0000003f
2170# define TV_CC_LINE_SHIFT 0
2171
2172#define TV_CC_DATA 0x68094
2173# define TV_CC_RDY (1 << 31)
2174/** Second word of CC data to be transmitted. */
2175# define TV_CC_DATA_2_MASK 0x007f0000
2176# define TV_CC_DATA_2_SHIFT 16
2177/** First word of CC data to be transmitted. */
2178# define TV_CC_DATA_1_MASK 0x0000007f
2179# define TV_CC_DATA_1_SHIFT 0
2180
2181#define TV_H_LUMA_0 0x68100
2182#define TV_H_LUMA_59 0x681ec
2183#define TV_H_CHROMA_0 0x68200
2184#define TV_H_CHROMA_59 0x682ec
2185#define TV_V_LUMA_0 0x68300
2186#define TV_V_LUMA_42 0x683a8
2187#define TV_V_CHROMA_0 0x68400
2188#define TV_V_CHROMA_42 0x684a8
2189
Keith Packard040d87f2009-05-30 20:42:33 -07002190/* Display Port */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002191#define DP_A 0x64000 /* eDP */
Keith Packard040d87f2009-05-30 20:42:33 -07002192#define DP_B 0x64100
2193#define DP_C 0x64200
2194#define DP_D 0x64300
2195
2196#define DP_PORT_EN (1 << 31)
2197#define DP_PIPEB_SELECT (1 << 30)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08002198#define DP_PIPE_MASK (1 << 30)
2199
Keith Packard040d87f2009-05-30 20:42:33 -07002200/* Link training mode - select a suitable mode for each stage */
2201#define DP_LINK_TRAIN_PAT_1 (0 << 28)
2202#define DP_LINK_TRAIN_PAT_2 (1 << 28)
2203#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2204#define DP_LINK_TRAIN_OFF (3 << 28)
2205#define DP_LINK_TRAIN_MASK (3 << 28)
2206#define DP_LINK_TRAIN_SHIFT 28
2207
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002208/* CPT Link training mode */
2209#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2210#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2211#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2212#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2213#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2214#define DP_LINK_TRAIN_SHIFT_CPT 8
2215
Keith Packard040d87f2009-05-30 20:42:33 -07002216/* Signal voltages. These are mostly controlled by the other end */
2217#define DP_VOLTAGE_0_4 (0 << 25)
2218#define DP_VOLTAGE_0_6 (1 << 25)
2219#define DP_VOLTAGE_0_8 (2 << 25)
2220#define DP_VOLTAGE_1_2 (3 << 25)
2221#define DP_VOLTAGE_MASK (7 << 25)
2222#define DP_VOLTAGE_SHIFT 25
2223
2224/* Signal pre-emphasis levels, like voltages, the other end tells us what
2225 * they want
2226 */
2227#define DP_PRE_EMPHASIS_0 (0 << 22)
2228#define DP_PRE_EMPHASIS_3_5 (1 << 22)
2229#define DP_PRE_EMPHASIS_6 (2 << 22)
2230#define DP_PRE_EMPHASIS_9_5 (3 << 22)
2231#define DP_PRE_EMPHASIS_MASK (7 << 22)
2232#define DP_PRE_EMPHASIS_SHIFT 22
2233
2234/* How many wires to use. I guess 3 was too hard */
2235#define DP_PORT_WIDTH_1 (0 << 19)
2236#define DP_PORT_WIDTH_2 (1 << 19)
2237#define DP_PORT_WIDTH_4 (3 << 19)
2238#define DP_PORT_WIDTH_MASK (7 << 19)
2239
2240/* Mystic DPCD version 1.1 special mode */
2241#define DP_ENHANCED_FRAMING (1 << 18)
2242
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002243/* eDP */
2244#define DP_PLL_FREQ_270MHZ (0 << 16)
2245#define DP_PLL_FREQ_160MHZ (1 << 16)
2246#define DP_PLL_FREQ_MASK (3 << 16)
2247
Keith Packard040d87f2009-05-30 20:42:33 -07002248/** locked once port is enabled */
2249#define DP_PORT_REVERSAL (1 << 15)
2250
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002251/* eDP */
2252#define DP_PLL_ENABLE (1 << 14)
2253
Keith Packard040d87f2009-05-30 20:42:33 -07002254/** sends the clock on lane 15 of the PEG for debug */
2255#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2256
2257#define DP_SCRAMBLING_DISABLE (1 << 12)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002258#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
Keith Packard040d87f2009-05-30 20:42:33 -07002259
2260/** limit RGB values to avoid confusing TVs */
2261#define DP_COLOR_RANGE_16_235 (1 << 8)
2262
2263/** Turn on the audio link */
2264#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2265
2266/** vs and hs sync polarity */
2267#define DP_SYNC_VS_HIGH (1 << 4)
2268#define DP_SYNC_HS_HIGH (1 << 3)
2269
2270/** A fantasy */
2271#define DP_DETECTED (1 << 2)
2272
2273/** The aux channel provides a way to talk to the
2274 * signal sink for DDC etc. Max packet size supported
2275 * is 20 bytes in each direction, hence the 5 fixed
2276 * data registers
2277 */
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002278#define DPA_AUX_CH_CTL 0x64010
2279#define DPA_AUX_CH_DATA1 0x64014
2280#define DPA_AUX_CH_DATA2 0x64018
2281#define DPA_AUX_CH_DATA3 0x6401c
2282#define DPA_AUX_CH_DATA4 0x64020
2283#define DPA_AUX_CH_DATA5 0x64024
2284
Keith Packard040d87f2009-05-30 20:42:33 -07002285#define DPB_AUX_CH_CTL 0x64110
2286#define DPB_AUX_CH_DATA1 0x64114
2287#define DPB_AUX_CH_DATA2 0x64118
2288#define DPB_AUX_CH_DATA3 0x6411c
2289#define DPB_AUX_CH_DATA4 0x64120
2290#define DPB_AUX_CH_DATA5 0x64124
2291
2292#define DPC_AUX_CH_CTL 0x64210
2293#define DPC_AUX_CH_DATA1 0x64214
2294#define DPC_AUX_CH_DATA2 0x64218
2295#define DPC_AUX_CH_DATA3 0x6421c
2296#define DPC_AUX_CH_DATA4 0x64220
2297#define DPC_AUX_CH_DATA5 0x64224
2298
2299#define DPD_AUX_CH_CTL 0x64310
2300#define DPD_AUX_CH_DATA1 0x64314
2301#define DPD_AUX_CH_DATA2 0x64318
2302#define DPD_AUX_CH_DATA3 0x6431c
2303#define DPD_AUX_CH_DATA4 0x64320
2304#define DPD_AUX_CH_DATA5 0x64324
2305
2306#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2307#define DP_AUX_CH_CTL_DONE (1 << 30)
2308#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2309#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2310#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2311#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2312#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2313#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2314#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2315#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2316#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2317#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2318#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2319#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2320#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2321#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2322#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2323#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2324#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2325#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2326#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2327
2328/*
2329 * Computing GMCH M and N values for the Display Port link
2330 *
2331 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2332 *
2333 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2334 *
2335 * The GMCH value is used internally
2336 *
2337 * bytes_per_pixel is the number of bytes coming out of the plane,
2338 * which is after the LUTs, so we want the bytes for our color format.
2339 * For our current usage, this is always 3, one byte for R, G and B.
2340 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002341#define _PIPEA_GMCH_DATA_M 0x70050
2342#define _PIPEB_GMCH_DATA_M 0x71050
Keith Packard040d87f2009-05-30 20:42:33 -07002343
2344/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2345#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2346#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2347
2348#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2349
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002350#define _PIPEA_GMCH_DATA_N 0x70054
2351#define _PIPEB_GMCH_DATA_N 0x71054
Keith Packard040d87f2009-05-30 20:42:33 -07002352#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2353
2354/*
2355 * Computing Link M and N values for the Display Port link
2356 *
2357 * Link M / N = pixel_clock / ls_clk
2358 *
2359 * (the DP spec calls pixel_clock the 'strm_clk')
2360 *
2361 * The Link value is transmitted in the Main Stream
2362 * Attributes and VB-ID.
2363 */
2364
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002365#define _PIPEA_DP_LINK_M 0x70060
2366#define _PIPEB_DP_LINK_M 0x71060
Keith Packard040d87f2009-05-30 20:42:33 -07002367#define PIPEA_DP_LINK_M_MASK (0xffffff)
2368
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002369#define _PIPEA_DP_LINK_N 0x70064
2370#define _PIPEB_DP_LINK_N 0x71064
Keith Packard040d87f2009-05-30 20:42:33 -07002371#define PIPEA_DP_LINK_N_MASK (0xffffff)
2372
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002373#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2374#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2375#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2376#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2377
Jesse Barnes585fb112008-07-29 11:54:06 -07002378/* Display & cursor control */
2379
2380/* Pipe A */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002381#define _PIPEADSL 0x70000
Chris Wilson58e10eb2010-10-03 10:56:11 +01002382#define DSL_LINEMASK 0x00000fff
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002383#define _PIPEACONF 0x70008
Chris Wilson5eddb702010-09-11 13:48:45 +01002384#define PIPECONF_ENABLE (1<<31)
2385#define PIPECONF_DISABLE 0
2386#define PIPECONF_DOUBLE_WIDE (1<<30)
Jesse Barnes585fb112008-07-29 11:54:06 -07002387#define I965_PIPECONF_ACTIVE (1<<30)
Chris Wilsonf47166d2012-03-22 15:00:50 +00002388#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
Chris Wilson5eddb702010-09-11 13:48:45 +01002389#define PIPECONF_SINGLE_WIDE 0
2390#define PIPECONF_PIPE_UNLOCKED 0
2391#define PIPECONF_PIPE_LOCKED (1<<25)
2392#define PIPECONF_PALETTE 0
2393#define PIPECONF_GAMMA (1<<24)
Jesse Barnes585fb112008-07-29 11:54:06 -07002394#define PIPECONF_FORCE_BORDER (1<<25)
Christian Schmidt59df7b12011-12-19 20:03:33 +01002395#define PIPECONF_INTERLACE_MASK (7 << 21)
Daniel Vetterd442ae12012-01-28 14:49:19 +01002396/* Note that pre-gen3 does not support interlaced display directly. Panel
2397 * fitting must be disabled on pre-ilk for interlaced. */
2398#define PIPECONF_PROGRESSIVE (0 << 21)
2399#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
2400#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
2401#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2402#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
2403/* Ironlake and later have a complete new set of values for interlaced. PFIT
2404 * means panel fitter required, PF means progressive fetch, DBL means power
2405 * saving pixel doubling. */
2406#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
2407#define PIPECONF_INTERLACED_ILK (3 << 21)
2408#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
2409#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
Jesse Barnes652c3932009-08-17 13:31:43 -07002410#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
Jesse Barnes4f0d1af2010-09-07 14:48:05 -07002411#define PIPECONF_BPP_MASK (0x000000e0)
2412#define PIPECONF_BPP_8 (0<<5)
2413#define PIPECONF_BPP_10 (1<<5)
2414#define PIPECONF_BPP_6 (2<<5)
2415#define PIPECONF_BPP_12 (3<<5)
2416#define PIPECONF_DITHER_EN (1<<4)
2417#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2418#define PIPECONF_DITHER_TYPE_SP (0<<2)
2419#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2420#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2421#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002422#define _PIPEASTAT 0x70024
Jesse Barnes585fb112008-07-29 11:54:06 -07002423#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2424#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2425#define PIPE_CRC_DONE_ENABLE (1UL<<28)
2426#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2427#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2428#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2429#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2430#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2431#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2432#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2433#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2434#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2435#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2436#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2437#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2438#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2439#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2440#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2441#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2442#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2443#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2444#define PIPE_DPST_EVENT_STATUS (1UL<<7)
2445#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2446#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2447#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2448#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2449#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2450#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2451#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
Chris Wilson58e10eb2010-10-03 10:56:11 +01002452#define PIPE_BPC_MASK (7 << 5) /* Ironlake */
Zhenyu Wang58a27472009-09-25 08:01:28 +00002453#define PIPE_8BPC (0 << 5)
2454#define PIPE_10BPC (1 << 5)
2455#define PIPE_6BPC (2 << 5)
2456#define PIPE_12BPC (3 << 5)
Jesse Barnes585fb112008-07-29 11:54:06 -07002457
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002458#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2459#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2460#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2461#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2462#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2463#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
Chris Wilson5eddb702010-09-11 13:48:45 +01002464
Jesse Barnes585fb112008-07-29 11:54:06 -07002465#define DSPARB 0x70030
2466#define DSPARB_CSTART_MASK (0x7f << 7)
2467#define DSPARB_CSTART_SHIFT 7
2468#define DSPARB_BSTART_MASK (0x7f)
2469#define DSPARB_BSTART_SHIFT 0
Shaohua Li7662c8b2009-06-26 11:23:55 +08002470#define DSPARB_BEND_SHIFT 9 /* on 855 */
2471#define DSPARB_AEND_SHIFT 0
2472
2473#define DSPFW1 0x70034
Jesse Barnes0e442c62009-10-19 10:09:33 +09002474#define DSPFW_SR_SHIFT 23
Akshay Joshi0206e352011-08-16 15:34:10 -04002475#define DSPFW_SR_MASK (0x1ff<<23)
Jesse Barnes0e442c62009-10-19 10:09:33 +09002476#define DSPFW_CURSORB_SHIFT 16
Zhao Yakuid4294342010-03-22 22:45:36 +08002477#define DSPFW_CURSORB_MASK (0x3f<<16)
Jesse Barnes0e442c62009-10-19 10:09:33 +09002478#define DSPFW_PLANEB_SHIFT 8
Zhao Yakuid4294342010-03-22 22:45:36 +08002479#define DSPFW_PLANEB_MASK (0x7f<<8)
2480#define DSPFW_PLANEA_MASK (0x7f)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002481#define DSPFW2 0x70038
Jesse Barnes0e442c62009-10-19 10:09:33 +09002482#define DSPFW_CURSORA_MASK 0x00003f00
Zhao Yakui21bd7702010-01-13 14:10:50 +00002483#define DSPFW_CURSORA_SHIFT 8
Zhao Yakuid4294342010-03-22 22:45:36 +08002484#define DSPFW_PLANEC_MASK (0x7f)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002485#define DSPFW3 0x7003c
Jesse Barnes0e442c62009-10-19 10:09:33 +09002486#define DSPFW_HPLL_SR_EN (1<<31)
2487#define DSPFW_CURSOR_SR_SHIFT 24
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002488#define PINEVIEW_SELF_REFRESH_EN (1<<30)
Zhao Yakuid4294342010-03-22 22:45:36 +08002489#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2490#define DSPFW_HPLL_CURSOR_SHIFT 16
2491#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2492#define DSPFW_HPLL_SR_MASK (0x1ff)
Shaohua Li7662c8b2009-06-26 11:23:55 +08002493
2494/* FIFO watermark sizes etc */
Jesse Barnes0e442c62009-10-19 10:09:33 +09002495#define G4X_FIFO_LINE_SIZE 64
Shaohua Li7662c8b2009-06-26 11:23:55 +08002496#define I915_FIFO_LINE_SIZE 64
2497#define I830_FIFO_LINE_SIZE 32
Jesse Barnes0e442c62009-10-19 10:09:33 +09002498
2499#define G4X_FIFO_SIZE 127
Zhao Yakui1b07e042010-06-12 14:32:24 +08002500#define I965_FIFO_SIZE 512
2501#define I945_FIFO_SIZE 127
Shaohua Li7662c8b2009-06-26 11:23:55 +08002502#define I915_FIFO_SIZE 95
Jesse Barnesdff33cf2009-07-14 10:15:56 -07002503#define I855GM_FIFO_SIZE 127 /* In cachelines */
Shaohua Li7662c8b2009-06-26 11:23:55 +08002504#define I830_FIFO_SIZE 95
Jesse Barnes0e442c62009-10-19 10:09:33 +09002505
2506#define G4X_MAX_WM 0x3f
Shaohua Li7662c8b2009-06-26 11:23:55 +08002507#define I915_MAX_WM 0x3f
2508
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002509#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2510#define PINEVIEW_FIFO_LINE_SIZE 64
2511#define PINEVIEW_MAX_WM 0x1ff
2512#define PINEVIEW_DFT_WM 0x3f
2513#define PINEVIEW_DFT_HPLLOFF_WM 0
2514#define PINEVIEW_GUARD_WM 10
2515#define PINEVIEW_CURSOR_FIFO 64
2516#define PINEVIEW_CURSOR_MAX_WM 0x3f
2517#define PINEVIEW_CURSOR_DFT_WM 0
2518#define PINEVIEW_CURSOR_GUARD_WM 5
Shaohua Li7662c8b2009-06-26 11:23:55 +08002519
Zhao Yakui4fe5e612010-06-12 14:32:25 +08002520#define I965_CURSOR_FIFO 64
2521#define I965_CURSOR_MAX_WM 32
2522#define I965_CURSOR_DFT_WM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002523
2524/* define the Watermark register on Ironlake */
2525#define WM0_PIPEA_ILK 0x45100
2526#define WM0_PIPE_PLANE_MASK (0x7f<<16)
2527#define WM0_PIPE_PLANE_SHIFT 16
2528#define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2529#define WM0_PIPE_SPRITE_SHIFT 8
2530#define WM0_PIPE_CURSOR_MASK (0x1f)
2531
2532#define WM0_PIPEB_ILK 0x45104
Jesse Barnesd6c892d2011-10-12 15:36:42 -07002533#define WM0_PIPEC_IVB 0x45200
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002534#define WM1_LP_ILK 0x45108
2535#define WM1_LP_SR_EN (1<<31)
2536#define WM1_LP_LATENCY_SHIFT 24
2537#define WM1_LP_LATENCY_MASK (0x7f<<24)
Chris Wilson4ed765f2010-09-11 10:46:47 +01002538#define WM1_LP_FBC_MASK (0xf<<20)
2539#define WM1_LP_FBC_SHIFT 20
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002540#define WM1_LP_SR_MASK (0x1ff<<8)
2541#define WM1_LP_SR_SHIFT 8
2542#define WM1_LP_CURSOR_MASK (0x3f)
Jesse Barnesdd8849c2010-09-09 11:58:02 -07002543#define WM2_LP_ILK 0x4510c
2544#define WM2_LP_EN (1<<31)
2545#define WM3_LP_ILK 0x45110
2546#define WM3_LP_EN (1<<31)
2547#define WM1S_LP_ILK 0x45120
Jesse Barnesb840d907f2011-12-13 13:19:38 -08002548#define WM2S_LP_IVB 0x45124
2549#define WM3S_LP_IVB 0x45128
Jesse Barnesdd8849c2010-09-09 11:58:02 -07002550#define WM1S_LP_EN (1<<31)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002551
2552/* Memory latency timer register */
2553#define MLTR_ILK 0x11222
Jesse Barnesb79d4992010-12-21 13:10:23 -08002554#define MLTR_WM1_SHIFT 0
2555#define MLTR_WM2_SHIFT 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002556/* the unit of memory self-refresh latency time is 0.5us */
2557#define ILK_SRLT_MASK 0x3f
Jesse Barnesb79d4992010-12-21 13:10:23 -08002558#define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2559#define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2560#define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002561
2562/* define the fifo size on Ironlake */
2563#define ILK_DISPLAY_FIFO 128
2564#define ILK_DISPLAY_MAXWM 64
2565#define ILK_DISPLAY_DFTWM 8
Zhao Yakuic936f442010-06-12 14:32:26 +08002566#define ILK_CURSOR_FIFO 32
2567#define ILK_CURSOR_MAXWM 16
2568#define ILK_CURSOR_DFTWM 8
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08002569
2570#define ILK_DISPLAY_SR_FIFO 512
2571#define ILK_DISPLAY_MAX_SRWM 0x1ff
2572#define ILK_DISPLAY_DFT_SRWM 0x3f
2573#define ILK_CURSOR_SR_FIFO 64
2574#define ILK_CURSOR_MAX_SRWM 0x3f
2575#define ILK_CURSOR_DFT_SRWM 8
2576
2577#define ILK_FIFO_LINE_SIZE 64
2578
Yuanhan Liu13982612010-12-15 15:42:31 +08002579/* define the WM info on Sandybridge */
2580#define SNB_DISPLAY_FIFO 128
2581#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2582#define SNB_DISPLAY_DFTWM 8
2583#define SNB_CURSOR_FIFO 32
2584#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2585#define SNB_CURSOR_DFTWM 8
2586
2587#define SNB_DISPLAY_SR_FIFO 512
2588#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2589#define SNB_DISPLAY_DFT_SRWM 0x3f
2590#define SNB_CURSOR_SR_FIFO 64
2591#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2592#define SNB_CURSOR_DFT_SRWM 8
2593
2594#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2595
2596#define SNB_FIFO_LINE_SIZE 64
2597
2598
2599/* the address where we get all kinds of latency value */
2600#define SSKPD 0x5d10
2601#define SSKPD_WM_MASK 0x3f
2602#define SSKPD_WM0_SHIFT 0
2603#define SSKPD_WM1_SHIFT 8
2604#define SSKPD_WM2_SHIFT 16
2605#define SSKPD_WM3_SHIFT 24
2606
2607#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2608#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2609#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2610#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2611#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2612
Jesse Barnes585fb112008-07-29 11:54:06 -07002613/*
2614 * The two pipe frame counter registers are not synchronized, so
2615 * reading a stable value is somewhat tricky. The following code
2616 * should work:
2617 *
2618 * do {
2619 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2620 * PIPE_FRAME_HIGH_SHIFT;
2621 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2622 * PIPE_FRAME_LOW_SHIFT);
2623 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2624 * PIPE_FRAME_HIGH_SHIFT);
2625 * } while (high1 != high2);
2626 * frame = (high1 << 8) | low1;
2627 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002628#define _PIPEAFRAMEHIGH 0x70040
Jesse Barnes585fb112008-07-29 11:54:06 -07002629#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2630#define PIPE_FRAME_HIGH_SHIFT 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002631#define _PIPEAFRAMEPIXEL 0x70044
Jesse Barnes585fb112008-07-29 11:54:06 -07002632#define PIPE_FRAME_LOW_MASK 0xff000000
2633#define PIPE_FRAME_LOW_SHIFT 24
2634#define PIPE_PIXEL_MASK 0x00ffffff
2635#define PIPE_PIXEL_SHIFT 0
Jesse Barnes9880b7a2009-02-06 10:22:41 -08002636/* GM45+ just has to be different */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002637#define _PIPEA_FRMCOUNT_GM45 0x70040
2638#define _PIPEA_FLIPCOUNT_GM45 0x70044
2639#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
Jesse Barnes585fb112008-07-29 11:54:06 -07002640
2641/* Cursor A & B regs */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002642#define _CURACNTR 0x70080
Jesse Barnes14b60392009-05-20 16:47:08 -04002643/* Old style CUR*CNTR flags (desktop 8xx) */
2644#define CURSOR_ENABLE 0x80000000
2645#define CURSOR_GAMMA_ENABLE 0x40000000
2646#define CURSOR_STRIDE_MASK 0x30000000
2647#define CURSOR_FORMAT_SHIFT 24
2648#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2649#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2650#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2651#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2652#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2653#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2654/* New style CUR*CNTR flags */
2655#define CURSOR_MODE 0x27
Jesse Barnes585fb112008-07-29 11:54:06 -07002656#define CURSOR_MODE_DISABLE 0x00
2657#define CURSOR_MODE_64_32B_AX 0x07
2658#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
Jesse Barnes14b60392009-05-20 16:47:08 -04002659#define MCURSOR_PIPE_SELECT (1 << 28)
2660#define MCURSOR_PIPE_A 0x00
2661#define MCURSOR_PIPE_B (1 << 28)
Jesse Barnes585fb112008-07-29 11:54:06 -07002662#define MCURSOR_GAMMA_ENABLE (1 << 26)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002663#define _CURABASE 0x70084
2664#define _CURAPOS 0x70088
Jesse Barnes585fb112008-07-29 11:54:06 -07002665#define CURSOR_POS_MASK 0x007FF
2666#define CURSOR_POS_SIGN 0x8000
2667#define CURSOR_X_SHIFT 0
2668#define CURSOR_Y_SHIFT 16
Jesse Barnes14b60392009-05-20 16:47:08 -04002669#define CURSIZE 0x700a0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002670#define _CURBCNTR 0x700c0
2671#define _CURBBASE 0x700c4
2672#define _CURBPOS 0x700c8
Jesse Barnes585fb112008-07-29 11:54:06 -07002673
Jesse Barnes65a21cd2011-10-12 11:10:21 -07002674#define _CURBCNTR_IVB 0x71080
2675#define _CURBBASE_IVB 0x71084
2676#define _CURBPOS_IVB 0x71088
2677
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002678#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2679#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2680#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00002681
Jesse Barnes65a21cd2011-10-12 11:10:21 -07002682#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
2683#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
2684#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
2685
Jesse Barnes585fb112008-07-29 11:54:06 -07002686/* Display A control */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002687#define _DSPACNTR 0x70180
Jesse Barnes585fb112008-07-29 11:54:06 -07002688#define DISPLAY_PLANE_ENABLE (1<<31)
2689#define DISPLAY_PLANE_DISABLE 0
2690#define DISPPLANE_GAMMA_ENABLE (1<<30)
2691#define DISPPLANE_GAMMA_DISABLE 0
2692#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2693#define DISPPLANE_8BPP (0x2<<26)
2694#define DISPPLANE_15_16BPP (0x4<<26)
2695#define DISPPLANE_16BPP (0x5<<26)
2696#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2697#define DISPPLANE_32BPP (0x7<<26)
Kristian Høgsberga4f45cf2009-10-19 14:35:30 -04002698#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
Jesse Barnes585fb112008-07-29 11:54:06 -07002699#define DISPPLANE_STEREO_ENABLE (1<<25)
2700#define DISPPLANE_STEREO_DISABLE 0
Jesse Barnesb24e7172011-01-04 15:09:30 -08002701#define DISPPLANE_SEL_PIPE_SHIFT 24
2702#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07002703#define DISPPLANE_SEL_PIPE_A 0
Jesse Barnesb24e7172011-01-04 15:09:30 -08002704#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
Jesse Barnes585fb112008-07-29 11:54:06 -07002705#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2706#define DISPPLANE_SRC_KEY_DISABLE 0
2707#define DISPPLANE_LINE_DOUBLE (1<<20)
2708#define DISPPLANE_NO_LINE_DOUBLE 0
2709#define DISPPLANE_STEREO_POLARITY_FIRST 0
2710#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002711#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
Jesse Barnesf5448472009-04-14 14:17:47 -07002712#define DISPPLANE_TILED (1<<10)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002713#define _DSPAADDR 0x70184
2714#define _DSPASTRIDE 0x70188
2715#define _DSPAPOS 0x7018C /* reserved */
2716#define _DSPASIZE 0x70190
2717#define _DSPASURF 0x7019C /* 965+ only */
2718#define _DSPATILEOFF 0x701A4 /* 965+ only */
Jesse Barnes585fb112008-07-29 11:54:06 -07002719
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002720#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2721#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2722#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2723#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2724#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2725#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2726#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
Chris Wilson5eddb702010-09-11 13:48:45 +01002727
Jesse Barnes585fb112008-07-29 11:54:06 -07002728/* VBIOS flags */
2729#define SWF00 0x71410
2730#define SWF01 0x71414
2731#define SWF02 0x71418
2732#define SWF03 0x7141c
2733#define SWF04 0x71420
2734#define SWF05 0x71424
2735#define SWF06 0x71428
2736#define SWF10 0x70410
2737#define SWF11 0x70414
2738#define SWF14 0x71420
2739#define SWF30 0x72414
2740#define SWF31 0x72418
2741#define SWF32 0x7241c
2742
2743/* Pipe B */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002744#define _PIPEBDSL 0x71000
2745#define _PIPEBCONF 0x71008
2746#define _PIPEBSTAT 0x71024
2747#define _PIPEBFRAMEHIGH 0x71040
2748#define _PIPEBFRAMEPIXEL 0x71044
2749#define _PIPEB_FRMCOUNT_GM45 0x71040
2750#define _PIPEB_FLIPCOUNT_GM45 0x71044
Jesse Barnes9880b7a2009-02-06 10:22:41 -08002751
Jesse Barnes585fb112008-07-29 11:54:06 -07002752
2753/* Display B control */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002754#define _DSPBCNTR 0x71180
Jesse Barnes585fb112008-07-29 11:54:06 -07002755#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2756#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2757#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2758#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002759#define _DSPBADDR 0x71184
2760#define _DSPBSTRIDE 0x71188
2761#define _DSPBPOS 0x7118C
2762#define _DSPBSIZE 0x71190
2763#define _DSPBSURF 0x7119C
2764#define _DSPBTILEOFF 0x711A4
Jesse Barnes585fb112008-07-29 11:54:06 -07002765
Jesse Barnesb840d907f2011-12-13 13:19:38 -08002766/* Sprite A control */
2767#define _DVSACNTR 0x72180
2768#define DVS_ENABLE (1<<31)
2769#define DVS_GAMMA_ENABLE (1<<30)
2770#define DVS_PIXFORMAT_MASK (3<<25)
2771#define DVS_FORMAT_YUV422 (0<<25)
2772#define DVS_FORMAT_RGBX101010 (1<<25)
2773#define DVS_FORMAT_RGBX888 (2<<25)
2774#define DVS_FORMAT_RGBX161616 (3<<25)
2775#define DVS_SOURCE_KEY (1<<22)
Jesse Barnesab2f9df2012-02-27 12:40:10 -08002776#define DVS_RGB_ORDER_XBGR (1<<20)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08002777#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
2778#define DVS_YUV_ORDER_YUYV (0<<16)
2779#define DVS_YUV_ORDER_UYVY (1<<16)
2780#define DVS_YUV_ORDER_YVYU (2<<16)
2781#define DVS_YUV_ORDER_VYUY (3<<16)
2782#define DVS_DEST_KEY (1<<2)
2783#define DVS_TRICKLE_FEED_DISABLE (1<<14)
2784#define DVS_TILED (1<<10)
2785#define _DVSALINOFF 0x72184
2786#define _DVSASTRIDE 0x72188
2787#define _DVSAPOS 0x7218c
2788#define _DVSASIZE 0x72190
2789#define _DVSAKEYVAL 0x72194
2790#define _DVSAKEYMSK 0x72198
2791#define _DVSASURF 0x7219c
2792#define _DVSAKEYMAXVAL 0x721a0
2793#define _DVSATILEOFF 0x721a4
2794#define _DVSASURFLIVE 0x721ac
2795#define _DVSASCALE 0x72204
2796#define DVS_SCALE_ENABLE (1<<31)
2797#define DVS_FILTER_MASK (3<<29)
2798#define DVS_FILTER_MEDIUM (0<<29)
2799#define DVS_FILTER_ENHANCING (1<<29)
2800#define DVS_FILTER_SOFTENING (2<<29)
2801#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
2802#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
2803#define _DVSAGAMC 0x72300
2804
2805#define _DVSBCNTR 0x73180
2806#define _DVSBLINOFF 0x73184
2807#define _DVSBSTRIDE 0x73188
2808#define _DVSBPOS 0x7318c
2809#define _DVSBSIZE 0x73190
2810#define _DVSBKEYVAL 0x73194
2811#define _DVSBKEYMSK 0x73198
2812#define _DVSBSURF 0x7319c
2813#define _DVSBKEYMAXVAL 0x731a0
2814#define _DVSBTILEOFF 0x731a4
2815#define _DVSBSURFLIVE 0x731ac
2816#define _DVSBSCALE 0x73204
2817#define _DVSBGAMC 0x73300
2818
2819#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
2820#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
2821#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
2822#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
2823#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08002824#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08002825#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
2826#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
2827#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
Jesse Barnes8ea30862012-01-03 08:05:39 -08002828#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
2829#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08002830
2831#define _SPRA_CTL 0x70280
2832#define SPRITE_ENABLE (1<<31)
2833#define SPRITE_GAMMA_ENABLE (1<<30)
2834#define SPRITE_PIXFORMAT_MASK (7<<25)
2835#define SPRITE_FORMAT_YUV422 (0<<25)
2836#define SPRITE_FORMAT_RGBX101010 (1<<25)
2837#define SPRITE_FORMAT_RGBX888 (2<<25)
2838#define SPRITE_FORMAT_RGBX161616 (3<<25)
2839#define SPRITE_FORMAT_YUV444 (4<<25)
2840#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
2841#define SPRITE_CSC_ENABLE (1<<24)
2842#define SPRITE_SOURCE_KEY (1<<22)
2843#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
2844#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
2845#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
2846#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
2847#define SPRITE_YUV_ORDER_YUYV (0<<16)
2848#define SPRITE_YUV_ORDER_UYVY (1<<16)
2849#define SPRITE_YUV_ORDER_YVYU (2<<16)
2850#define SPRITE_YUV_ORDER_VYUY (3<<16)
2851#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
2852#define SPRITE_INT_GAMMA_ENABLE (1<<13)
2853#define SPRITE_TILED (1<<10)
2854#define SPRITE_DEST_KEY (1<<2)
2855#define _SPRA_LINOFF 0x70284
2856#define _SPRA_STRIDE 0x70288
2857#define _SPRA_POS 0x7028c
2858#define _SPRA_SIZE 0x70290
2859#define _SPRA_KEYVAL 0x70294
2860#define _SPRA_KEYMSK 0x70298
2861#define _SPRA_SURF 0x7029c
2862#define _SPRA_KEYMAX 0x702a0
2863#define _SPRA_TILEOFF 0x702a4
2864#define _SPRA_SCALE 0x70304
2865#define SPRITE_SCALE_ENABLE (1<<31)
2866#define SPRITE_FILTER_MASK (3<<29)
2867#define SPRITE_FILTER_MEDIUM (0<<29)
2868#define SPRITE_FILTER_ENHANCING (1<<29)
2869#define SPRITE_FILTER_SOFTENING (2<<29)
2870#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
2871#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
2872#define _SPRA_GAMC 0x70400
2873
2874#define _SPRB_CTL 0x71280
2875#define _SPRB_LINOFF 0x71284
2876#define _SPRB_STRIDE 0x71288
2877#define _SPRB_POS 0x7128c
2878#define _SPRB_SIZE 0x71290
2879#define _SPRB_KEYVAL 0x71294
2880#define _SPRB_KEYMSK 0x71298
2881#define _SPRB_SURF 0x7129c
2882#define _SPRB_KEYMAX 0x712a0
2883#define _SPRB_TILEOFF 0x712a4
2884#define _SPRB_SCALE 0x71304
2885#define _SPRB_GAMC 0x71400
2886
2887#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
2888#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
2889#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
2890#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
2891#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
2892#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
2893#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
2894#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
2895#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
2896#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
2897#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
2898#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
2899
Jesse Barnes585fb112008-07-29 11:54:06 -07002900/* VBIOS regs */
2901#define VGACNTRL 0x71400
2902# define VGA_DISP_DISABLE (1 << 31)
2903# define VGA_2X_MODE (1 << 30)
2904# define VGA_PIPE_B_SELECT (1 << 29)
2905
Adam Jacksonf2b115e2009-12-03 17:14:42 -05002906/* Ironlake */
Zhenyu Wangb9055052009-06-05 15:38:38 +08002907
2908#define CPU_VGACNTRL 0x41000
2909
2910#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2911#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2912#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2913#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2914#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2915#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2916#define DIGITAL_PORTA_NO_DETECT (0 << 0)
2917#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2918#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2919
2920/* refresh rate hardware control */
2921#define RR_HW_CTL 0x45300
2922#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2923#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2924
2925#define FDI_PLL_BIOS_0 0x46000
Chris Wilson021357a2010-09-07 20:54:59 +01002926#define FDI_PLL_FB_CLOCK_MASK 0xff
Zhenyu Wangb9055052009-06-05 15:38:38 +08002927#define FDI_PLL_BIOS_1 0x46004
2928#define FDI_PLL_BIOS_2 0x46008
2929#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2930#define DISPLAY_PORT_PLL_BIOS_1 0x46010
2931#define DISPLAY_PORT_PLL_BIOS_2 0x46014
2932
Eric Anholt8956c8b2010-03-18 13:21:14 -07002933#define PCH_DSPCLK_GATE_D 0x42020
Jesse Barnes1ffa3252011-01-17 13:35:57 -08002934# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2935# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
Eric Anholt8956c8b2010-03-18 13:21:14 -07002936# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2937# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2938
2939#define PCH_3DCGDIS0 0x46020
2940# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2941# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2942
Eric Anholt06f37752010-12-14 10:06:46 -08002943#define PCH_3DCGDIS1 0x46024
2944# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2945
Zhenyu Wangb9055052009-06-05 15:38:38 +08002946#define FDI_PLL_FREQ_CTL 0x46030
2947#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2948#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2949#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2950
2951
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002952#define _PIPEA_DATA_M1 0x60030
Zhenyu Wangb9055052009-06-05 15:38:38 +08002953#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2954#define TU_SIZE_MASK 0x7e000000
Chris Wilson5eddb702010-09-11 13:48:45 +01002955#define PIPE_DATA_M1_OFFSET 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002956#define _PIPEA_DATA_N1 0x60034
Chris Wilson5eddb702010-09-11 13:48:45 +01002957#define PIPE_DATA_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08002958
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002959#define _PIPEA_DATA_M2 0x60038
Chris Wilson5eddb702010-09-11 13:48:45 +01002960#define PIPE_DATA_M2_OFFSET 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002961#define _PIPEA_DATA_N2 0x6003c
Chris Wilson5eddb702010-09-11 13:48:45 +01002962#define PIPE_DATA_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08002963
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002964#define _PIPEA_LINK_M1 0x60040
Chris Wilson5eddb702010-09-11 13:48:45 +01002965#define PIPE_LINK_M1_OFFSET 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002966#define _PIPEA_LINK_N1 0x60044
Chris Wilson5eddb702010-09-11 13:48:45 +01002967#define PIPE_LINK_N1_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08002968
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002969#define _PIPEA_LINK_M2 0x60048
Chris Wilson5eddb702010-09-11 13:48:45 +01002970#define PIPE_LINK_M2_OFFSET 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002971#define _PIPEA_LINK_N2 0x6004c
Chris Wilson5eddb702010-09-11 13:48:45 +01002972#define PIPE_LINK_N2_OFFSET 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08002973
2974/* PIPEB timing regs are same start from 0x61000 */
2975
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002976#define _PIPEB_DATA_M1 0x61030
2977#define _PIPEB_DATA_N1 0x61034
Zhenyu Wangb9055052009-06-05 15:38:38 +08002978
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002979#define _PIPEB_DATA_M2 0x61038
2980#define _PIPEB_DATA_N2 0x6103c
Zhenyu Wangb9055052009-06-05 15:38:38 +08002981
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002982#define _PIPEB_LINK_M1 0x61040
2983#define _PIPEB_LINK_N1 0x61044
Zhenyu Wangb9055052009-06-05 15:38:38 +08002984
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002985#define _PIPEB_LINK_M2 0x61048
2986#define _PIPEB_LINK_N2 0x6104c
Chris Wilson5eddb702010-09-11 13:48:45 +01002987
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002988#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2989#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2990#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2991#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2992#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2993#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2994#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2995#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08002996
2997/* CPU panel fitter */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002998/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2999#define _PFA_CTL_1 0x68080
3000#define _PFB_CTL_1 0x68880
Zhenyu Wangb9055052009-06-05 15:38:38 +08003001#define PF_ENABLE (1<<31)
Zhenyu Wangb1f60b72009-10-19 15:43:49 +08003002#define PF_FILTER_MASK (3<<23)
3003#define PF_FILTER_PROGRAMMED (0<<23)
3004#define PF_FILTER_MED_3x3 (1<<23)
3005#define PF_FILTER_EDGE_ENHANCE (2<<23)
3006#define PF_FILTER_EDGE_SOFTEN (3<<23)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003007#define _PFA_WIN_SZ 0x68074
3008#define _PFB_WIN_SZ 0x68874
3009#define _PFA_WIN_POS 0x68070
3010#define _PFB_WIN_POS 0x68870
3011#define _PFA_VSCALE 0x68084
3012#define _PFB_VSCALE 0x68884
3013#define _PFA_HSCALE 0x68090
3014#define _PFB_HSCALE 0x68890
3015
3016#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
3017#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
3018#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
3019#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
3020#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003021
3022/* legacy palette */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003023#define _LGC_PALETTE_A 0x4a000
3024#define _LGC_PALETTE_B 0x4a800
3025#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003026
3027/* interrupts */
3028#define DE_MASTER_IRQ_CONTROL (1 << 31)
3029#define DE_SPRITEB_FLIP_DONE (1 << 29)
3030#define DE_SPRITEA_FLIP_DONE (1 << 28)
3031#define DE_PLANEB_FLIP_DONE (1 << 27)
3032#define DE_PLANEA_FLIP_DONE (1 << 26)
3033#define DE_PCU_EVENT (1 << 25)
3034#define DE_GTT_FAULT (1 << 24)
3035#define DE_POISON (1 << 23)
3036#define DE_PERFORM_COUNTER (1 << 22)
3037#define DE_PCH_EVENT (1 << 21)
3038#define DE_AUX_CHANNEL_A (1 << 20)
3039#define DE_DP_A_HOTPLUG (1 << 19)
3040#define DE_GSE (1 << 18)
3041#define DE_PIPEB_VBLANK (1 << 15)
3042#define DE_PIPEB_EVEN_FIELD (1 << 14)
3043#define DE_PIPEB_ODD_FIELD (1 << 13)
3044#define DE_PIPEB_LINE_COMPARE (1 << 12)
3045#define DE_PIPEB_VSYNC (1 << 11)
3046#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3047#define DE_PIPEA_VBLANK (1 << 7)
3048#define DE_PIPEA_EVEN_FIELD (1 << 6)
3049#define DE_PIPEA_ODD_FIELD (1 << 5)
3050#define DE_PIPEA_LINE_COMPARE (1 << 4)
3051#define DE_PIPEA_VSYNC (1 << 3)
3052#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3053
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07003054/* More Ivybridge lolz */
3055#define DE_ERR_DEBUG_IVB (1<<30)
3056#define DE_GSE_IVB (1<<29)
3057#define DE_PCH_EVENT_IVB (1<<28)
3058#define DE_DP_A_HOTPLUG_IVB (1<<27)
3059#define DE_AUX_CHANNEL_A_IVB (1<<26)
3060#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
3061#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
3062#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
3063#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
3064#define DE_PIPEB_VBLANK_IVB (1<<5)
3065#define DE_PIPEA_VBLANK_IVB (1<<0)
3066
Zhenyu Wangb9055052009-06-05 15:38:38 +08003067#define DEISR 0x44000
3068#define DEIMR 0x44004
3069#define DEIIR 0x44008
3070#define DEIER 0x4400c
3071
3072/* GT interrupt */
Jesse Barnese552eb72010-04-21 11:39:23 -07003073#define GT_PIPE_NOTIFY (1 << 4)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003074#define GT_SYNC_STATUS (1 << 2)
3075#define GT_USER_INTERRUPT (1 << 0)
Zou Nan haid1b851f2010-05-21 09:08:57 +08003076#define GT_BSD_USER_INTERRUPT (1 << 5)
Xiang, Haihao881f47b2010-09-19 14:40:43 +01003077#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
Chris Wilson549f7362010-10-19 11:19:32 +01003078#define GT_BLT_USER_INTERRUPT (1 << 22)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003079
3080#define GTISR 0x44010
3081#define GTIMR 0x44014
3082#define GTIIR 0x44018
3083#define GTIER 0x4401c
3084
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003085#define ILK_DISPLAY_CHICKEN2 0x42004
Eric Anholt67e92af2010-11-06 14:53:33 -07003086/* Required on all Ironlake and Sandybridge according to the B-Spec. */
3087#define ILK_ELPIN_409_SELECT (1 << 25)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003088#define ILK_DPARB_GATE (1<<22)
3089#define ILK_VSDPFD_FULL (1<<21)
Chris Wilson4d302442010-12-14 19:21:29 +00003090#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
3091#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
3092#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
3093#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
3094#define ILK_HDCP_DISABLE (1<<25)
3095#define ILK_eDP_A_DISABLE (1<<24)
3096#define ILK_DESKTOP (1<<23)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003097#define ILK_DSPCLK_GATE 0x42020
Jesse Barnes28963a32011-05-11 09:42:30 -07003098#define IVB_VRHUNIT_CLK_GATE (1<<28)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003099#define ILK_DPARB_CLK_GATE (1<<5)
Yuanhan Liu13982612010-12-15 15:42:31 +08003100#define ILK_DPFD_CLK_GATE (1<<7)
3101
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08003102/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
3103#define ILK_CLK_FBC (1<<7)
3104#define ILK_DPFC_DIS1 (1<<8)
3105#define ILK_DPFC_DIS2 (1<<9)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003106
Eric Anholt116ac8d2011-12-21 10:31:09 -08003107#define IVB_CHICKEN3 0x4200c
3108# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
3109# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
3110
Zhenyu Wang553bd142009-09-02 10:57:52 +08003111#define DISP_ARB_CTL 0x45000
3112#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003113#define DISP_FBC_WM_DIS (1<<15)
Zhenyu Wang553bd142009-09-02 10:57:52 +08003114
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08003115/* GEN7 chicken */
Kenneth Graunked71de142012-02-08 12:53:52 -08003116#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
3117# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
3118
Eugeni Dodonove4e0c052012-02-08 12:53:50 -08003119#define GEN7_L3CNTLREG1 0xB01C
3120#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
3121
3122#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
3123#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
3124
Eugeni Dodonovdb099c82012-02-08 12:53:51 -08003125/* WaCatErrorRejectionIssue */
3126#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
3127#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
3128
Zhenyu Wangb9055052009-06-05 15:38:38 +08003129/* PCH */
3130
3131/* south display engine interrupt */
Jesse Barnes776ad802011-01-04 15:09:39 -08003132#define SDE_AUDIO_POWER_D (1 << 27)
3133#define SDE_AUDIO_POWER_C (1 << 26)
3134#define SDE_AUDIO_POWER_B (1 << 25)
3135#define SDE_AUDIO_POWER_SHIFT (25)
3136#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
3137#define SDE_GMBUS (1 << 24)
3138#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
3139#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
3140#define SDE_AUDIO_HDCP_MASK (3 << 22)
3141#define SDE_AUDIO_TRANSB (1 << 21)
3142#define SDE_AUDIO_TRANSA (1 << 20)
3143#define SDE_AUDIO_TRANS_MASK (3 << 20)
3144#define SDE_POISON (1 << 19)
3145/* 18 reserved */
3146#define SDE_FDI_RXB (1 << 17)
3147#define SDE_FDI_RXA (1 << 16)
3148#define SDE_FDI_MASK (3 << 16)
3149#define SDE_AUXD (1 << 15)
3150#define SDE_AUXC (1 << 14)
3151#define SDE_AUXB (1 << 13)
3152#define SDE_AUX_MASK (7 << 13)
3153/* 12 reserved */
Zhenyu Wangb9055052009-06-05 15:38:38 +08003154#define SDE_CRT_HOTPLUG (1 << 11)
3155#define SDE_PORTD_HOTPLUG (1 << 10)
3156#define SDE_PORTC_HOTPLUG (1 << 9)
3157#define SDE_PORTB_HOTPLUG (1 << 8)
3158#define SDE_SDVOB_HOTPLUG (1 << 6)
Zhenyu Wangc6501562009-11-03 18:57:21 +00003159#define SDE_HOTPLUG_MASK (0xf << 8)
Jesse Barnes776ad802011-01-04 15:09:39 -08003160#define SDE_TRANSB_CRC_DONE (1 << 5)
3161#define SDE_TRANSB_CRC_ERR (1 << 4)
3162#define SDE_TRANSB_FIFO_UNDER (1 << 3)
3163#define SDE_TRANSA_CRC_DONE (1 << 2)
3164#define SDE_TRANSA_CRC_ERR (1 << 1)
3165#define SDE_TRANSA_FIFO_UNDER (1 << 0)
3166#define SDE_TRANS_MASK (0x3f)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003167/* CPT */
3168#define SDE_CRT_HOTPLUG_CPT (1 << 19)
3169#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3170#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3171#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
Yuanhan Liu2d7b8362010-10-08 10:21:06 +01003172#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3173 SDE_PORTD_HOTPLUG_CPT | \
3174 SDE_PORTC_HOTPLUG_CPT | \
3175 SDE_PORTB_HOTPLUG_CPT)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003176
3177#define SDEISR 0xc4000
3178#define SDEIMR 0xc4004
3179#define SDEIIR 0xc4008
3180#define SDEIER 0xc400c
3181
3182/* digital port hotplug */
Keith Packard7fe0b972011-09-19 13:31:02 -07003183#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
Zhenyu Wangb9055052009-06-05 15:38:38 +08003184#define PORTD_HOTPLUG_ENABLE (1 << 20)
3185#define PORTD_PULSE_DURATION_2ms (0)
3186#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
3187#define PORTD_PULSE_DURATION_6ms (2 << 18)
3188#define PORTD_PULSE_DURATION_100ms (3 << 18)
Keith Packard7fe0b972011-09-19 13:31:02 -07003189#define PORTD_PULSE_DURATION_MASK (3 << 18)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003190#define PORTD_HOTPLUG_NO_DETECT (0)
3191#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3192#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
3193#define PORTC_HOTPLUG_ENABLE (1 << 12)
3194#define PORTC_PULSE_DURATION_2ms (0)
3195#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
3196#define PORTC_PULSE_DURATION_6ms (2 << 10)
3197#define PORTC_PULSE_DURATION_100ms (3 << 10)
Keith Packard7fe0b972011-09-19 13:31:02 -07003198#define PORTC_PULSE_DURATION_MASK (3 << 10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003199#define PORTC_HOTPLUG_NO_DETECT (0)
3200#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3201#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
3202#define PORTB_HOTPLUG_ENABLE (1 << 4)
3203#define PORTB_PULSE_DURATION_2ms (0)
3204#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
3205#define PORTB_PULSE_DURATION_6ms (2 << 2)
3206#define PORTB_PULSE_DURATION_100ms (3 << 2)
Keith Packard7fe0b972011-09-19 13:31:02 -07003207#define PORTB_PULSE_DURATION_MASK (3 << 2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003208#define PORTB_HOTPLUG_NO_DETECT (0)
3209#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3210#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
3211
3212#define PCH_GPIOA 0xc5010
3213#define PCH_GPIOB 0xc5014
3214#define PCH_GPIOC 0xc5018
3215#define PCH_GPIOD 0xc501c
3216#define PCH_GPIOE 0xc5020
3217#define PCH_GPIOF 0xc5024
3218
Eric Anholtf0217c42009-12-01 11:56:30 -08003219#define PCH_GMBUS0 0xc5100
3220#define PCH_GMBUS1 0xc5104
3221#define PCH_GMBUS2 0xc5108
3222#define PCH_GMBUS3 0xc510c
3223#define PCH_GMBUS4 0xc5110
3224#define PCH_GMBUS5 0xc5120
3225
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003226#define _PCH_DPLL_A 0xc6014
3227#define _PCH_DPLL_B 0xc6018
Jesse Barnes4c609cb2011-09-02 12:52:11 -07003228#define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003229
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003230#define _PCH_FPA0 0xc6040
Chris Wilsonc1858122010-12-03 21:35:48 +00003231#define FP_CB_TUNE (0x3<<22)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003232#define _PCH_FPA1 0xc6044
3233#define _PCH_FPB0 0xc6048
3234#define _PCH_FPB1 0xc604c
Jesse Barnes4c609cb2011-09-02 12:52:11 -07003235#define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0)
3236#define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003237
3238#define PCH_DPLL_TEST 0xc606c
3239
3240#define PCH_DREF_CONTROL 0xC6200
3241#define DREF_CONTROL_MASK 0x7fc3
3242#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
3243#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
3244#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
3245#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
3246#define DREF_SSC_SOURCE_DISABLE (0<<11)
3247#define DREF_SSC_SOURCE_ENABLE (2<<11)
Zhenyu Wangc038e512009-10-19 15:43:48 +08003248#define DREF_SSC_SOURCE_MASK (3<<11)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003249#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
3250#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
3251#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
Zhenyu Wangc038e512009-10-19 15:43:48 +08003252#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003253#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
3254#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
Jesse Barnes92f25842011-01-04 15:09:34 -08003255#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003256#define DREF_SSC4_DOWNSPREAD (0<<6)
3257#define DREF_SSC4_CENTERSPREAD (1<<6)
3258#define DREF_SSC1_DISABLE (0<<1)
3259#define DREF_SSC1_ENABLE (1<<1)
3260#define DREF_SSC4_DISABLE (0)
3261#define DREF_SSC4_ENABLE (1)
3262
3263#define PCH_RAWCLK_FREQ 0xc6204
3264#define FDL_TP1_TIMER_SHIFT 12
3265#define FDL_TP1_TIMER_MASK (3<<12)
3266#define FDL_TP2_TIMER_SHIFT 10
3267#define FDL_TP2_TIMER_MASK (3<<10)
3268#define RAWCLK_FREQ_MASK 0x3ff
3269
3270#define PCH_DPLL_TMR_CFG 0xc6208
3271
3272#define PCH_SSC4_PARMS 0xc6210
3273#define PCH_SSC4_AUX_PARMS 0xc6214
3274
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003275#define PCH_DPLL_SEL 0xc7000
3276#define TRANSA_DPLL_ENABLE (1<<3)
3277#define TRANSA_DPLLB_SEL (1<<0)
3278#define TRANSA_DPLLA_SEL 0
3279#define TRANSB_DPLL_ENABLE (1<<7)
3280#define TRANSB_DPLLB_SEL (1<<4)
3281#define TRANSB_DPLLA_SEL (0)
3282#define TRANSC_DPLL_ENABLE (1<<11)
3283#define TRANSC_DPLLB_SEL (1<<8)
3284#define TRANSC_DPLLA_SEL (0)
3285
Zhenyu Wangb9055052009-06-05 15:38:38 +08003286/* transcoder */
3287
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003288#define _TRANS_HTOTAL_A 0xe0000
Zhenyu Wangb9055052009-06-05 15:38:38 +08003289#define TRANS_HTOTAL_SHIFT 16
3290#define TRANS_HACTIVE_SHIFT 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003291#define _TRANS_HBLANK_A 0xe0004
Zhenyu Wangb9055052009-06-05 15:38:38 +08003292#define TRANS_HBLANK_END_SHIFT 16
3293#define TRANS_HBLANK_START_SHIFT 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003294#define _TRANS_HSYNC_A 0xe0008
Zhenyu Wangb9055052009-06-05 15:38:38 +08003295#define TRANS_HSYNC_END_SHIFT 16
3296#define TRANS_HSYNC_START_SHIFT 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003297#define _TRANS_VTOTAL_A 0xe000c
Zhenyu Wangb9055052009-06-05 15:38:38 +08003298#define TRANS_VTOTAL_SHIFT 16
3299#define TRANS_VACTIVE_SHIFT 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003300#define _TRANS_VBLANK_A 0xe0010
Zhenyu Wangb9055052009-06-05 15:38:38 +08003301#define TRANS_VBLANK_END_SHIFT 16
3302#define TRANS_VBLANK_START_SHIFT 0
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003303#define _TRANS_VSYNC_A 0xe0014
Zhenyu Wangb9055052009-06-05 15:38:38 +08003304#define TRANS_VSYNC_END_SHIFT 16
3305#define TRANS_VSYNC_START_SHIFT 0
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003306#define _TRANS_VSYNCSHIFT_A 0xe0028
Zhenyu Wangb9055052009-06-05 15:38:38 +08003307
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003308#define _TRANSA_DATA_M1 0xe0030
3309#define _TRANSA_DATA_N1 0xe0034
3310#define _TRANSA_DATA_M2 0xe0038
3311#define _TRANSA_DATA_N2 0xe003c
3312#define _TRANSA_DP_LINK_M1 0xe0040
3313#define _TRANSA_DP_LINK_N1 0xe0044
3314#define _TRANSA_DP_LINK_M2 0xe0048
3315#define _TRANSA_DP_LINK_N2 0xe004c
Zhenyu Wangb9055052009-06-05 15:38:38 +08003316
Jesse Barnesb055c8f2011-07-08 11:31:57 -07003317/* Per-transcoder DIP controls */
3318
3319#define _VIDEO_DIP_CTL_A 0xe0200
3320#define _VIDEO_DIP_DATA_A 0xe0208
3321#define _VIDEO_DIP_GCP_A 0xe0210
3322
3323#define _VIDEO_DIP_CTL_B 0xe1200
3324#define _VIDEO_DIP_DATA_B 0xe1208
3325#define _VIDEO_DIP_GCP_B 0xe1210
3326
3327#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3328#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3329#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3330
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003331#define _TRANS_HTOTAL_B 0xe1000
3332#define _TRANS_HBLANK_B 0xe1004
3333#define _TRANS_HSYNC_B 0xe1008
3334#define _TRANS_VTOTAL_B 0xe100c
3335#define _TRANS_VBLANK_B 0xe1010
3336#define _TRANS_VSYNC_B 0xe1014
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003337#define _TRANS_VSYNCSHIFT_B 0xe1028
Zhenyu Wangb9055052009-06-05 15:38:38 +08003338
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003339#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3340#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3341#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3342#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3343#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3344#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003345#define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
3346 _TRANS_VSYNCSHIFT_B)
Chris Wilson5eddb702010-09-11 13:48:45 +01003347
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003348#define _TRANSB_DATA_M1 0xe1030
3349#define _TRANSB_DATA_N1 0xe1034
3350#define _TRANSB_DATA_M2 0xe1038
3351#define _TRANSB_DATA_N2 0xe103c
3352#define _TRANSB_DP_LINK_M1 0xe1040
3353#define _TRANSB_DP_LINK_N1 0xe1044
3354#define _TRANSB_DP_LINK_M2 0xe1048
3355#define _TRANSB_DP_LINK_N2 0xe104c
Zhenyu Wangb9055052009-06-05 15:38:38 +08003356
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003357#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3358#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3359#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3360#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3361#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3362#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3363#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3364#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3365
3366#define _TRANSACONF 0xf0008
3367#define _TRANSBCONF 0xf1008
3368#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003369#define TRANS_DISABLE (0<<31)
3370#define TRANS_ENABLE (1<<31)
3371#define TRANS_STATE_MASK (1<<30)
3372#define TRANS_STATE_DISABLE (0<<30)
3373#define TRANS_STATE_ENABLE (1<<30)
3374#define TRANS_FSYNC_DELAY_HB1 (0<<27)
3375#define TRANS_FSYNC_DELAY_HB2 (1<<27)
3376#define TRANS_FSYNC_DELAY_HB3 (2<<27)
3377#define TRANS_FSYNC_DELAY_HB4 (3<<27)
3378#define TRANS_DP_AUDIO_ONLY (1<<26)
3379#define TRANS_DP_VIDEO_AUDIO (0<<26)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02003380#define TRANS_INTERLACE_MASK (7<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003381#define TRANS_PROGRESSIVE (0<<21)
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02003382#define TRANS_INTERLACED (3<<21)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02003383#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003384#define TRANS_8BPC (0<<5)
3385#define TRANS_10BPC (1<<5)
3386#define TRANS_6BPC (2<<5)
3387#define TRANS_12BPC (3<<5)
3388
Jesse Barnes3bcf6032011-07-27 11:51:40 -07003389#define _TRANSA_CHICKEN2 0xf0064
3390#define _TRANSB_CHICKEN2 0xf1064
3391#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3392#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3393
Jesse Barnes291427f2011-07-29 12:42:37 -07003394#define SOUTH_CHICKEN1 0xc2000
3395#define FDIA_PHASE_SYNC_SHIFT_OVR 19
3396#define FDIA_PHASE_SYNC_SHIFT_EN 18
3397#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3398#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
Jesse Barnes645c62a2011-05-11 09:49:31 -07003399#define SOUTH_CHICKEN2 0xc2004
3400#define DPLS_EDP_PPS_FIX_DIS (1<<0)
3401
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003402#define _FDI_RXA_CHICKEN 0xc200c
3403#define _FDI_RXB_CHICKEN 0xc2010
Jesse Barnes6f06ce12011-01-04 15:09:38 -08003404#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3405#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003406#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003407
Jesse Barnes382b0932010-10-07 16:01:25 -07003408#define SOUTH_DSPCLK_GATE_D 0xc2020
3409#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3410
Zhenyu Wangb9055052009-06-05 15:38:38 +08003411/* CPU: FDI_TX */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003412#define _FDI_TXA_CTL 0x60100
3413#define _FDI_TXB_CTL 0x61100
3414#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003415#define FDI_TX_DISABLE (0<<31)
3416#define FDI_TX_ENABLE (1<<31)
3417#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3418#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3419#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3420#define FDI_LINK_TRAIN_NONE (3<<28)
3421#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3422#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3423#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3424#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3425#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3426#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3427#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3428#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003429/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3430 SNB has different settings. */
3431/* SNB A-stepping */
3432#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3433#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3434#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3435#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3436/* SNB B-stepping */
3437#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3438#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3439#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3440#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3441#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003442#define FDI_DP_PORT_WIDTH_X1 (0<<19)
3443#define FDI_DP_PORT_WIDTH_X2 (1<<19)
3444#define FDI_DP_PORT_WIDTH_X3 (2<<19)
3445#define FDI_DP_PORT_WIDTH_X4 (3<<19)
3446#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003447/* Ironlake: hardwired to 1 */
Zhenyu Wangb9055052009-06-05 15:38:38 +08003448#define FDI_TX_PLL_ENABLE (1<<14)
Jesse Barnes357555c2011-04-28 15:09:55 -07003449
3450/* Ivybridge has different bits for lolz */
3451#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3452#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3453#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3454#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3455
Zhenyu Wangb9055052009-06-05 15:38:38 +08003456/* both Tx and Rx */
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07003457#define FDI_COMPOSITE_SYNC (1<<11)
Jesse Barnes357555c2011-04-28 15:09:55 -07003458#define FDI_LINK_TRAIN_AUTO (1<<10)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003459#define FDI_SCRAMBLING_ENABLE (0<<7)
3460#define FDI_SCRAMBLING_DISABLE (1<<7)
3461
3462/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003463#define _FDI_RXA_CTL 0xf000c
3464#define _FDI_RXB_CTL 0xf100c
3465#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003466#define FDI_RX_ENABLE (1<<31)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003467/* train, dp width same as FDI_TX */
Jesse Barnes357555c2011-04-28 15:09:55 -07003468#define FDI_FS_ERRC_ENABLE (1<<27)
3469#define FDI_FE_ERRC_ENABLE (1<<26)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003470#define FDI_DP_PORT_WIDTH_X8 (7<<19)
3471#define FDI_8BPC (0<<16)
3472#define FDI_10BPC (1<<16)
3473#define FDI_6BPC (2<<16)
3474#define FDI_12BPC (3<<16)
3475#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3476#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3477#define FDI_RX_PLL_ENABLE (1<<13)
3478#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3479#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3480#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3481#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3482#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
Chris Wilson5eddb702010-09-11 13:48:45 +01003483#define FDI_PCDCLK (1<<4)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003484/* CPT */
3485#define FDI_AUTO_TRAINING (1<<10)
3486#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3487#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3488#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3489#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3490#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003491
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003492#define _FDI_RXA_MISC 0xf0010
3493#define _FDI_RXB_MISC 0xf1010
3494#define _FDI_RXA_TUSIZE1 0xf0030
3495#define _FDI_RXA_TUSIZE2 0xf0038
3496#define _FDI_RXB_TUSIZE1 0xf1030
3497#define _FDI_RXB_TUSIZE2 0xf1038
3498#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3499#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3500#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003501
3502/* FDI_RX interrupt register format */
3503#define FDI_RX_INTER_LANE_ALIGN (1<<10)
3504#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3505#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3506#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3507#define FDI_RX_FS_CODE_ERR (1<<6)
3508#define FDI_RX_FE_CODE_ERR (1<<5)
3509#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3510#define FDI_RX_HDCP_LINK_FAIL (1<<3)
3511#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3512#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3513#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3514
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003515#define _FDI_RXA_IIR 0xf0014
3516#define _FDI_RXA_IMR 0xf0018
3517#define _FDI_RXB_IIR 0xf1014
3518#define _FDI_RXB_IMR 0xf1018
3519#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3520#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003521
3522#define FDI_PLL_CTL_1 0xfe000
3523#define FDI_PLL_CTL_2 0xfe004
3524
3525/* CRT */
3526#define PCH_ADPA 0xe1100
3527#define ADPA_TRANS_SELECT_MASK (1<<30)
3528#define ADPA_TRANS_A_SELECT 0
3529#define ADPA_TRANS_B_SELECT (1<<30)
3530#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3531#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3532#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3533#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3534#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3535#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3536#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3537#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3538#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3539#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3540#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3541#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3542#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3543#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3544#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3545#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3546#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3547#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3548#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3549
3550/* or SDVOB */
3551#define HDMIB 0xe1140
3552#define PORT_ENABLE (1 << 31)
Paulo Zanoni3573c412011-10-14 18:16:22 -03003553#define TRANSCODER(pipe) ((pipe) << 30)
3554#define TRANSCODER_CPT(pipe) ((pipe) << 29)
3555#define TRANSCODER_MASK (1 << 30)
3556#define TRANSCODER_MASK_CPT (3 << 29)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003557#define COLOR_FORMAT_8bpc (0)
3558#define COLOR_FORMAT_12bpc (3 << 26)
3559#define SDVOB_HOTPLUG_ENABLE (1 << 23)
3560#define SDVO_ENCODING (0)
3561#define TMDS_ENCODING (2 << 10)
3562#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
Zhenyu Wang467b2002010-05-12 11:02:14 +08003563/* CPT */
3564#define HDMI_MODE_SELECT (1 << 9)
3565#define DVI_MODE_SELECT (0)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003566#define SDVOB_BORDER_ENABLE (1 << 7)
3567#define AUDIO_ENABLE (1 << 6)
3568#define VSYNC_ACTIVE_HIGH (1 << 4)
3569#define HSYNC_ACTIVE_HIGH (1 << 3)
3570#define PORT_DETECTED (1 << 2)
3571
Zhao Yakui461ed3c2010-03-30 15:11:33 +08003572/* PCH SDVOB multiplex with HDMIB */
3573#define PCH_SDVOB HDMIB
3574
Zhenyu Wangb9055052009-06-05 15:38:38 +08003575#define HDMIC 0xe1150
3576#define HDMID 0xe1160
3577
3578#define PCH_LVDS 0xe1180
3579#define LVDS_DETECTED (1 << 1)
3580
3581#define BLC_PWM_CPU_CTL2 0x48250
3582#define PWM_ENABLE (1 << 31)
3583#define PWM_PIPE_A (0 << 29)
3584#define PWM_PIPE_B (1 << 29)
3585#define BLC_PWM_CPU_CTL 0x48254
3586
3587#define BLC_PWM_PCH_CTL1 0xc8250
3588#define PWM_PCH_ENABLE (1 << 31)
3589#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3590#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3591#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3592#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3593
3594#define BLC_PWM_PCH_CTL2 0xc8254
3595
3596#define PCH_PP_STATUS 0xc7200
3597#define PCH_PP_CONTROL 0xc7204
Jesse Barnes4a655f02010-07-22 13:18:18 -07003598#define PANEL_UNLOCK_REGS (0xabcd << 16)
Keith Packard1c0ae802011-09-19 13:59:29 -07003599#define PANEL_UNLOCK_MASK (0xffff << 16)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003600#define EDP_FORCE_VDD (1 << 3)
3601#define EDP_BLC_ENABLE (1 << 2)
3602#define PANEL_POWER_RESET (1 << 1)
3603#define PANEL_POWER_OFF (0 << 0)
3604#define PANEL_POWER_ON (1 << 0)
3605#define PCH_PP_ON_DELAYS 0xc7208
Keith Packardf01eca22011-09-28 16:48:10 -07003606#define PANEL_PORT_SELECT_MASK (3 << 30)
3607#define PANEL_PORT_SELECT_LVDS (0 << 30)
3608#define PANEL_PORT_SELECT_DPA (1 << 30)
Zhenyu Wangb9055052009-06-05 15:38:38 +08003609#define EDP_PANEL (1 << 30)
Keith Packardf01eca22011-09-28 16:48:10 -07003610#define PANEL_PORT_SELECT_DPC (2 << 30)
3611#define PANEL_PORT_SELECT_DPD (3 << 30)
3612#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
3613#define PANEL_POWER_UP_DELAY_SHIFT 16
3614#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
3615#define PANEL_LIGHT_ON_DELAY_SHIFT 0
3616
Zhenyu Wangb9055052009-06-05 15:38:38 +08003617#define PCH_PP_OFF_DELAYS 0xc720c
Keith Packardf01eca22011-09-28 16:48:10 -07003618#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
3619#define PANEL_POWER_DOWN_DELAY_SHIFT 16
3620#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
3621#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
3622
Zhenyu Wangb9055052009-06-05 15:38:38 +08003623#define PCH_PP_DIVISOR 0xc7210
Keith Packardf01eca22011-09-28 16:48:10 -07003624#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
3625#define PP_REFERENCE_DIVIDER_SHIFT 8
3626#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
3627#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
Zhenyu Wangb9055052009-06-05 15:38:38 +08003628
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003629#define PCH_DP_B 0xe4100
3630#define PCH_DPB_AUX_CH_CTL 0xe4110
3631#define PCH_DPB_AUX_CH_DATA1 0xe4114
3632#define PCH_DPB_AUX_CH_DATA2 0xe4118
3633#define PCH_DPB_AUX_CH_DATA3 0xe411c
3634#define PCH_DPB_AUX_CH_DATA4 0xe4120
3635#define PCH_DPB_AUX_CH_DATA5 0xe4124
3636
3637#define PCH_DP_C 0xe4200
3638#define PCH_DPC_AUX_CH_CTL 0xe4210
3639#define PCH_DPC_AUX_CH_DATA1 0xe4214
3640#define PCH_DPC_AUX_CH_DATA2 0xe4218
3641#define PCH_DPC_AUX_CH_DATA3 0xe421c
3642#define PCH_DPC_AUX_CH_DATA4 0xe4220
3643#define PCH_DPC_AUX_CH_DATA5 0xe4224
3644
3645#define PCH_DP_D 0xe4300
3646#define PCH_DPD_AUX_CH_CTL 0xe4310
3647#define PCH_DPD_AUX_CH_DATA1 0xe4314
3648#define PCH_DPD_AUX_CH_DATA2 0xe4318
3649#define PCH_DPD_AUX_CH_DATA3 0xe431c
3650#define PCH_DPD_AUX_CH_DATA4 0xe4320
3651#define PCH_DPD_AUX_CH_DATA5 0xe4324
3652
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003653/* CPT */
3654#define PORT_TRANS_A_SEL_CPT 0
3655#define PORT_TRANS_B_SEL_CPT (1<<29)
3656#define PORT_TRANS_C_SEL_CPT (2<<29)
3657#define PORT_TRANS_SEL_MASK (3<<29)
Keith Packard1519b992011-08-06 10:35:34 -07003658#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003659
3660#define TRANS_DP_CTL_A 0xe0300
3661#define TRANS_DP_CTL_B 0xe1300
3662#define TRANS_DP_CTL_C 0xe2300
Chris Wilson5eddb702010-09-11 13:48:45 +01003663#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003664#define TRANS_DP_OUTPUT_ENABLE (1<<31)
3665#define TRANS_DP_PORT_SEL_B (0<<29)
3666#define TRANS_DP_PORT_SEL_C (1<<29)
3667#define TRANS_DP_PORT_SEL_D (2<<29)
Eric Anholtcb3543c2011-02-02 12:08:07 -08003668#define TRANS_DP_PORT_SEL_NONE (3<<29)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003669#define TRANS_DP_PORT_SEL_MASK (3<<29)
3670#define TRANS_DP_AUDIO_ONLY (1<<26)
3671#define TRANS_DP_ENH_FRAMING (1<<18)
3672#define TRANS_DP_8BPC (0<<9)
3673#define TRANS_DP_10BPC (1<<9)
3674#define TRANS_DP_6BPC (2<<9)
3675#define TRANS_DP_12BPC (3<<9)
Eric Anholt220cad32010-11-18 09:32:58 +08003676#define TRANS_DP_BPC_MASK (3<<9)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003677#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3678#define TRANS_DP_VSYNC_ACTIVE_LOW 0
3679#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3680#define TRANS_DP_HSYNC_ACTIVE_LOW 0
Chris Wilson94113ce2010-08-04 11:25:21 +01003681#define TRANS_DP_SYNC_MASK (3<<3)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003682
3683/* SNB eDP training params */
3684/* SNB A-stepping */
3685#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3686#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3687#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3688#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3689/* SNB B-stepping */
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08003690#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
3691#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
3692#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
3693#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3694#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
Zhenyu Wang8db9d772010-04-07 16:15:54 +08003695#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3696
Keith Packard1a2eb462011-11-16 16:26:07 -08003697/* IVB */
3698#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
3699#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
3700#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
3701#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
3702#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
3703#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
3704#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x33 <<22)
3705
3706/* legacy values */
3707#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
3708#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
3709#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
3710#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
3711#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
3712
3713#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
3714
Zou Nan haicae58522010-11-09 17:17:32 +08003715#define FORCEWAKE 0xA18C
Chris Wilsoneb43f4a2010-12-08 17:32:24 +00003716#define FORCEWAKE_ACK 0x130090
Keith Packard8d715f02011-11-18 20:39:01 -08003717#define FORCEWAKE_MT 0xa188 /* multi-threaded */
3718#define FORCEWAKE_MT_ACK 0x130040
3719#define ECOBUS 0xa180
3720#define FORCEWAKE_MT_ENABLE (1<<5)
Chris Wilson8fd26852010-12-08 18:40:43 +00003721
Ben Widawskydd202c62012-02-09 10:15:18 +01003722#define GTFIFODBG 0x120000
3723#define GT_FIFO_CPU_ERROR_MASK 7
3724#define GT_FIFO_OVFERR (1<<2)
3725#define GT_FIFO_IAWRERR (1<<1)
3726#define GT_FIFO_IARDERR (1<<0)
3727
Chris Wilson91355832011-03-04 19:22:40 +00003728#define GT_FIFO_FREE_ENTRIES 0x120008
Chris Wilson957367202011-05-12 22:17:09 +01003729#define GT_FIFO_NUM_RESERVED_ENTRIES 20
Chris Wilson91355832011-03-04 19:22:40 +00003730
Daniel Vetter80e829f2012-03-31 11:21:57 +02003731#define GEN6_UCGCTL1 0x9400
3732# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
3733
Eric Anholt406478d2011-11-07 16:07:04 -08003734#define GEN6_UCGCTL2 0x9404
Eugeni Dodonoveae66b52012-02-08 12:53:49 -08003735# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
Eric Anholt406478d2011-11-07 16:07:04 -08003736# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
Eric Anholt9ca1d102011-11-07 16:07:05 -08003737# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
Eric Anholt406478d2011-11-07 16:07:04 -08003738
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08003739#define GEN6_RPNSWREQ 0xA008
Chris Wilson8fd26852010-12-08 18:40:43 +00003740#define GEN6_TURBO_DISABLE (1<<31)
3741#define GEN6_FREQUENCY(x) ((x)<<25)
3742#define GEN6_OFFSET(x) ((x)<<19)
3743#define GEN6_AGGRESSIVE_TURBO (0<<15)
3744#define GEN6_RC_VIDEO_FREQ 0xA00C
3745#define GEN6_RC_CONTROL 0xA090
3746#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3747#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3748#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3749#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3750#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3751#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3752#define GEN6_RC_CTL_HW_ENABLE (1<<31)
3753#define GEN6_RP_DOWN_TIMEOUT 0xA010
3754#define GEN6_RP_INTERRUPT_LIMITS 0xA014
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08003755#define GEN6_RPSTAT1 0xA01C
Jesse Barnesccab5c82011-01-18 15:49:25 -08003756#define GEN6_CAGF_SHIFT 8
3757#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
Chris Wilson8fd26852010-12-08 18:40:43 +00003758#define GEN6_RP_CONTROL 0xA024
3759#define GEN6_RP_MEDIA_TURBO (1<<11)
Ben Widawsky6ed55ee2011-12-12 19:21:59 -08003760#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
3761#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
3762#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
3763#define GEN6_RP_MEDIA_HW_MODE (1<<9)
3764#define GEN6_RP_MEDIA_SW_MODE (0<<9)
Chris Wilson8fd26852010-12-08 18:40:43 +00003765#define GEN6_RP_MEDIA_IS_GFX (1<<8)
3766#define GEN6_RP_ENABLE (1<<7)
Jesse Barnesccab5c82011-01-18 15:49:25 -08003767#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3768#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3769#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3770#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
Chris Wilson8fd26852010-12-08 18:40:43 +00003771#define GEN6_RP_UP_THRESHOLD 0xA02C
3772#define GEN6_RP_DOWN_THRESHOLD 0xA030
Jesse Barnesccab5c82011-01-18 15:49:25 -08003773#define GEN6_RP_CUR_UP_EI 0xA050
3774#define GEN6_CURICONT_MASK 0xffffff
3775#define GEN6_RP_CUR_UP 0xA054
3776#define GEN6_CURBSYTAVG_MASK 0xffffff
3777#define GEN6_RP_PREV_UP 0xA058
3778#define GEN6_RP_CUR_DOWN_EI 0xA05C
3779#define GEN6_CURIAVG_MASK 0xffffff
3780#define GEN6_RP_CUR_DOWN 0xA060
3781#define GEN6_RP_PREV_DOWN 0xA064
Chris Wilson8fd26852010-12-08 18:40:43 +00003782#define GEN6_RP_UP_EI 0xA068
3783#define GEN6_RP_DOWN_EI 0xA06C
3784#define GEN6_RP_IDLE_HYSTERSIS 0xA070
3785#define GEN6_RC_STATE 0xA094
3786#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3787#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3788#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3789#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3790#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3791#define GEN6_RC_SLEEP 0xA0B0
3792#define GEN6_RC1e_THRESHOLD 0xA0B4
3793#define GEN6_RC6_THRESHOLD 0xA0B8
3794#define GEN6_RC6p_THRESHOLD 0xA0BC
3795#define GEN6_RC6pp_THRESHOLD 0xA0C0
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08003796#define GEN6_PMINTRMSK 0xA168
Chris Wilson8fd26852010-12-08 18:40:43 +00003797
3798#define GEN6_PMISR 0x44020
Ben Widawsky4912d042011-04-25 11:25:20 -07003799#define GEN6_PMIMR 0x44024 /* rps_lock */
Chris Wilson8fd26852010-12-08 18:40:43 +00003800#define GEN6_PMIIR 0x44028
3801#define GEN6_PMIER 0x4402C
3802#define GEN6_PM_MBOX_EVENT (1<<25)
3803#define GEN6_PM_THERMAL_EVENT (1<<24)
3804#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3805#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3806#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3807#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3808#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
Ben Widawsky4912d042011-04-25 11:25:20 -07003809#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
3810 GEN6_PM_RP_DOWN_THRESHOLD | \
3811 GEN6_PM_RP_DOWN_TIMEOUT)
Chris Wilson8fd26852010-12-08 18:40:43 +00003812
3813#define GEN6_PCODE_MAILBOX 0x138124
3814#define GEN6_PCODE_READY (1<<31)
Jesse Barnesa6044e22010-12-20 11:34:20 -08003815#define GEN6_READ_OC_PARAMS 0xc
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07003816#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3817#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
Chris Wilson8fd26852010-12-08 18:40:43 +00003818#define GEN6_PCODE_DATA 0x138128
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07003819#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
Chris Wilson8fd26852010-12-08 18:40:43 +00003820
Ben Widawsky4d855292011-12-12 19:34:16 -08003821#define GEN6_GT_CORE_STATUS 0x138060
3822#define GEN6_CORE_CPD_STATE_MASK (7<<4)
3823#define GEN6_RCn_MASK 7
3824#define GEN6_RC0 0
3825#define GEN6_RC3 2
3826#define GEN6_RC6 3
3827#define GEN6_RC7 4
3828
Wu Fengguange0dac652011-09-05 14:25:34 +08003829#define G4X_AUD_VID_DID 0x62020
3830#define INTEL_AUDIO_DEVCL 0x808629FB
3831#define INTEL_AUDIO_DEVBLC 0x80862801
3832#define INTEL_AUDIO_DEVCTG 0x80862802
3833
3834#define G4X_AUD_CNTL_ST 0x620B4
3835#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
3836#define G4X_ELDV_DEVCTG (1 << 14)
3837#define G4X_ELD_ADDR (0xf << 5)
3838#define G4X_ELD_ACK (1 << 4)
3839#define G4X_HDMIW_HDMIEDID 0x6210C
3840
Wu Fengguang1202b4c62011-12-09 20:42:18 +08003841#define IBX_HDMIW_HDMIEDID_A 0xE2050
3842#define IBX_AUD_CNTL_ST_A 0xE20B4
3843#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
3844#define IBX_ELD_ADDRESS (0x1f << 5)
3845#define IBX_ELD_ACK (1 << 4)
3846#define IBX_AUD_CNTL_ST2 0xE20C0
3847#define IBX_ELD_VALIDB (1 << 0)
3848#define IBX_CP_READYB (1 << 1)
Wu Fengguange0dac652011-09-05 14:25:34 +08003849
Wu Fengguang1202b4c62011-12-09 20:42:18 +08003850#define CPT_HDMIW_HDMIEDID_A 0xE5050
3851#define CPT_AUD_CNTL_ST_A 0xE50B4
3852#define CPT_AUD_CNTRL_ST2 0xE50C0
Wu Fengguange0dac652011-09-05 14:25:34 +08003853
Eric Anholtae662d32012-01-03 09:23:29 -08003854/* These are the 4 32-bit write offset registers for each stream
3855 * output buffer. It determines the offset from the
3856 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
3857 */
3858#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
3859
Wu Fengguangb6daa022012-01-06 14:41:31 -06003860#define IBX_AUD_CONFIG_A 0xe2000
3861#define CPT_AUD_CONFIG_A 0xe5000
3862#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
3863#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
3864#define AUD_CONFIG_UPPER_N_SHIFT 20
3865#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
3866#define AUD_CONFIG_LOWER_N_SHIFT 4
3867#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
3868#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
3869#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
3870#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
3871
Jesse Barnes585fb112008-07-29 11:54:06 -07003872#endif /* _I915_REG_H_ */