blob: cb589cbb2b6c0322b1cdd61faf72a602db04a72e [file] [log] [blame]
Russell Kingd73e60b2008-10-31 13:08:02 +00001/*
2 * linux/arch/arm/mm/copypage-v4wb.c
3 *
4 * Copyright (C) 1995-1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/init.h>
Russell King063b0a42008-10-31 15:08:35 +000011#include <linux/highmem.h>
Russell Kingd73e60b2008-10-31 13:08:02 +000012
13/*
Russell King063b0a42008-10-31 15:08:35 +000014 * ARMv4 optimised copy_user_highpage
Russell Kingd73e60b2008-10-31 13:08:02 +000015 *
16 * We flush the destination cache lines just before we write the data into the
17 * corresponding address. Since the Dcache is read-allocate, this removes the
18 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
19 * and merged as appropriate.
20 *
21 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
22 * instruction. If your processor does not supply this, you have to write your
Russell King063b0a42008-10-31 15:08:35 +000023 * own copy_user_highpage that does the right thing.
Russell Kingd73e60b2008-10-31 13:08:02 +000024 */
Uwe Kleine-König446c92b2009-03-12 18:03:16 +010025static void __naked
Russell King063b0a42008-10-31 15:08:35 +000026v4wb_copy_user_page(void *kto, const void *kfrom)
Russell Kingd73e60b2008-10-31 13:08:02 +000027{
28 asm("\
29 stmfd sp!, {r4, lr} @ 2\n\
Khem Raj9a40ac862010-06-04 04:05:15 +010030 mov r2, %2 @ 1\n\
Russell Kingd73e60b2008-10-31 13:08:02 +000031 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
321: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
33 stmia r0!, {r3, r4, ip, lr} @ 4\n\
34 ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
35 stmia r0!, {r3, r4, ip, lr} @ 4\n\
36 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
37 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
38 stmia r0!, {r3, r4, ip, lr} @ 4\n\
39 ldmia r1!, {r3, r4, ip, lr} @ 4\n\
40 subs r2, r2, #1 @ 1\n\
41 stmia r0!, {r3, r4, ip, lr} @ 4\n\
42 ldmneia r1!, {r3, r4, ip, lr} @ 4\n\
43 bne 1b @ 1\n\
44 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\
45 ldmfd sp!, {r4, pc} @ 3"
46 :
Khem Raj9a40ac862010-06-04 04:05:15 +010047 : "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64));
Russell Kingd73e60b2008-10-31 13:08:02 +000048}
49
Russell King063b0a42008-10-31 15:08:35 +000050void v4wb_copy_user_highpage(struct page *to, struct page *from,
Russell Kingf00a75c2009-10-05 15:17:45 +010051 unsigned long vaddr, struct vm_area_struct *vma)
Russell King063b0a42008-10-31 15:08:35 +000052{
53 void *kto, *kfrom;
54
55 kto = kmap_atomic(to, KM_USER0);
56 kfrom = kmap_atomic(from, KM_USER1);
Russell King27258982009-10-05 15:34:22 +010057 flush_cache_page(vma, vaddr, page_to_pfn(from));
Russell King063b0a42008-10-31 15:08:35 +000058 v4wb_copy_user_page(kto, kfrom);
59 kunmap_atomic(kfrom, KM_USER1);
60 kunmap_atomic(kto, KM_USER0);
61}
62
Russell Kingd73e60b2008-10-31 13:08:02 +000063/*
64 * ARMv4 optimised clear_user_page
65 *
66 * Same story as above.
67 */
Russell King303c6442008-10-31 16:32:19 +000068void v4wb_clear_user_highpage(struct page *page, unsigned long vaddr)
Russell Kingd73e60b2008-10-31 13:08:02 +000069{
Nicolas Pitre43ae2862008-11-04 02:42:27 -050070 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
71 asm volatile("\
72 mov r1, %2 @ 1\n\
Russell Kingd73e60b2008-10-31 13:08:02 +000073 mov r2, #0 @ 1\n\
74 mov r3, #0 @ 1\n\
75 mov ip, #0 @ 1\n\
76 mov lr, #0 @ 1\n\
Russell King303c6442008-10-31 16:32:19 +0000771: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
78 stmia %0!, {r2, r3, ip, lr} @ 4\n\
79 stmia %0!, {r2, r3, ip, lr} @ 4\n\
80 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
81 stmia %0!, {r2, r3, ip, lr} @ 4\n\
82 stmia %0!, {r2, r3, ip, lr} @ 4\n\
Russell Kingd73e60b2008-10-31 13:08:02 +000083 subs r1, r1, #1 @ 1\n\
84 bne 1b @ 1\n\
Russell King303c6442008-10-31 16:32:19 +000085 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB"
Nicolas Pitre43ae2862008-11-04 02:42:27 -050086 : "=r" (ptr)
87 : "0" (kaddr), "I" (PAGE_SIZE / 64)
Russell King303c6442008-10-31 16:32:19 +000088 : "r1", "r2", "r3", "ip", "lr");
89 kunmap_atomic(kaddr, KM_USER0);
Russell Kingd73e60b2008-10-31 13:08:02 +000090}
91
92struct cpu_user_fns v4wb_user_fns __initdata = {
Russell King303c6442008-10-31 16:32:19 +000093 .cpu_clear_user_highpage = v4wb_clear_user_highpage,
Russell King063b0a42008-10-31 15:08:35 +000094 .cpu_copy_user_highpage = v4wb_copy_user_highpage,
Russell Kingd73e60b2008-10-31 13:08:02 +000095};