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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/proc-v6.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
Hyok S. Choid090ddd2006-06-28 14:10:01 +01005 * Modified by Catalin Marinas for noMMU support
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This is the "shell" of the ARMv6 processor support.
12 */
Tim Abbott991da172009-04-27 14:02:22 -040013#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/linkage.h>
15#include <asm/assembler.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +020016#include <asm/asm-offsets.h>
Russell King5ec94072008-09-07 19:15:31 +010017#include <asm/hwcap.h>
Russell King74945c82006-03-16 14:44:36 +000018#include <asm/pgtable-hwdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <asm/pgtable.h>
20
21#include "proc-macros.S"
22
23#define D_CACHE_LINE_SIZE 32
24
Russell King3747b362006-03-27 16:59:07 +010025#define TTB_C (1 << 0)
26#define TTB_S (1 << 1)
27#define TTB_IMP (1 << 2)
28#define TTB_RGN_NC (0 << 3)
29#define TTB_RGN_WBWA (1 << 3)
30#define TTB_RGN_WT (2 << 3)
31#define TTB_RGN_WB (3 << 3)
32
Russell Kingf2131d32007-02-08 20:46:20 +000033#ifndef CONFIG_SMP
34#define TTB_FLAGS TTB_RGN_WBWA
Russell King4b46d642009-11-01 17:44:24 +000035#define PMD_FLAGS PMD_SECT_WB
Russell Kingf2131d32007-02-08 20:46:20 +000036#else
37#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
Russell King4b46d642009-11-01 17:44:24 +000038#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
Russell Kingf2131d32007-02-08 20:46:20 +000039#endif
40
Linus Torvalds1da177e2005-04-16 15:20:36 -070041ENTRY(cpu_v6_proc_init)
42 mov pc, lr
43
44ENTRY(cpu_v6_proc_fin)
Tony Lindgren67c5587a2005-10-19 23:00:56 +010045 stmfd sp!, {lr}
46 cpsid if @ disable interrupts
47 bl v6_flush_kern_cache_all
48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 bic r0, r0, #0x1000 @ ...i............
50 bic r0, r0, #0x0006 @ .............ca.
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
52 ldmfd sp!, {pc}
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54/*
55 * cpu_v6_reset(loc)
56 *
57 * Perform a soft reset of the system. Put the CPU into the
58 * same state as it would be if it had been reset, and branch
59 * to what would be the reset vector.
60 *
61 * - loc - location to jump to for soft reset
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 */
63 .align 5
64ENTRY(cpu_v6_reset)
65 mov pc, r0
66
67/*
68 * cpu_v6_do_idle()
69 *
70 * Idle the processor (eg, wait for interrupt).
71 *
72 * IRQs are already disabled.
73 */
74ENTRY(cpu_v6_do_idle)
Catalin Marinas8553cb62008-11-10 14:14:11 +000075 mov r1, #0
76 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
Linus Torvalds1da177e2005-04-16 15:20:36 -070077 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
78 mov pc, lr
79
80ENTRY(cpu_v6_dcache_clean_area)
81#ifndef TLB_CAN_READ_FROM_L1_CACHE
821: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 add r0, r0, #D_CACHE_LINE_SIZE
84 subs r1, r1, #D_CACHE_LINE_SIZE
85 bhi 1b
86#endif
87 mov pc, lr
88
89/*
90 * cpu_arm926_switch_mm(pgd_phys, tsk)
91 *
92 * Set the translation table base pointer to be pgd_phys
93 *
94 * - pgd_phys - physical address of new TTB
95 *
96 * It is assumed that:
97 * - we are not using split page tables
98 */
99ENTRY(cpu_v6_switch_mm)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100100#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 mov r2, #0
102 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
Russell Kingf2131d32007-02-08 20:46:20 +0000103 orr r0, r0, #TTB_FLAGS
Russell Kingd93742f52005-08-15 16:53:38 +0100104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
107 mcr p15, 0, r1, c13, c0, 1 @ set context ID
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100108#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 mov pc, lr
110
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111/*
Russell Kingad1ae2f2006-12-13 14:34:43 +0000112 * cpu_v6_set_pte_ext(ptep, pte, ext)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113 *
114 * Set a level 2 translation table entry.
115 *
116 * - ptep - pointer to level 2 translation table entry
117 * (hardware version is stored at -1024 bytes)
118 * - pte - PTE value to store
Russell Kingad1ae2f2006-12-13 14:34:43 +0000119 * - ext - value for extended PTE bits
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 */
Russell King639b0ae2008-09-06 21:07:45 +0100121 armv6_mt_table cpu_v6
122
Russell Kingad1ae2f2006-12-13 14:34:43 +0000123ENTRY(cpu_v6_set_pte_ext)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100124#ifdef CONFIG_MMU
Russell King639b0ae2008-09-06 21:07:45 +0100125 armv6_set_pte_ext cpu_v6
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100126#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127 mov pc, lr
128
129
130
Saeed Bisharaedabd382009-08-06 15:12:43 +0300131 .type cpu_v6_name, #object
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132cpu_v6_name:
Russell King94b1e962006-12-08 15:32:25 +0000133 .asciz "ARMv6-compatible processor"
Saeed Bisharaedabd382009-08-06 15:12:43 +0300134 .size cpu_v6_name, . - cpu_v6_name
135
136 .type cpu_pj4_name, #object
137cpu_pj4_name:
138 .asciz "Marvell PJ4 processor"
139 .size cpu_pj4_name, . - cpu_pj4_name
140
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 .align
142
Tim Abbott991da172009-04-27 14:02:22 -0400143 __INIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144
145/*
146 * __v6_setup
147 *
148 * Initialise TLB, Caches, and MMU state ready to switch the MMU
149 * on. Return in r0 the new CP15 C1 control register setting.
150 *
151 * We automatically detect if we have a Harvard cache, and use the
152 * Harvard cache control instructions insead of the unified cache
153 * control instructions.
154 *
155 * This should be able to cover all ARMv6 cores.
156 *
157 * It is assumed that:
158 * - cache type register is implemented
159 */
160__v6_setup:
Russell King862184f2005-11-07 21:05:42 +0000161#ifdef CONFIG_SMP
Russell King862184f2005-11-07 21:05:42 +0000162 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
163 orr r0, r0, #0x20
164 mcr p15, 0, r0, c1, c0, 1
165#endif
Russell King862184f2005-11-07 21:05:42 +0000166
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 mov r0, #0
168 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
169 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
170 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
171 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100172#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
174 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
Russell Kingf2131d32007-02-08 20:46:20 +0000175 orr r4, r4, #TTB_FLAGS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100177#endif /* CONFIG_MMU */
Russell King22b190862006-06-29 15:09:57 +0100178 adr r5, v6_crval
179 ldmia r5, {r5, r6}
Catalin Marinas26584852009-05-30 14:00:18 +0100180#ifdef CONFIG_CPU_ENDIAN_BE8
181 orr r6, r6, #1 << 25 @ big-endian page tables
182#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 mrc p15, 0, r0, c1, c0, 0 @ read control register
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 bic r0, r0, r5 @ clear bits them
Russell King22b190862006-06-29 15:09:57 +0100185 orr r0, r0, r6 @ set them
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186 mov pc, lr @ return to head.S:__ret
187
188 /*
189 * V X F I D LR
190 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
191 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
192 * 0 110 0011 1.00 .111 1101 < we want
193 */
Russell King22b190862006-06-29 15:09:57 +0100194 .type v6_crval, #object
195v6_crval:
196 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197
198 .type v6_processor_functions, #object
199ENTRY(v6_processor_functions)
200 .word v6_early_abort
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100201 .word v6_pabort
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202 .word cpu_v6_proc_init
203 .word cpu_v6_proc_fin
204 .word cpu_v6_reset
205 .word cpu_v6_do_idle
206 .word cpu_v6_dcache_clean_area
207 .word cpu_v6_switch_mm
Russell Kingad1ae2f2006-12-13 14:34:43 +0000208 .word cpu_v6_set_pte_ext
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 .size v6_processor_functions, . - v6_processor_functions
210
211 .type cpu_arch_name, #object
212cpu_arch_name:
213 .asciz "armv6"
214 .size cpu_arch_name, . - cpu_arch_name
215
216 .type cpu_elf_name, #object
217cpu_elf_name:
218 .asciz "v6"
219 .size cpu_elf_name, . - cpu_elf_name
220 .align
221
Ben Dooks02b7dd12005-09-20 16:35:03 +0100222 .section ".proc.info.init", #alloc, #execinstr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223
224 /*
225 * Match any ARMv6 processor core.
226 */
227 .type __v6_proc_info, #object
228__v6_proc_info:
229 .long 0x0007b000
230 .long 0x0007f000
231 .long PMD_TYPE_SECT | \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 PMD_SECT_AP_WRITE | \
Russell King4b46d642009-11-01 17:44:24 +0000233 PMD_SECT_AP_READ | \
234 PMD_FLAGS
Russell King8799ee92006-06-29 18:24:21 +0100235 .long PMD_TYPE_SECT | \
236 PMD_SECT_XN | \
237 PMD_SECT_AP_WRITE | \
238 PMD_SECT_AP_READ
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 b __v6_setup
240 .long cpu_arch_name
241 .long cpu_elf_name
Russell Kingefe90d22006-12-08 15:22:20 +0000242 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243 .long cpu_v6_name
244 .long v6_processor_functions
245 .long v6wbi_tlb_fns
246 .long v6_user_fns
247 .long v6_cache_fns
248 .size __v6_proc_info, . - __v6_proc_info
Saeed Bisharaedabd382009-08-06 15:12:43 +0300249
250 .type __pj4_v6_proc_info, #object
251__pj4_v6_proc_info:
252 .long 0x560f5810
253 .long 0xff0ffff0
254 .long PMD_TYPE_SECT | \
Saeed Bisharaedabd382009-08-06 15:12:43 +0300255 PMD_SECT_AP_WRITE | \
Saeed Bisharaf0e5d2c2009-12-06 18:06:43 +0200256 PMD_SECT_AP_READ | \
257 PMD_FLAGS
Saeed Bisharaedabd382009-08-06 15:12:43 +0300258 .long PMD_TYPE_SECT | \
259 PMD_SECT_XN | \
260 PMD_SECT_AP_WRITE | \
261 PMD_SECT_AP_READ
262 b __v6_setup
263 .long cpu_arch_name
264 .long cpu_elf_name
265 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
266 .long cpu_pj4_name
267 .long v6_processor_functions
268 .long v6wbi_tlb_fns
269 .long v6_user_fns
270 .long v6_cache_fns
271 .size __pj4_v6_proc_info, . - __pj4_v6_proc_info