R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
Rajendra Nayak | 38b248d | 2014-04-29 16:35:10 +0530 | [diff] [blame] | 10 | #include "dra74x.dtsi" |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 11 | #include <dt-bindings/gpio/gpio.h> |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 12 | |
| 13 | / { |
Rajendra Nayak | 38b248d | 2014-04-29 16:35:10 +0530 | [diff] [blame] | 14 | model = "TI DRA742"; |
| 15 | compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 16 | |
| 17 | memory { |
| 18 | device_type = "memory"; |
| 19 | reg = <0x80000000 0x60000000>; /* 1536 MB */ |
| 20 | }; |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 21 | |
Balaji T K | 4b93521 | 2015-07-30 13:43:35 +0530 | [diff] [blame] | 22 | evm_3v3_sd: fixedregulator-sd { |
| 23 | compatible = "regulator-fixed"; |
| 24 | regulator-name = "evm_3v3_sd"; |
| 25 | regulator-min-microvolt = <3300000>; |
| 26 | regulator-max-microvolt = <3300000>; |
| 27 | enable-active-high; |
| 28 | gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; |
| 29 | }; |
| 30 | |
Peter Ujfalusi | 27f39e5 | 2015-08-24 10:19:59 +0300 | [diff] [blame] | 31 | evm_3v3_sw: fixedregulator-evm_3v3_sw { |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 32 | compatible = "regulator-fixed"; |
Peter Ujfalusi | 27f39e5 | 2015-08-24 10:19:59 +0300 | [diff] [blame] | 33 | regulator-name = "evm_3v3_sw"; |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 34 | regulator-min-microvolt = <3300000>; |
| 35 | regulator-max-microvolt = <3300000>; |
| 36 | }; |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 37 | |
Peter Ujfalusi | d681822 | 2015-08-24 10:20:00 +0300 | [diff] [blame^] | 38 | aic_dvdd: fixedregulator-aic_dvdd { |
| 39 | /* TPS77018DBVT */ |
| 40 | compatible = "regulator-fixed"; |
| 41 | regulator-name = "aic_dvdd"; |
| 42 | vin-supply = <&evm_3v3_sw>; |
| 43 | regulator-min-microvolt = <1800000>; |
| 44 | regulator-max-microvolt = <1800000>; |
| 45 | }; |
| 46 | |
Roger Quadros | 87517d2 | 2015-01-26 14:15:28 +0200 | [diff] [blame] | 47 | extcon_usb1: extcon_usb1 { |
| 48 | compatible = "linux,extcon-usb-gpio"; |
| 49 | id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; |
| 50 | }; |
| 51 | |
| 52 | extcon_usb2: extcon_usb2 { |
| 53 | compatible = "linux,extcon-usb-gpio"; |
| 54 | id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; |
| 55 | }; |
| 56 | |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 57 | vtt_fixed: fixedregulator-vtt { |
| 58 | compatible = "regulator-fixed"; |
| 59 | regulator-name = "vtt_fixed"; |
| 60 | regulator-min-microvolt = <1350000>; |
| 61 | regulator-max-microvolt = <1350000>; |
| 62 | regulator-always-on; |
| 63 | regulator-boot-on; |
| 64 | enable-active-high; |
| 65 | gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; |
| 66 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | &dra7_pmx_core { |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 70 | pinctrl-names = "default"; |
| 71 | pinctrl-0 = <&vtt_pin>; |
| 72 | |
| 73 | vtt_pin: pinmux_vtt_pin { |
| 74 | pinctrl-single,pins = < |
| 75 | 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ |
| 76 | >; |
| 77 | }; |
| 78 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 79 | i2c1_pins: pinmux_i2c1_pins { |
| 80 | pinctrl-single,pins = < |
| 81 | 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ |
| 82 | 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ |
| 83 | >; |
| 84 | }; |
| 85 | |
| 86 | i2c2_pins: pinmux_i2c2_pins { |
| 87 | pinctrl-single,pins = < |
| 88 | 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ |
| 89 | 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ |
| 90 | >; |
| 91 | }; |
| 92 | |
| 93 | i2c3_pins: pinmux_i2c3_pins { |
| 94 | pinctrl-single,pins = < |
Roger Quadros | 544d63d | 2014-09-03 14:17:31 +0300 | [diff] [blame] | 95 | 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ |
| 96 | 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 97 | >; |
| 98 | }; |
| 99 | |
| 100 | mcspi1_pins: pinmux_mcspi1_pins { |
| 101 | pinctrl-single,pins = < |
Nishanth Menon | 68e4d9e | 2014-09-04 08:33:37 -0500 | [diff] [blame] | 102 | 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */ |
| 103 | 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */ |
| 104 | 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */ |
| 105 | 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ |
Nishanth Menon | 68e4d9e | 2014-09-04 08:33:37 -0500 | [diff] [blame] | 106 | 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ |
| 107 | 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 108 | >; |
| 109 | }; |
| 110 | |
| 111 | mcspi2_pins: pinmux_mcspi2_pins { |
| 112 | pinctrl-single,pins = < |
| 113 | 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ |
| 114 | 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ |
| 115 | 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ |
| 116 | 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ |
| 117 | >; |
| 118 | }; |
| 119 | |
| 120 | uart1_pins: pinmux_uart1_pins { |
| 121 | pinctrl-single,pins = < |
| 122 | 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ |
| 123 | 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ |
| 124 | 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ |
| 125 | 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ |
| 126 | >; |
| 127 | }; |
| 128 | |
| 129 | uart2_pins: pinmux_uart2_pins { |
| 130 | pinctrl-single,pins = < |
| 131 | 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ |
| 132 | 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ |
| 133 | 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ |
| 134 | 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ |
| 135 | >; |
| 136 | }; |
| 137 | |
| 138 | uart3_pins: pinmux_uart3_pins { |
| 139 | pinctrl-single,pins = < |
| 140 | 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ |
| 141 | 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ |
| 142 | >; |
| 143 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 144 | |
| 145 | qspi1_pins: pinmux_qspi1_pins { |
| 146 | pinctrl-single,pins = < |
| 147 | 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ |
| 148 | 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ |
| 149 | 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ |
| 150 | 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ |
| 151 | 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ |
| 152 | 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ |
| 153 | 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ |
| 154 | 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ |
| 155 | 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ |
| 156 | 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ |
| 157 | >; |
| 158 | }; |
Roger Quadros | 4b4437c | 2014-05-14 10:58:13 +0300 | [diff] [blame] | 159 | |
| 160 | usb1_pins: pinmux_usb1_pins { |
| 161 | pinctrl-single,pins = < |
| 162 | 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ |
| 163 | >; |
| 164 | }; |
| 165 | |
| 166 | usb2_pins: pinmux_usb2_pins { |
| 167 | pinctrl-single,pins = < |
| 168 | 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ |
| 169 | >; |
| 170 | }; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 171 | |
| 172 | nand_flash_x16: nand_flash_x16 { |
| 173 | /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch |
| 174 | * So NAND flash requires following switch settings: |
| 175 | * SW5.9 (GPMC_WPN) = LOW |
| 176 | * SW5.1 (NAND_BOOTn) = HIGH */ |
| 177 | pinctrl-single,pins = < |
| 178 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ |
| 179 | 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ |
| 180 | 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ |
| 181 | 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ |
| 182 | 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ |
| 183 | 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ |
| 184 | 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ |
| 185 | 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ |
| 186 | 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ |
| 187 | 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ |
| 188 | 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ |
| 189 | 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ |
| 190 | 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ |
| 191 | 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ |
| 192 | 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ |
| 193 | 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ |
| 194 | 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ |
| 195 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ |
| 196 | 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ |
| 197 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ |
| 198 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ |
| 199 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ |
| 200 | >; |
| 201 | }; |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 202 | |
| 203 | cpsw_default: cpsw_default { |
| 204 | pinctrl-single,pins = < |
| 205 | /* Slave 1 */ |
| 206 | 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ |
| 207 | 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ |
| 208 | 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ |
| 209 | 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ |
| 210 | 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ |
| 211 | 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ |
| 212 | 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ |
| 213 | 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ |
| 214 | 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ |
| 215 | 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ |
| 216 | 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ |
| 217 | 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ |
| 218 | |
| 219 | /* Slave 2 */ |
| 220 | 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ |
| 221 | 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ |
| 222 | 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ |
| 223 | 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ |
| 224 | 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ |
| 225 | 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ |
| 226 | 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ |
| 227 | 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ |
| 228 | 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ |
| 229 | 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ |
| 230 | 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ |
| 231 | 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ |
| 232 | >; |
| 233 | |
| 234 | }; |
| 235 | |
| 236 | cpsw_sleep: cpsw_sleep { |
| 237 | pinctrl-single,pins = < |
| 238 | /* Slave 1 */ |
| 239 | 0x250 (MUX_MODE15) |
| 240 | 0x254 (MUX_MODE15) |
| 241 | 0x258 (MUX_MODE15) |
| 242 | 0x25c (MUX_MODE15) |
| 243 | 0x260 (MUX_MODE15) |
| 244 | 0x264 (MUX_MODE15) |
| 245 | 0x268 (MUX_MODE15) |
| 246 | 0x26c (MUX_MODE15) |
| 247 | 0x270 (MUX_MODE15) |
| 248 | 0x274 (MUX_MODE15) |
| 249 | 0x278 (MUX_MODE15) |
| 250 | 0x27c (MUX_MODE15) |
| 251 | |
| 252 | /* Slave 2 */ |
| 253 | 0x198 (MUX_MODE15) |
| 254 | 0x19c (MUX_MODE15) |
| 255 | 0x1a0 (MUX_MODE15) |
| 256 | 0x1a4 (MUX_MODE15) |
| 257 | 0x1a8 (MUX_MODE15) |
| 258 | 0x1ac (MUX_MODE15) |
| 259 | 0x1b0 (MUX_MODE15) |
| 260 | 0x1b4 (MUX_MODE15) |
| 261 | 0x1b8 (MUX_MODE15) |
| 262 | 0x1bc (MUX_MODE15) |
| 263 | 0x1c0 (MUX_MODE15) |
| 264 | 0x1c4 (MUX_MODE15) |
| 265 | >; |
| 266 | }; |
| 267 | |
| 268 | davinci_mdio_default: davinci_mdio_default { |
| 269 | pinctrl-single,pins = < |
| 270 | 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ |
| 271 | 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
| 272 | >; |
| 273 | }; |
| 274 | |
| 275 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 276 | pinctrl-single,pins = < |
| 277 | 0x23c (MUX_MODE15) |
| 278 | 0x240 (MUX_MODE15) |
| 279 | >; |
| 280 | }; |
| 281 | |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 282 | dcan1_pins_default: dcan1_pins_default { |
| 283 | pinctrl-single,pins = < |
Roger Quadros | d80d581 | 2015-03-05 15:32:43 +0200 | [diff] [blame] | 284 | 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ |
| 285 | 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 286 | >; |
| 287 | }; |
| 288 | |
| 289 | dcan1_pins_sleep: dcan1_pins_sleep { |
| 290 | pinctrl-single,pins = < |
Roger Quadros | d80d581 | 2015-03-05 15:32:43 +0200 | [diff] [blame] | 291 | 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ |
| 292 | 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 293 | >; |
| 294 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 295 | }; |
| 296 | |
| 297 | &i2c1 { |
| 298 | status = "okay"; |
| 299 | pinctrl-names = "default"; |
| 300 | pinctrl-0 = <&i2c1_pins>; |
| 301 | clock-frequency = <400000>; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 302 | |
| 303 | tps659038: tps659038@58 { |
| 304 | compatible = "ti,tps659038"; |
| 305 | reg = <0x58>; |
| 306 | |
| 307 | tps659038_pmic { |
| 308 | compatible = "ti,tps659038-pmic"; |
| 309 | |
| 310 | regulators { |
| 311 | smps123_reg: smps123 { |
| 312 | /* VDD_MPU */ |
| 313 | regulator-name = "smps123"; |
| 314 | regulator-min-microvolt = < 850000>; |
| 315 | regulator-max-microvolt = <1250000>; |
| 316 | regulator-always-on; |
| 317 | regulator-boot-on; |
| 318 | }; |
| 319 | |
| 320 | smps45_reg: smps45 { |
| 321 | /* VDD_DSPEVE */ |
| 322 | regulator-name = "smps45"; |
| 323 | regulator-min-microvolt = < 850000>; |
| 324 | regulator-max-microvolt = <1150000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 325 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 326 | regulator-boot-on; |
| 327 | }; |
| 328 | |
| 329 | smps6_reg: smps6 { |
| 330 | /* VDD_GPU - over VDD_SMPS6 */ |
| 331 | regulator-name = "smps6"; |
| 332 | regulator-min-microvolt = <850000>; |
Ravikumar Kattekola | d114e85 | 2014-12-03 17:33:56 +0530 | [diff] [blame] | 333 | regulator-max-microvolt = <1250000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 334 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 335 | regulator-boot-on; |
| 336 | }; |
| 337 | |
| 338 | smps7_reg: smps7 { |
| 339 | /* CORE_VDD */ |
| 340 | regulator-name = "smps7"; |
| 341 | regulator-min-microvolt = <850000>; |
Ravikumar Kattekola | 70fcaf9 | 2014-12-03 17:33:57 +0530 | [diff] [blame] | 342 | regulator-max-microvolt = <1060000>; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 343 | regulator-always-on; |
| 344 | regulator-boot-on; |
| 345 | }; |
| 346 | |
| 347 | smps8_reg: smps8 { |
| 348 | /* VDD_IVAHD */ |
| 349 | regulator-name = "smps8"; |
| 350 | regulator-min-microvolt = < 850000>; |
| 351 | regulator-max-microvolt = <1250000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 352 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 353 | regulator-boot-on; |
| 354 | }; |
| 355 | |
| 356 | smps9_reg: smps9 { |
| 357 | /* VDDS1V8 */ |
| 358 | regulator-name = "smps9"; |
| 359 | regulator-min-microvolt = <1800000>; |
| 360 | regulator-max-microvolt = <1800000>; |
| 361 | regulator-always-on; |
| 362 | regulator-boot-on; |
| 363 | }; |
| 364 | |
| 365 | ldo1_reg: ldo1 { |
| 366 | /* LDO1_OUT --> SDIO */ |
| 367 | regulator-name = "ldo1"; |
| 368 | regulator-min-microvolt = <1800000>; |
| 369 | regulator-max-microvolt = <3300000>; |
Kishon Vijay Abraham I | 9f04cee | 2015-07-30 13:43:39 +0530 | [diff] [blame] | 370 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 371 | regulator-boot-on; |
| 372 | }; |
| 373 | |
| 374 | ldo2_reg: ldo2 { |
| 375 | /* VDD_RTCIO */ |
| 376 | /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ |
| 377 | regulator-name = "ldo2"; |
| 378 | regulator-min-microvolt = <3300000>; |
| 379 | regulator-max-microvolt = <3300000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 380 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 381 | regulator-boot-on; |
| 382 | }; |
| 383 | |
| 384 | ldo3_reg: ldo3 { |
| 385 | /* VDDA_1V8_PHY */ |
| 386 | regulator-name = "ldo3"; |
| 387 | regulator-min-microvolt = <1800000>; |
| 388 | regulator-max-microvolt = <1800000>; |
Roger Quadros | e120fb4 | 2014-07-04 12:55:43 +0300 | [diff] [blame] | 389 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 390 | regulator-boot-on; |
| 391 | }; |
| 392 | |
| 393 | ldo9_reg: ldo9 { |
| 394 | /* VDD_RTC */ |
| 395 | regulator-name = "ldo9"; |
| 396 | regulator-min-microvolt = <1050000>; |
| 397 | regulator-max-microvolt = <1050000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 398 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 399 | regulator-boot-on; |
| 400 | }; |
| 401 | |
| 402 | ldoln_reg: ldoln { |
| 403 | /* VDDA_1V8_PLL */ |
| 404 | regulator-name = "ldoln"; |
| 405 | regulator-min-microvolt = <1800000>; |
| 406 | regulator-max-microvolt = <1800000>; |
| 407 | regulator-always-on; |
| 408 | regulator-boot-on; |
| 409 | }; |
| 410 | |
| 411 | ldousb_reg: ldousb { |
| 412 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
| 413 | regulator-name = "ldousb"; |
| 414 | regulator-min-microvolt = <3300000>; |
| 415 | regulator-max-microvolt = <3300000>; |
| 416 | regulator-boot-on; |
| 417 | }; |
| 418 | }; |
| 419 | }; |
| 420 | }; |
Roger Quadros | 87517d2 | 2015-01-26 14:15:28 +0200 | [diff] [blame] | 421 | |
| 422 | pcf_gpio_21: gpio@21 { |
| 423 | compatible = "ti,pcf8575"; |
| 424 | reg = <0x21>; |
| 425 | lines-initial-states = <0x1408>; |
| 426 | gpio-controller; |
| 427 | #gpio-cells = <2>; |
| 428 | interrupt-parent = <&gpio6>; |
| 429 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; |
| 430 | interrupt-controller; |
| 431 | #interrupt-cells = <2>; |
| 432 | }; |
| 433 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 434 | }; |
| 435 | |
| 436 | &i2c2 { |
| 437 | status = "okay"; |
| 438 | pinctrl-names = "default"; |
| 439 | pinctrl-0 = <&i2c2_pins>; |
| 440 | clock-frequency = <400000>; |
| 441 | }; |
| 442 | |
| 443 | &i2c3 { |
| 444 | status = "okay"; |
| 445 | pinctrl-names = "default"; |
| 446 | pinctrl-0 = <&i2c3_pins>; |
Roger Quadros | 544d63d | 2014-09-03 14:17:31 +0300 | [diff] [blame] | 447 | clock-frequency = <400000>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 448 | }; |
| 449 | |
| 450 | &mcspi1 { |
| 451 | status = "okay"; |
| 452 | pinctrl-names = "default"; |
| 453 | pinctrl-0 = <&mcspi1_pins>; |
| 454 | }; |
| 455 | |
| 456 | &mcspi2 { |
| 457 | status = "okay"; |
| 458 | pinctrl-names = "default"; |
| 459 | pinctrl-0 = <&mcspi2_pins>; |
| 460 | }; |
| 461 | |
| 462 | &uart1 { |
| 463 | status = "okay"; |
| 464 | pinctrl-names = "default"; |
| 465 | pinctrl-0 = <&uart1_pins>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 466 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
Nishanth Menon | 66b0436 | 2014-06-06 20:53:22 -0500 | [diff] [blame] | 467 | <&dra7_pmx_core 0x3e0>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 468 | }; |
| 469 | |
| 470 | &uart2 { |
| 471 | status = "okay"; |
| 472 | pinctrl-names = "default"; |
| 473 | pinctrl-0 = <&uart2_pins>; |
| 474 | }; |
| 475 | |
| 476 | &uart3 { |
| 477 | status = "okay"; |
| 478 | pinctrl-names = "default"; |
| 479 | pinctrl-0 = <&uart3_pins>; |
| 480 | }; |
Balaji T K | bf1788d | 2013-10-07 21:55:03 +0530 | [diff] [blame] | 481 | |
| 482 | &mmc1 { |
| 483 | status = "okay"; |
Balaji T K | 4b93521 | 2015-07-30 13:43:35 +0530 | [diff] [blame] | 484 | vmmc-supply = <&evm_3v3_sd>; |
| 485 | vmmc_aux-supply = <&ldo1_reg>; |
Balaji T K | bf1788d | 2013-10-07 21:55:03 +0530 | [diff] [blame] | 486 | bus-width = <4>; |
Nishanth Menon | f4eaf9e | 2015-07-30 13:43:37 +0530 | [diff] [blame] | 487 | /* |
| 488 | * SDCD signal is not being used here - using the fact that GPIO mode |
| 489 | * is always hardwired. |
| 490 | */ |
| 491 | cd-gpios = <&gpio6 27 0>; |
Balaji T K | bf1788d | 2013-10-07 21:55:03 +0530 | [diff] [blame] | 492 | }; |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 493 | |
| 494 | &mmc2 { |
| 495 | status = "okay"; |
Peter Ujfalusi | 27f39e5 | 2015-08-24 10:19:59 +0300 | [diff] [blame] | 496 | vmmc-supply = <&evm_3v3_sw>; |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 497 | bus-width = <8>; |
| 498 | }; |
J Keerthy | 22f1e7e | 2013-10-16 10:39:05 -0500 | [diff] [blame] | 499 | |
| 500 | &cpu0 { |
| 501 | cpu0-supply = <&smps123_reg>; |
| 502 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 503 | |
| 504 | &qspi { |
| 505 | status = "okay"; |
| 506 | pinctrl-names = "default"; |
| 507 | pinctrl-0 = <&qspi1_pins>; |
| 508 | |
| 509 | spi-max-frequency = <48000000>; |
| 510 | m25p80@0 { |
| 511 | compatible = "s25fl256s1"; |
| 512 | spi-max-frequency = <48000000>; |
| 513 | reg = <0>; |
| 514 | spi-tx-bus-width = <1>; |
| 515 | spi-rx-bus-width = <4>; |
| 516 | spi-cpol; |
| 517 | spi-cpha; |
| 518 | #address-cells = <1>; |
| 519 | #size-cells = <1>; |
| 520 | |
| 521 | /* MTD partition table. |
| 522 | * The ROM checks the first four physical blocks |
| 523 | * for a valid file to boot and the flash here is |
| 524 | * 64KiB block size. |
| 525 | */ |
| 526 | partition@0 { |
| 527 | label = "QSPI.SPL"; |
| 528 | reg = <0x00000000 0x000010000>; |
| 529 | }; |
| 530 | partition@1 { |
| 531 | label = "QSPI.SPL.backup1"; |
| 532 | reg = <0x00010000 0x00010000>; |
| 533 | }; |
| 534 | partition@2 { |
| 535 | label = "QSPI.SPL.backup2"; |
| 536 | reg = <0x00020000 0x00010000>; |
| 537 | }; |
| 538 | partition@3 { |
| 539 | label = "QSPI.SPL.backup3"; |
| 540 | reg = <0x00030000 0x00010000>; |
| 541 | }; |
| 542 | partition@4 { |
| 543 | label = "QSPI.u-boot"; |
| 544 | reg = <0x00040000 0x00100000>; |
| 545 | }; |
| 546 | partition@5 { |
| 547 | label = "QSPI.u-boot-spl-os"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 548 | reg = <0x00140000 0x00080000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 549 | }; |
| 550 | partition@6 { |
| 551 | label = "QSPI.u-boot-env"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 552 | reg = <0x001c0000 0x00010000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 553 | }; |
| 554 | partition@7 { |
| 555 | label = "QSPI.u-boot-env.backup1"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 556 | reg = <0x001d0000 0x0010000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 557 | }; |
| 558 | partition@8 { |
| 559 | label = "QSPI.kernel"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 560 | reg = <0x001e0000 0x0800000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 561 | }; |
| 562 | partition@9 { |
| 563 | label = "QSPI.file-system"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 564 | reg = <0x009e0000 0x01620000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 565 | }; |
| 566 | }; |
| 567 | }; |
Roger Quadros | 4b4437c | 2014-05-14 10:58:13 +0300 | [diff] [blame] | 568 | |
Roger Quadros | a7b0aa1 | 2015-03-17 11:43:51 +0200 | [diff] [blame] | 569 | &omap_dwc3_1 { |
| 570 | extcon = <&extcon_usb1>; |
| 571 | }; |
| 572 | |
| 573 | &omap_dwc3_2 { |
| 574 | extcon = <&extcon_usb2>; |
| 575 | }; |
| 576 | |
Roger Quadros | 4b4437c | 2014-05-14 10:58:13 +0300 | [diff] [blame] | 577 | &usb1 { |
| 578 | dr_mode = "peripheral"; |
| 579 | pinctrl-names = "default"; |
| 580 | pinctrl-0 = <&usb1_pins>; |
| 581 | }; |
| 582 | |
| 583 | &usb2 { |
| 584 | dr_mode = "host"; |
| 585 | pinctrl-names = "default"; |
| 586 | pinctrl-0 = <&usb2_pins>; |
| 587 | }; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 588 | |
| 589 | &elm { |
| 590 | status = "okay"; |
| 591 | }; |
| 592 | |
| 593 | &gpmc { |
| 594 | status = "okay"; |
| 595 | pinctrl-names = "default"; |
| 596 | pinctrl-0 = <&nand_flash_x16>; |
| 597 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ |
| 598 | nand@0,0 { |
| 599 | reg = <0 0 4>; /* device IO registers */ |
| 600 | ti,nand-ecc-opt = "bch8"; |
| 601 | ti,elm-id = <&elm>; |
| 602 | nand-bus-width = <16>; |
| 603 | gpmc,device-width = <2>; |
| 604 | gpmc,sync-clk-ps = <0>; |
| 605 | gpmc,cs-on-ns = <0>; |
Roger Quadros | 5990047 | 2014-09-10 08:57:11 -0700 | [diff] [blame] | 606 | gpmc,cs-rd-off-ns = <80>; |
| 607 | gpmc,cs-wr-off-ns = <80>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 608 | gpmc,adv-on-ns = <0>; |
Roger Quadros | 5990047 | 2014-09-10 08:57:11 -0700 | [diff] [blame] | 609 | gpmc,adv-rd-off-ns = <60>; |
| 610 | gpmc,adv-wr-off-ns = <60>; |
| 611 | gpmc,we-on-ns = <10>; |
| 612 | gpmc,we-off-ns = <50>; |
| 613 | gpmc,oe-on-ns = <4>; |
| 614 | gpmc,oe-off-ns = <40>; |
| 615 | gpmc,access-ns = <40>; |
| 616 | gpmc,wr-access-ns = <80>; |
| 617 | gpmc,rd-cycle-ns = <80>; |
| 618 | gpmc,wr-cycle-ns = <80>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 619 | gpmc,bus-turnaround-ns = <0>; |
| 620 | gpmc,cycle2cycle-delay-ns = <0>; |
| 621 | gpmc,clk-activation-ns = <0>; |
| 622 | gpmc,wait-monitoring-ns = <0>; |
| 623 | gpmc,wr-data-mux-bus-ns = <0>; |
| 624 | /* MTD partition table */ |
| 625 | /* All SPL-* partitions are sized to minimal length |
| 626 | * which can be independently programmable. For |
| 627 | * NAND flash this is equal to size of erase-block */ |
| 628 | #address-cells = <1>; |
| 629 | #size-cells = <1>; |
| 630 | partition@0 { |
| 631 | label = "NAND.SPL"; |
| 632 | reg = <0x00000000 0x000020000>; |
| 633 | }; |
| 634 | partition@1 { |
| 635 | label = "NAND.SPL.backup1"; |
| 636 | reg = <0x00020000 0x00020000>; |
| 637 | }; |
| 638 | partition@2 { |
| 639 | label = "NAND.SPL.backup2"; |
| 640 | reg = <0x00040000 0x00020000>; |
| 641 | }; |
| 642 | partition@3 { |
| 643 | label = "NAND.SPL.backup3"; |
| 644 | reg = <0x00060000 0x00020000>; |
| 645 | }; |
| 646 | partition@4 { |
| 647 | label = "NAND.u-boot-spl-os"; |
| 648 | reg = <0x00080000 0x00040000>; |
| 649 | }; |
| 650 | partition@5 { |
| 651 | label = "NAND.u-boot"; |
| 652 | reg = <0x000c0000 0x00100000>; |
| 653 | }; |
| 654 | partition@6 { |
| 655 | label = "NAND.u-boot-env"; |
| 656 | reg = <0x001c0000 0x00020000>; |
| 657 | }; |
| 658 | partition@7 { |
Roger Quadros | f0e9fab | 2014-09-03 14:17:32 +0300 | [diff] [blame] | 659 | label = "NAND.u-boot-env.backup1"; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 660 | reg = <0x001e0000 0x00020000>; |
| 661 | }; |
| 662 | partition@8 { |
| 663 | label = "NAND.kernel"; |
| 664 | reg = <0x00200000 0x00800000>; |
| 665 | }; |
| 666 | partition@9 { |
| 667 | label = "NAND.file-system"; |
| 668 | reg = <0x00a00000 0x0f600000>; |
| 669 | }; |
| 670 | }; |
| 671 | }; |
Roger Quadros | ae28ea8 | 2014-06-30 14:00:38 +0300 | [diff] [blame] | 672 | |
| 673 | &usb2_phy1 { |
| 674 | phy-supply = <&ldousb_reg>; |
| 675 | }; |
| 676 | |
| 677 | &usb2_phy2 { |
| 678 | phy-supply = <&ldousb_reg>; |
| 679 | }; |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 680 | |
| 681 | &gpio7 { |
| 682 | ti,no-reset-on-init; |
| 683 | ti,no-idle-on-init; |
| 684 | }; |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 685 | |
| 686 | &mac { |
| 687 | status = "okay"; |
| 688 | pinctrl-names = "default", "sleep"; |
| 689 | pinctrl-0 = <&cpsw_default>; |
| 690 | pinctrl-1 = <&cpsw_sleep>; |
| 691 | dual_emac; |
| 692 | }; |
| 693 | |
| 694 | &cpsw_emac0 { |
| 695 | phy_id = <&davinci_mdio>, <2>; |
| 696 | phy-mode = "rgmii"; |
| 697 | dual_emac_res_vlan = <1>; |
| 698 | }; |
| 699 | |
| 700 | &cpsw_emac1 { |
| 701 | phy_id = <&davinci_mdio>, <3>; |
| 702 | phy-mode = "rgmii"; |
| 703 | dual_emac_res_vlan = <2>; |
| 704 | }; |
| 705 | |
| 706 | &davinci_mdio { |
| 707 | pinctrl-names = "default", "sleep"; |
| 708 | pinctrl-0 = <&davinci_mdio_default>; |
| 709 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 710 | }; |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 711 | |
| 712 | &dcan1 { |
| 713 | status = "ok"; |
Roger Quadros | 2acb5c3 | 2015-07-07 17:27:57 +0300 | [diff] [blame] | 714 | pinctrl-names = "default", "sleep", "active"; |
| 715 | pinctrl-0 = <&dcan1_pins_sleep>; |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 716 | pinctrl-1 = <&dcan1_pins_sleep>; |
Roger Quadros | 2acb5c3 | 2015-07-07 17:27:57 +0300 | [diff] [blame] | 717 | pinctrl-2 = <&dcan1_pins_default>; |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 718 | }; |