| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* linux/include/asm/arch-s3c2410/regs-clock.h |
| 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * S3C2410 clock register definitions |
| 11 | * |
| 12 | * Changelog: |
| 13 | * 18-Aug-2004 Ben Dooks Added 2440 definitions |
| 14 | * 08-Aug-2004 Herbert Pötzl Added CLKCON definitions |
| 15 | * 19-06-2003 Ben Dooks Created file |
| 16 | * 12-03-2004 Ben Dooks Updated include protection |
| 17 | * 29-Sep-2004 Ben Dooks Fixed usage for assembly inclusion |
| 18 | * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) |
| 19 | * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA |
| 20 | */ |
| 21 | |
| 22 | #ifndef __ASM_ARM_REGS_CLOCK |
| 23 | #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" |
| 24 | |
| 25 | #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) |
| 26 | |
| 27 | #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s))) |
| 28 | |
| 29 | #define S3C2410_LOCKTIME S3C2410_CLKREG(0x00) |
| 30 | #define S3C2410_MPLLCON S3C2410_CLKREG(0x04) |
| 31 | #define S3C2410_UPLLCON S3C2410_CLKREG(0x08) |
| 32 | #define S3C2410_CLKCON S3C2410_CLKREG(0x0C) |
| 33 | #define S3C2410_CLKSLOW S3C2410_CLKREG(0x10) |
| 34 | #define S3C2410_CLKDIVN S3C2410_CLKREG(0x14) |
| 35 | |
| 36 | #define S3C2410_CLKCON_IDLE (1<<2) |
| 37 | #define S3C2410_CLKCON_POWER (1<<3) |
| 38 | #define S3C2410_CLKCON_NAND (1<<4) |
| 39 | #define S3C2410_CLKCON_LCDC (1<<5) |
| 40 | #define S3C2410_CLKCON_USBH (1<<6) |
| 41 | #define S3C2410_CLKCON_USBD (1<<7) |
| 42 | #define S3C2410_CLKCON_PWMT (1<<8) |
| 43 | #define S3C2410_CLKCON_SDI (1<<9) |
| 44 | #define S3C2410_CLKCON_UART0 (1<<10) |
| 45 | #define S3C2410_CLKCON_UART1 (1<<11) |
| 46 | #define S3C2410_CLKCON_UART2 (1<<12) |
| 47 | #define S3C2410_CLKCON_GPIO (1<<13) |
| 48 | #define S3C2410_CLKCON_RTC (1<<14) |
| 49 | #define S3C2410_CLKCON_ADC (1<<15) |
| 50 | #define S3C2410_CLKCON_IIC (1<<16) |
| 51 | #define S3C2410_CLKCON_IIS (1<<17) |
| 52 | #define S3C2410_CLKCON_SPI (1<<18) |
| 53 | |
| 54 | #define S3C2410_PLLCON_MDIVSHIFT 12 |
| 55 | #define S3C2410_PLLCON_PDIVSHIFT 4 |
| 56 | #define S3C2410_PLLCON_SDIVSHIFT 0 |
| 57 | #define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) |
| 58 | #define S3C2410_PLLCON_PDIVMASK ((1<<5)-1) |
| 59 | #define S3C2410_PLLCON_SDIVMASK 3 |
| 60 | |
| 61 | /* DCLKCON register addresses in gpio.h */ |
| 62 | |
| 63 | #define S3C2410_DCLKCON_DCLK0EN (1<<0) |
| 64 | #define S3C2410_DCLKCON_DCLK0_PCLK (0<<1) |
| 65 | #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) |
| 66 | #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) |
| 67 | #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) |
| 68 | |
| 69 | #define S3C2410_DCLKCON_DCLK1EN (1<<16) |
| 70 | #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) |
| 71 | #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) |
| 72 | #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) |
| 73 | |
| 74 | #define S3C2410_CLKDIVN_PDIVN (1<<0) |
| 75 | #define S3C2410_CLKDIVN_HDIVN (1<<1) |
| 76 | |
| 77 | #ifndef __ASSEMBLY__ |
| 78 | |
| 79 | static inline unsigned int |
| 80 | s3c2410_get_pll(int pllval, int baseclk) |
| 81 | { |
| 82 | int mdiv, pdiv, sdiv; |
| 83 | |
| 84 | mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; |
| 85 | pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; |
| 86 | sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT; |
| 87 | |
| 88 | mdiv &= S3C2410_PLLCON_MDIVMASK; |
| 89 | pdiv &= S3C2410_PLLCON_PDIVMASK; |
| 90 | sdiv &= S3C2410_PLLCON_SDIVMASK; |
| 91 | |
| 92 | return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv); |
| 93 | } |
| 94 | |
| 95 | #endif /* __ASSEMBLY__ */ |
| 96 | |
| 97 | #ifdef CONFIG_CPU_S3C2440 |
| 98 | |
| 99 | /* extra registers */ |
| 100 | #define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) |
| 101 | |
| 102 | #define S3C2440_CLKCON_CAMERA (1<<19) |
| 103 | #define S3C2440_CLKCON_AC97 (1<<20) |
| 104 | |
| 105 | #define S3C2440_CLKDIVN_PDIVN (1<<0) |
| 106 | #define S3C2440_CLKDIVN_HDIVN_MASK (3<<1) |
| 107 | #define S3C2440_CLKDIVN_HDIVN_1 (0<<1) |
| 108 | #define S3C2440_CLKDIVN_HDIVN_2 (1<<1) |
| 109 | #define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1) |
| 110 | #define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1) |
| 111 | #define S3C2440_CLKDIVN_UCLK (1<<3) |
| 112 | |
| 113 | #define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0) |
| 114 | #define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4) |
| 115 | #define S3C2440_CAMDIVN_HCLK3_HALF (1<<8) |
| 116 | #define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) |
| 117 | #define S3C2440_CAMDIVN_DVSEN (1<<12) |
| 118 | |
| 119 | #endif /* CONFIG_CPU_S3C2440 */ |
| 120 | |
| 121 | |
| 122 | #endif /* __ASM_ARM_REGS_CLOCK */ |