Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 1 | #include <asm/unwind.h> |
| 2 | |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 3 | #if __LINUX_ARM_ARCH__ >= 6 |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 4 | .macro bitop, name, instr |
| 5 | ENTRY( \name ) |
| 6 | UNWIND( .fnstart ) |
Russell King | a16ede3 | 2011-01-16 17:59:44 +0000 | [diff] [blame] | 7 | ands ip, r1, #3 |
| 8 | strneb r1, [ip] @ assert word-aligned |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 9 | mov r2, #1 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 10 | and r3, r0, #31 @ Get bit offset |
| 11 | mov r0, r0, lsr #5 |
| 12 | add r1, r1, r0, lsl #2 @ Get word offset |
Will Deacon | d779c07 | 2013-06-27 12:01:51 +0100 | [diff] [blame^] | 13 | #if __LINUX_ARM_ARCH__ >= 7 |
| 14 | .arch_extension mp |
| 15 | ALT_SMP(W(pldw) [r1]) |
| 16 | ALT_UP(W(nop)) |
| 17 | #endif |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 18 | mov r3, r2, lsl r3 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 19 | 1: ldrex r2, [r1] |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 20 | \instr r2, r2, r3 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 21 | strex r0, r2, [r1] |
Russell King | e7ec029 | 2005-07-28 20:36:26 +0100 | [diff] [blame] | 22 | cmp r0, #0 |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 23 | bne 1b |
Dave Martin | 3ba6e69 | 2011-02-08 12:09:52 +0100 | [diff] [blame] | 24 | bx lr |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 25 | UNWIND( .fnend ) |
| 26 | ENDPROC(\name ) |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 27 | .endm |
| 28 | |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 29 | .macro testop, name, instr, store |
| 30 | ENTRY( \name ) |
| 31 | UNWIND( .fnstart ) |
Russell King | a16ede3 | 2011-01-16 17:59:44 +0000 | [diff] [blame] | 32 | ands ip, r1, #3 |
| 33 | strneb r1, [ip] @ assert word-aligned |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 34 | mov r2, #1 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 35 | and r3, r0, #31 @ Get bit offset |
| 36 | mov r0, r0, lsr #5 |
| 37 | add r1, r1, r0, lsl #2 @ Get word offset |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 38 | mov r3, r2, lsl r3 @ create mask |
Russell King | bac4e96 | 2009-05-25 20:58:00 +0100 | [diff] [blame] | 39 | smp_dmb |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 40 | 1: ldrex r2, [r1] |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 41 | ands r0, r2, r3 @ save old value of bit |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 42 | \instr r2, r2, r3 @ toggle bit |
| 43 | strex ip, r2, [r1] |
Russell King | 614d73e | 2005-07-27 23:00:05 +0100 | [diff] [blame] | 44 | cmp ip, #0 |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 45 | bne 1b |
Russell King | bac4e96 | 2009-05-25 20:58:00 +0100 | [diff] [blame] | 46 | smp_dmb |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 47 | cmp r0, #0 |
| 48 | movne r0, #1 |
Dave Martin | 3ba6e69 | 2011-02-08 12:09:52 +0100 | [diff] [blame] | 49 | 2: bx lr |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 50 | UNWIND( .fnend ) |
| 51 | ENDPROC(\name ) |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 52 | .endm |
| 53 | #else |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 54 | .macro bitop, name, instr |
| 55 | ENTRY( \name ) |
| 56 | UNWIND( .fnstart ) |
Russell King | a16ede3 | 2011-01-16 17:59:44 +0000 | [diff] [blame] | 57 | ands ip, r1, #3 |
| 58 | strneb r1, [ip] @ assert word-aligned |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 59 | and r2, r0, #31 |
| 60 | mov r0, r0, lsr #5 |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 61 | mov r3, #1 |
| 62 | mov r3, r3, lsl r2 |
Russell King | 59d1ff3 | 2005-11-09 15:04:22 +0000 | [diff] [blame] | 63 | save_and_disable_irqs ip |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 64 | ldr r2, [r1, r0, lsl #2] |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 65 | \instr r2, r2, r3 |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 66 | str r2, [r1, r0, lsl #2] |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 67 | restore_irqs ip |
| 68 | mov pc, lr |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 69 | UNWIND( .fnend ) |
| 70 | ENDPROC(\name ) |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 71 | .endm |
| 72 | |
| 73 | /** |
| 74 | * testop - implement a test_and_xxx_bit operation. |
| 75 | * @instr: operational instruction |
| 76 | * @store: store instruction |
| 77 | * |
| 78 | * Note: we can trivially conditionalise the store instruction |
Simon Arlott | 6cbdc8c | 2007-05-11 20:40:30 +0100 | [diff] [blame] | 79 | * to avoid dirtying the data cache. |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 80 | */ |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 81 | .macro testop, name, instr, store |
| 82 | ENTRY( \name ) |
| 83 | UNWIND( .fnstart ) |
Russell King | a16ede3 | 2011-01-16 17:59:44 +0000 | [diff] [blame] | 84 | ands ip, r1, #3 |
| 85 | strneb r1, [ip] @ assert word-aligned |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 86 | and r3, r0, #31 |
| 87 | mov r0, r0, lsr #5 |
Russell King | 59d1ff3 | 2005-11-09 15:04:22 +0000 | [diff] [blame] | 88 | save_and_disable_irqs ip |
Russell King | 6323f0c | 2011-01-16 18:02:17 +0000 | [diff] [blame] | 89 | ldr r2, [r1, r0, lsl #2]! |
| 90 | mov r0, #1 |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 91 | tst r2, r0, lsl r3 |
| 92 | \instr r2, r2, r0, lsl r3 |
| 93 | \store r2, [r1] |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 94 | moveq r0, #0 |
Uwe Kleine-König | 0d928b0 | 2009-08-13 20:38:17 +0200 | [diff] [blame] | 95 | restore_irqs ip |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 96 | mov pc, lr |
Will Deacon | c36ef4b | 2011-11-23 11:28:25 +0100 | [diff] [blame] | 97 | UNWIND( .fnend ) |
| 98 | ENDPROC(\name ) |
Russell King | 7a55fd0 | 2005-04-18 22:50:01 +0100 | [diff] [blame] | 99 | .endm |
Russell King | 54ea06f | 2005-07-16 15:21:51 +0100 | [diff] [blame] | 100 | #endif |