blob: 7188c3778ee288d183334d3931d89ee5c616a8b6 [file] [log] [blame]
Dave Airlie551ebd82009-09-01 15:25:57 +10001
2#define R100_TRACK_MAX_TEXTURE 3
3#define R200_TRACK_MAX_TEXTURE 6
4#define R300_TRACK_MAX_TEXTURE 16
5
6#define R100_MAX_CB 1
7#define R300_MAX_CB 4
8
9/*
10 * CS functions
11 */
12struct r100_cs_track_cb {
Jerome Glisse4c788672009-11-20 14:29:23 +010013 struct radeon_bo *robj;
Dave Airlie551ebd82009-09-01 15:25:57 +100014 unsigned pitch;
15 unsigned cpp;
16 unsigned offset;
17};
18
19struct r100_cs_track_array {
Jerome Glisse4c788672009-11-20 14:29:23 +010020 struct radeon_bo *robj;
Dave Airlie551ebd82009-09-01 15:25:57 +100021 unsigned esize;
22};
23
24struct r100_cs_cube_info {
Jerome Glisse4c788672009-11-20 14:29:23 +010025 struct radeon_bo *robj;
26 unsigned offset;
Dave Airlie551ebd82009-09-01 15:25:57 +100027 unsigned width;
28 unsigned height;
29};
30
Dave Airlied785d782009-12-07 13:16:06 +100031#define R100_TRACK_COMP_NONE 0
32#define R100_TRACK_COMP_DXT1 1
33#define R100_TRACK_COMP_DXT35 2
34
Dave Airlie551ebd82009-09-01 15:25:57 +100035struct r100_cs_track_texture {
Jerome Glisse4c788672009-11-20 14:29:23 +010036 struct radeon_bo *robj;
Dave Airlie551ebd82009-09-01 15:25:57 +100037 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
38 unsigned pitch;
39 unsigned width;
40 unsigned height;
41 unsigned num_levels;
42 unsigned cpp;
43 unsigned tex_coord_type;
44 unsigned txdepth;
45 unsigned width_11;
46 unsigned height_11;
47 bool use_pitch;
48 bool enabled;
49 bool roundup_w;
50 bool roundup_h;
Dave Airlied785d782009-12-07 13:16:06 +100051 unsigned compress_format;
Dave Airlie551ebd82009-09-01 15:25:57 +100052};
53
54struct r100_cs_track_limits {
55 unsigned num_cb;
56 unsigned num_texture;
57 unsigned max_levels;
58};
59
60struct r100_cs_track {
61 struct radeon_device *rdev;
62 unsigned num_cb;
63 unsigned num_texture;
64 unsigned maxy;
65 unsigned vtx_size;
66 unsigned vap_vf_cntl;
67 unsigned immd_dwords;
68 unsigned num_arrays;
69 unsigned max_indx;
70 struct r100_cs_track_array arrays[11];
71 struct r100_cs_track_cb cb[R300_MAX_CB];
72 struct r100_cs_track_cb zb;
73 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
74 bool z_enabled;
75 bool separate_cube;
76
77};
78
79int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
80void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
81int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
82 struct radeon_cs_reloc **cs_reloc);
83void r100_cs_dump_packet(struct radeon_cs_parser *p,
84 struct radeon_cs_packet *pkt);
85
86int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
87
88int r200_packet0_check(struct radeon_cs_parser *p,
89 struct radeon_cs_packet *pkt,
90 unsigned idx, unsigned reg);
91
Dave Airlie513bcb42009-09-23 16:56:27 +100092
93
Dave Airlie551ebd82009-09-01 15:25:57 +100094static inline int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
95 struct radeon_cs_packet *pkt,
96 unsigned idx,
97 unsigned reg)
98{
99 int r;
100 u32 tile_flags = 0;
101 u32 tmp;
102 struct radeon_cs_reloc *reloc;
Dave Airlie513bcb42009-09-23 16:56:27 +1000103 u32 value;
Dave Airlie551ebd82009-09-01 15:25:57 +1000104
105 r = r100_cs_packet_next_reloc(p, &reloc);
106 if (r) {
107 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
108 idx, reg);
109 r100_cs_dump_packet(p, pkt);
110 return r;
111 }
Dave Airlie513bcb42009-09-23 16:56:27 +1000112 value = radeon_get_ib_value(p, idx);
113 tmp = value & 0x003fffff;
Dave Airlie551ebd82009-09-01 15:25:57 +1000114 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
115
116 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
117 tile_flags |= RADEON_DST_TILE_MACRO;
118 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
119 if (reg == RADEON_SRC_PITCH_OFFSET) {
120 DRM_ERROR("Cannot src blit from microtiled surface\n");
121 r100_cs_dump_packet(p, pkt);
122 return -EINVAL;
123 }
124 tile_flags |= RADEON_DST_TILE_MICRO;
125 }
126
127 tmp |= tile_flags;
Dave Airlie513bcb42009-09-23 16:56:27 +1000128 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
Dave Airlie551ebd82009-09-01 15:25:57 +1000129 return 0;
130}
Dave Airlie513bcb42009-09-23 16:56:27 +1000131
132static inline int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
133 struct radeon_cs_packet *pkt,
134 int idx)
135{
136 unsigned c, i;
137 struct radeon_cs_reloc *reloc;
138 struct r100_cs_track *track;
139 int r = 0;
140 volatile uint32_t *ib;
141 u32 idx_value;
142
143 ib = p->ib->ptr;
144 track = (struct r100_cs_track *)p->track;
145 c = radeon_get_ib_value(p, idx++) & 0x1F;
146 track->num_arrays = c;
147 for (i = 0; i < (c - 1); i+=2, idx+=3) {
148 r = r100_cs_packet_next_reloc(p, &reloc);
149 if (r) {
150 DRM_ERROR("No reloc for packet3 %d\n",
151 pkt->opcode);
152 r100_cs_dump_packet(p, pkt);
153 return r;
154 }
155 idx_value = radeon_get_ib_value(p, idx);
156 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
157
158 track->arrays[i + 0].esize = idx_value >> 8;
159 track->arrays[i + 0].robj = reloc->robj;
160 track->arrays[i + 0].esize &= 0x7F;
161 r = r100_cs_packet_next_reloc(p, &reloc);
162 if (r) {
163 DRM_ERROR("No reloc for packet3 %d\n",
164 pkt->opcode);
165 r100_cs_dump_packet(p, pkt);
166 return r;
167 }
168 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
169 track->arrays[i + 1].robj = reloc->robj;
170 track->arrays[i + 1].esize = idx_value >> 24;
171 track->arrays[i + 1].esize &= 0x7F;
172 }
173 if (c & 1) {
174 r = r100_cs_packet_next_reloc(p, &reloc);
175 if (r) {
176 DRM_ERROR("No reloc for packet3 %d\n",
177 pkt->opcode);
178 r100_cs_dump_packet(p, pkt);
179 return r;
180 }
181 idx_value = radeon_get_ib_value(p, idx);
182 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
183 track->arrays[i + 0].robj = reloc->robj;
184 track->arrays[i + 0].esize = idx_value >> 8;
185 track->arrays[i + 0].esize &= 0x7F;
186 }
187 return r;
188}