blob: 7d7e3fdab71fae0ce080c791dfd320d8f45218c1 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_mpiix.c - Intel MPIIX PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * The MPIIX is different enough to the PIIX4 and friends that we give it
7 * a separate driver. The old ide/pci code handles this by just not tuning
8 * MPIIX at all.
9 *
10 * The MPIIX also differs in another important way from the majority of PIIX
11 * devices. The chip is a bridge (pardon the pun) between the old world of
12 * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
13 * IDE controller is not decoded in PCI space and the chip does not claim to
14 * be IDE class PCI. This requires slightly non-standard probe logic compared
15 * with PCI IDE and also that we do not disable the device when our driver is
16 * unloaded (as it has many other functions).
17 *
18 * The driver conciously keeps this logic internally to avoid pushing quirky
19 * PATA history into the clean libata layer.
20 *
Alan Coxc9619222006-09-26 17:53:38 +010021 * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
Jeff Garzik669a5db2006-08-29 18:12:40 -040022 * hard disk present this driver will not detect it. This is not a bug. In this
23 * configuration the secondary port of the MPIIX is disabled and the addresses
24 * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
25 * to operate.
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/init.h>
32#include <linux/blkdev.h>
33#include <linux/delay.h>
34#include <scsi/scsi_host.h>
35#include <linux/libata.h>
36
37#define DRV_NAME "pata_mpiix"
Jeff Garzika0fcdc02007-03-09 07:24:15 -050038#define DRV_VERSION "0.7.6"
Jeff Garzik669a5db2006-08-29 18:12:40 -040039
40enum {
41 IDETIM = 0x6C, /* IDE control register */
42 IORDY = (1 << 1),
43 PPE = (1 << 2),
44 FTIM = (1 << 0),
45 ENABLED = (1 << 15),
46 SECONDARY = (1 << 14)
47};
48
Tejun Heocc0680a2007-08-06 18:36:23 +090049static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -040050{
Tejun Heocc0680a2007-08-06 18:36:23 +090051 struct ata_port *ap = link->ap;
Jeff Garzik669a5db2006-08-29 18:12:40 -040052 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Sergei Shtylyov92ae7842007-02-05 21:08:55 +030053 static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
Jeff Garzik669a5db2006-08-29 18:12:40 -040054
Sergei Shtylyov92ae7842007-02-05 21:08:55 +030055 if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
Alan Coxc9619222006-09-26 17:53:38 +010056 return -ENOENT;
Tejun Heod4b2bab2007-02-02 16:50:52 +090057
Tejun Heo9363c382008-04-07 22:47:16 +090058 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -040059}
60
61/**
Jeff Garzik669a5db2006-08-29 18:12:40 -040062 * mpiix_set_piomode - set initial PIO mode data
63 * @ap: ATA interface
64 * @adev: ATA device
65 *
66 * Called to do the PIO mode setup. The MPIIX allows us to program the
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +030067 * IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
68 * prefetching or IORDY are used.
Jeff Garzik669a5db2006-08-29 18:12:40 -040069 *
70 * This would get very ugly because we can only program timing for one
71 * device at a time, the other gets PIO0. Fortunately libata calls
Tejun Heo9363c382008-04-07 22:47:16 +090072 * our qc_issue command before a command is issued so we can flip the
73 * timings back and forth to reduce the pain.
Jeff Garzik669a5db2006-08-29 18:12:40 -040074 */
75
76static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
77{
78 int control = 0;
79 int pio = adev->pio_mode - XFER_PIO_0;
80 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
81 u16 idetim;
82 static const /* ISP RTC */
83 u8 timings[][2] = { { 0, 0 },
84 { 0, 0 },
85 { 1, 0 },
86 { 2, 1 },
87 { 2, 3 }, };
88
89 pci_read_config_word(pdev, IDETIM, &idetim);
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +030090
91 /* Mask the IORDY/TIME/PPE for this device */
Jeff Garzik669a5db2006-08-29 18:12:40 -040092 if (adev->class == ATA_DEV_ATA)
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +030093 control |= PPE; /* Enable prefetch/posting for disk */
Jeff Garzik669a5db2006-08-29 18:12:40 -040094 if (ata_pio_need_iordy(adev))
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +030095 control |= IORDY;
96 if (pio > 1)
Jeff Garzik669a5db2006-08-29 18:12:40 -040097 control |= FTIM; /* This drive is on the fast timing bank */
98
99 /* Mask out timing and clear both TIME bank selects */
100 idetim &= 0xCCEE;
Sergei Shtylyov7b4f1a12007-02-05 20:24:57 +0300101 idetim &= ~(0x07 << (4 * adev->devno));
102 idetim |= control << (4 * adev->devno);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400103
104 idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
105 pci_write_config_word(pdev, IDETIM, idetim);
106
107 /* We use ap->private_data as a pointer to the device currently
108 loaded for timing */
109 ap->private_data = adev;
110}
111
112/**
Tejun Heo9363c382008-04-07 22:47:16 +0900113 * mpiix_qc_issue - command issue
Jeff Garzik669a5db2006-08-29 18:12:40 -0400114 * @qc: command pending
115 *
116 * Called when the libata layer is about to issue a command. We wrap
117 * this interface so that we can load the correct ATA timings if
Robert P. J. Day3a4fa0a2007-10-19 23:10:43 +0200118 * necessary. Our logic also clears TIME0/TIME1 for the other device so
Jeff Garzik669a5db2006-08-29 18:12:40 -0400119 * that, even if we get this wrong, cycles to the other device will
120 * be made PIO0.
121 */
122
Tejun Heo9363c382008-04-07 22:47:16 +0900123static unsigned int mpiix_qc_issue(struct ata_queued_cmd *qc)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400124{
125 struct ata_port *ap = qc->ap;
126 struct ata_device *adev = qc->dev;
127
128 /* If modes have been configured and the channel data is not loaded
129 then load it. We have to check if pio_mode is set as the core code
130 does not set adev->pio_mode to XFER_PIO_0 while probing as would be
131 logical */
132
133 if (adev->pio_mode && adev != ap->private_data)
134 mpiix_set_piomode(ap, adev);
135
Tejun Heo9363c382008-04-07 22:47:16 +0900136 return ata_sff_qc_issue(qc);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400137}
138
139static struct scsi_host_template mpiix_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900140 ATA_PIO_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400141};
142
143static struct ata_port_operations mpiix_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900144 .inherits = &ata_sff_port_ops,
Tejun Heo9363c382008-04-07 22:47:16 +0900145 .qc_issue = mpiix_qc_issue,
Tejun Heo029cfd62008-03-25 12:22:49 +0900146 .cable_detect = ata_cable_40wire,
147 .set_piomode = mpiix_set_piomode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900148 .prereset = mpiix_pre_reset,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400149};
150
151static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
152{
153 /* Single threaded by the PCI probe logic */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400154 static int printed_version;
Tejun Heo5d728822007-04-17 23:44:08 +0900155 struct ata_host *host;
156 struct ata_port *ap;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900157 void __iomem *cmd_addr, *ctl_addr;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400158 u16 idetim;
Tejun Heocbcdd872007-08-18 13:14:55 +0900159 int cmd, ctl, irq;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400160
161 if (!printed_version++)
162 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
163
Tejun Heo5d728822007-04-17 23:44:08 +0900164 host = ata_host_alloc(&dev->dev, 1);
165 if (!host)
166 return -ENOMEM;
Tejun Heocbcdd872007-08-18 13:14:55 +0900167 ap = host->ports[0];
Tejun Heo5d728822007-04-17 23:44:08 +0900168
Jeff Garzik669a5db2006-08-29 18:12:40 -0400169 /* MPIIX has many functions which can be turned on or off according
170 to other devices present. Make sure IDE is enabled before we try
171 and use it */
172
173 pci_read_config_word(dev, IDETIM, &idetim);
174 if (!(idetim & ENABLED))
175 return -ENODEV;
176
Sergei Shtylyov92ae7842007-02-05 21:08:55 +0300177 /* See if it's primary or secondary channel... */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900178 if (!(idetim & SECONDARY)) {
Tejun Heocbcdd872007-08-18 13:14:55 +0900179 cmd = 0x1F0;
180 ctl = 0x3F6;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900181 irq = 14;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900182 } else {
Tejun Heocbcdd872007-08-18 13:14:55 +0900183 cmd = 0x170;
184 ctl = 0x376;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900185 irq = 15;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900186 }
187
Tejun Heocbcdd872007-08-18 13:14:55 +0900188 cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
189 ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900190 if (!cmd_addr || !ctl_addr)
191 return -ENOMEM;
192
Tejun Heocbcdd872007-08-18 13:14:55 +0900193 ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);
194
Jeff Garzik669a5db2006-08-29 18:12:40 -0400195 /* We do our own plumbing to avoid leaking special cases for whacko
196 ancient hardware into the core code. There are two issues to
197 worry about. #1 The chip is a bridge so if in legacy mode and
198 without BARs set fools the setup. #2 If you pci_disable_device
199 the MPIIX your box goes castors up */
200
Tejun Heo5d728822007-04-17 23:44:08 +0900201 ap->ops = &mpiix_port_ops;
202 ap->pio_mask = 0x1F;
203 ap->flags |= ATA_FLAG_SLAVE_POSS;
Sergei Shtylyov92ae7842007-02-05 21:08:55 +0300204
Tejun Heo5d728822007-04-17 23:44:08 +0900205 ap->ioaddr.cmd_addr = cmd_addr;
206 ap->ioaddr.ctl_addr = ctl_addr;
207 ap->ioaddr.altstatus_addr = ctl_addr;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400208
209 /* Let libata fill in the port details */
Tejun Heo9363c382008-04-07 22:47:16 +0900210 ata_sff_std_ports(&ap->ioaddr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400211
Tejun Heo5d728822007-04-17 23:44:08 +0900212 /* activate host */
Tejun Heo9363c382008-04-07 22:47:16 +0900213 return ata_host_activate(host, irq, ata_sff_interrupt, IRQF_SHARED,
Tejun Heo5d728822007-04-17 23:44:08 +0900214 &mpiix_sht);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400215}
216
Jeff Garzik669a5db2006-08-29 18:12:40 -0400217static const struct pci_device_id mpiix[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400218 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
219
220 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400221};
222
223static struct pci_driver mpiix_pci_driver = {
224 .name = DRV_NAME,
225 .id_table = mpiix,
226 .probe = mpiix_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900227 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900228#ifdef CONFIG_PM
Alan30ced0f2006-11-22 16:57:36 +0000229 .suspend = ata_pci_device_suspend,
230 .resume = ata_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900231#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400232};
233
234static int __init mpiix_init(void)
235{
236 return pci_register_driver(&mpiix_pci_driver);
237}
238
Jeff Garzik669a5db2006-08-29 18:12:40 -0400239static void __exit mpiix_exit(void)
240{
241 pci_unregister_driver(&mpiix_pci_driver);
242}
243
Jeff Garzik669a5db2006-08-29 18:12:40 -0400244MODULE_AUTHOR("Alan Cox");
245MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
246MODULE_LICENSE("GPL");
247MODULE_DEVICE_TABLE(pci, mpiix);
248MODULE_VERSION(DRV_VERSION);
249
250module_init(mpiix_init);
251module_exit(mpiix_exit);