Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 1 | /* |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 2 | * Designware SPI core controller driver (refer pxa2xx_spi.c) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2009, Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <linux/dma-mapping.h> |
| 17 | #include <linux/interrupt.h> |
Paul Gortmaker | d7614de | 2011-07-03 15:44:29 -0400 | [diff] [blame] | 18 | #include <linux/module.h> |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 19 | #include <linux/highmem.h> |
| 20 | #include <linux/delay.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 22 | #include <linux/spi/spi.h> |
Baruch Siach | d9c73bb | 2014-01-31 12:07:47 +0200 | [diff] [blame] | 23 | #include <linux/gpio.h> |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 24 | |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 25 | #include "spi-dw.h" |
Grant Likely | 568a60e | 2011-02-28 12:47:12 -0700 | [diff] [blame] | 26 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 27 | #ifdef CONFIG_DEBUG_FS |
| 28 | #include <linux/debugfs.h> |
| 29 | #endif |
| 30 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 31 | /* Slave spi_dev related */ |
| 32 | struct chip_data { |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 33 | u8 cs; /* chip select pin */ |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 34 | u8 tmode; /* TR/TO/RO/EEPROM */ |
| 35 | u8 type; /* SPI/SSP/MicroWire */ |
| 36 | |
| 37 | u8 poll_mode; /* 1 means use poll mode */ |
| 38 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 39 | u8 enable_dma; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 40 | u16 clk_div; /* baud rate divider */ |
| 41 | u32 speed_hz; /* baud rate */ |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 42 | void (*cs_control)(u32 command); |
| 43 | }; |
| 44 | |
| 45 | #ifdef CONFIG_DEBUG_FS |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 46 | #define SPI_REGS_BUFSIZE 1024 |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 47 | static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, |
| 48 | size_t count, loff_t *ppos) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 49 | { |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 50 | struct dw_spi *dws = file->private_data; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 51 | char *buf; |
| 52 | u32 len = 0; |
| 53 | ssize_t ret; |
| 54 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 55 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); |
| 56 | if (!buf) |
| 57 | return 0; |
| 58 | |
| 59 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 60 | "%s registers:\n", dev_name(&dws->master->dev)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 61 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
| 62 | "=================================\n"); |
| 63 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 64 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 65 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 66 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 67 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 68 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 69 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 70 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 71 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 72 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 73 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 74 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 75 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 76 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 77 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 78 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 79 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 80 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 81 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 82 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 83 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 84 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 85 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 86 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 87 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 88 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 89 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 90 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 91 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 92 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 93 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
| 94 | "=================================\n"); |
| 95 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 96 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 97 | kfree(buf); |
| 98 | return ret; |
| 99 | } |
| 100 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 101 | static const struct file_operations dw_spi_regs_ops = { |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 102 | .owner = THIS_MODULE, |
Stephen Boyd | 234e340 | 2012-04-05 14:25:11 -0700 | [diff] [blame] | 103 | .open = simple_open, |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 104 | .read = dw_spi_show_regs, |
Arnd Bergmann | 6038f37 | 2010-08-15 18:52:59 +0200 | [diff] [blame] | 105 | .llseek = default_llseek, |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 106 | }; |
| 107 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 108 | static int dw_spi_debugfs_init(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 109 | { |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 110 | dws->debugfs = debugfs_create_dir("dw_spi", NULL); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 111 | if (!dws->debugfs) |
| 112 | return -ENOMEM; |
| 113 | |
| 114 | debugfs_create_file("registers", S_IFREG | S_IRUGO, |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 115 | dws->debugfs, (void *)dws, &dw_spi_regs_ops); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 116 | return 0; |
| 117 | } |
| 118 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 119 | static void dw_spi_debugfs_remove(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 120 | { |
Jingoo Han | fadcace | 2014-09-02 11:49:24 +0900 | [diff] [blame] | 121 | debugfs_remove_recursive(dws->debugfs); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 122 | } |
| 123 | |
| 124 | #else |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 125 | static inline int dw_spi_debugfs_init(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 126 | { |
George Shore | 20a588f | 2010-01-21 11:40:49 +0000 | [diff] [blame] | 127 | return 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 128 | } |
| 129 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 130 | static inline void dw_spi_debugfs_remove(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 131 | { |
| 132 | } |
| 133 | #endif /* CONFIG_DEBUG_FS */ |
| 134 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 135 | static void dw_spi_set_cs(struct spi_device *spi, bool enable) |
| 136 | { |
| 137 | struct dw_spi *dws = spi_master_get_devdata(spi->master); |
| 138 | struct chip_data *chip = spi_get_ctldata(spi); |
| 139 | |
| 140 | /* Chip select logic is inverted from spi_set_cs() */ |
Andy Shevchenko | 207cda9 | 2015-03-25 20:26:26 +0200 | [diff] [blame] | 141 | if (chip && chip->cs_control) |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 142 | chip->cs_control(!enable); |
| 143 | |
| 144 | if (!enable) |
| 145 | dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); |
| 146 | } |
| 147 | |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 148 | /* Return the max entries we can fill into tx fifo */ |
| 149 | static inline u32 tx_max(struct dw_spi *dws) |
| 150 | { |
| 151 | u32 tx_left, tx_room, rxtx_gap; |
| 152 | |
| 153 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 154 | tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 155 | |
| 156 | /* |
| 157 | * Another concern is about the tx/rx mismatch, we |
| 158 | * though to use (dws->fifo_len - rxflr - txflr) as |
| 159 | * one maximum value for tx, but it doesn't cover the |
| 160 | * data which is out of tx/rx fifo and inside the |
| 161 | * shift registers. So a control from sw point of |
| 162 | * view is taken. |
| 163 | */ |
| 164 | rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) |
| 165 | / dws->n_bytes; |
| 166 | |
| 167 | return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); |
| 168 | } |
| 169 | |
| 170 | /* Return the max entries we should read out of rx fifo */ |
| 171 | static inline u32 rx_max(struct dw_spi *dws) |
| 172 | { |
| 173 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; |
| 174 | |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 175 | return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR)); |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 176 | } |
| 177 | |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 178 | static void dw_writer(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 179 | { |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 180 | u32 max = tx_max(dws); |
Feng Tang | de6efe0 | 2011-03-30 23:09:52 +0800 | [diff] [blame] | 181 | u16 txw = 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 182 | |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 183 | while (max--) { |
| 184 | /* Set the tx word if the transfer's original "tx" is not null */ |
| 185 | if (dws->tx_end - dws->len) { |
| 186 | if (dws->n_bytes == 1) |
| 187 | txw = *(u8 *)(dws->tx); |
| 188 | else |
| 189 | txw = *(u16 *)(dws->tx); |
| 190 | } |
Michael van der Westhuizen | c4fe57f | 2015-08-18 22:21:53 +0200 | [diff] [blame] | 191 | dw_write_io_reg(dws, DW_SPI_DR, txw); |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 192 | dws->tx += dws->n_bytes; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 193 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 194 | } |
| 195 | |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 196 | static void dw_reader(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 197 | { |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 198 | u32 max = rx_max(dws); |
Feng Tang | de6efe0 | 2011-03-30 23:09:52 +0800 | [diff] [blame] | 199 | u16 rxw; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 200 | |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 201 | while (max--) { |
Michael van der Westhuizen | c4fe57f | 2015-08-18 22:21:53 +0200 | [diff] [blame] | 202 | rxw = dw_read_io_reg(dws, DW_SPI_DR); |
Feng Tang | de6efe0 | 2011-03-30 23:09:52 +0800 | [diff] [blame] | 203 | /* Care rx only if the transfer's original "rx" is not null */ |
| 204 | if (dws->rx_end - dws->len) { |
| 205 | if (dws->n_bytes == 1) |
| 206 | *(u8 *)(dws->rx) = rxw; |
| 207 | else |
| 208 | *(u16 *)(dws->rx) = rxw; |
| 209 | } |
| 210 | dws->rx += dws->n_bytes; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 211 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 212 | } |
| 213 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 214 | static void int_error_stop(struct dw_spi *dws, const char *msg) |
| 215 | { |
Andy Shevchenko | 45746e8 | 2015-03-02 14:58:55 +0200 | [diff] [blame] | 216 | spi_reset_chip(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 217 | |
| 218 | dev_err(&dws->master->dev, "%s\n", msg); |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 219 | dws->master->cur_msg->status = -EIO; |
| 220 | spi_finalize_current_transfer(dws->master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 221 | } |
| 222 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 223 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) |
| 224 | { |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 225 | u16 irq_status = dw_readl(dws, DW_SPI_ISR); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 226 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 227 | /* Error handling */ |
| 228 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 229 | dw_readl(dws, DW_SPI_ICR); |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 230 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 231 | return IRQ_HANDLED; |
| 232 | } |
| 233 | |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 234 | dw_reader(dws); |
| 235 | if (dws->rx_end == dws->rx) { |
| 236 | spi_mask_intr(dws, SPI_INT_TXEI); |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 237 | spi_finalize_current_transfer(dws->master); |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 238 | return IRQ_HANDLED; |
| 239 | } |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 240 | if (irq_status & SPI_INT_TXEI) { |
| 241 | spi_mask_intr(dws, SPI_INT_TXEI); |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 242 | dw_writer(dws); |
| 243 | /* Enable TX irq always, it will be disabled when RX finished */ |
| 244 | spi_umask_intr(dws, SPI_INT_TXEI); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 245 | } |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 246 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 247 | return IRQ_HANDLED; |
| 248 | } |
| 249 | |
| 250 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) |
| 251 | { |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 252 | struct spi_master *master = dev_id; |
| 253 | struct dw_spi *dws = spi_master_get_devdata(master); |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 254 | u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; |
Yong Wang | cbcc062 | 2010-09-07 15:27:27 +0800 | [diff] [blame] | 255 | |
Yong Wang | cbcc062 | 2010-09-07 15:27:27 +0800 | [diff] [blame] | 256 | if (!irq_status) |
| 257 | return IRQ_NONE; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 258 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 259 | if (!master->cur_msg) { |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 260 | spi_mask_intr(dws, SPI_INT_TXEI); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 261 | return IRQ_HANDLED; |
| 262 | } |
| 263 | |
| 264 | return dws->transfer_handler(dws); |
| 265 | } |
| 266 | |
| 267 | /* Must be called inside pump_transfers() */ |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 268 | static int poll_transfer(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 269 | { |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 270 | do { |
| 271 | dw_writer(dws); |
Feng Tang | de6efe0 | 2011-03-30 23:09:52 +0800 | [diff] [blame] | 272 | dw_reader(dws); |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 273 | cpu_relax(); |
| 274 | } while (dws->rx_end > dws->rx); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 275 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 276 | return 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 277 | } |
| 278 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 279 | static int dw_spi_transfer_one(struct spi_master *master, |
| 280 | struct spi_device *spi, struct spi_transfer *transfer) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 281 | { |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 282 | struct dw_spi *dws = spi_master_get_devdata(master); |
| 283 | struct chip_data *chip = spi_get_ctldata(spi); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 284 | u8 imask = 0; |
Andy Shevchenko | ea11370 | 2015-02-24 13:32:11 +0200 | [diff] [blame] | 285 | u16 txlevel = 0; |
Andy Shevchenko | de6feda | 2015-10-14 23:12:21 +0300 | [diff] [blame] | 286 | u16 clk_div; |
Andy Shevchenko | 4adb1f8 | 2015-10-14 23:12:18 +0300 | [diff] [blame] | 287 | u32 cr0; |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 288 | int ret; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 289 | |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 290 | dws->dma_mapped = 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 291 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 292 | dws->tx = (void *)transfer->tx_buf; |
| 293 | dws->tx_end = dws->tx + transfer->len; |
| 294 | dws->rx = transfer->rx_buf; |
| 295 | dws->rx_end = dws->rx + transfer->len; |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 296 | dws->len = transfer->len; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 297 | |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 298 | spi_enable_chip(dws, 0); |
| 299 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 300 | /* Handle per transfer options for bpw and speed */ |
Andy Shevchenko | de6feda | 2015-10-14 23:12:21 +0300 | [diff] [blame] | 301 | if (transfer->speed_hz != chip->speed_hz) { |
Jarkko Nikula | 0ed3699 | 2015-09-15 16:26:23 +0300 | [diff] [blame] | 302 | /* clk_div doesn't support odd number */ |
Andy Shevchenko | de6feda | 2015-10-14 23:12:21 +0300 | [diff] [blame] | 303 | clk_div = (dws->max_freq / transfer->speed_hz + 1) & 0xfffe; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 304 | |
Andy Shevchenko | de6feda | 2015-10-14 23:12:21 +0300 | [diff] [blame] | 305 | chip->speed_hz = transfer->speed_hz; |
Jarkko Nikula | 0ed3699 | 2015-09-15 16:26:23 +0300 | [diff] [blame] | 306 | chip->clk_div = clk_div; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 307 | |
Jarkko Nikula | 0ed3699 | 2015-09-15 16:26:23 +0300 | [diff] [blame] | 308 | spi_set_clk(dws, chip->clk_div); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 309 | } |
Jarkko Nikula | 0ed3699 | 2015-09-15 16:26:23 +0300 | [diff] [blame] | 310 | if (transfer->bits_per_word == 8) { |
| 311 | dws->n_bytes = 1; |
| 312 | dws->dma_width = 1; |
| 313 | } else if (transfer->bits_per_word == 16) { |
| 314 | dws->n_bytes = 2; |
| 315 | dws->dma_width = 2; |
Andy Shevchenko | 863cb2f | 2015-10-14 23:12:20 +0300 | [diff] [blame] | 316 | } else { |
| 317 | return -EINVAL; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 318 | } |
Andy Shevchenko | 4adb1f8 | 2015-10-14 23:12:18 +0300 | [diff] [blame] | 319 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ |
Jarkko Nikula | 0ed3699 | 2015-09-15 16:26:23 +0300 | [diff] [blame] | 320 | cr0 = (transfer->bits_per_word - 1) |
| 321 | | (chip->type << SPI_FRF_OFFSET) |
| 322 | | (spi->mode << SPI_MODE_OFFSET) |
| 323 | | (chip->tmode << SPI_TMOD_OFFSET); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 324 | |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 325 | /* |
| 326 | * Adjust transfer mode if necessary. Requires platform dependent |
| 327 | * chipselect mechanism. |
| 328 | */ |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 329 | if (chip->cs_control) { |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 330 | if (dws->rx && dws->tx) |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 331 | chip->tmode = SPI_TMOD_TR; |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 332 | else if (dws->rx) |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 333 | chip->tmode = SPI_TMOD_RO; |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 334 | else |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 335 | chip->tmode = SPI_TMOD_TO; |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 336 | |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 337 | cr0 &= ~SPI_TMOD_MASK; |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 338 | cr0 |= (chip->tmode << SPI_TMOD_OFFSET); |
| 339 | } |
| 340 | |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 341 | dw_writel(dws, DW_SPI_CTRL0, cr0); |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 342 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 343 | /* Check if current transfer is a DMA transaction */ |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 344 | if (master->can_dma && master->can_dma(master, spi, transfer)) |
| 345 | dws->dma_mapped = master->cur_msg_mapped; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 346 | |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 347 | /* For poll mode just disable all interrupts */ |
| 348 | spi_mask_intr(dws, 0xff); |
| 349 | |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 350 | /* |
| 351 | * Interrupt mode |
| 352 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely |
| 353 | */ |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 354 | if (dws->dma_mapped) { |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 355 | ret = dws->dma_ops->dma_setup(dws, transfer); |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 356 | if (ret < 0) { |
| 357 | spi_enable_chip(dws, 1); |
| 358 | return ret; |
| 359 | } |
| 360 | } else if (!chip->poll_mode) { |
Andy Shevchenko | ea11370 | 2015-02-24 13:32:11 +0200 | [diff] [blame] | 361 | txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 362 | dw_writel(dws, DW_SPI_TXFLTR, txlevel); |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 363 | |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 364 | /* Set the interrupt mask */ |
Jingoo Han | fadcace | 2014-09-02 11:49:24 +0900 | [diff] [blame] | 365 | imask |= SPI_INT_TXEI | SPI_INT_TXOI | |
| 366 | SPI_INT_RXUI | SPI_INT_RXOI; |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 367 | spi_umask_intr(dws, imask); |
| 368 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 369 | dws->transfer_handler = interrupt_transfer; |
| 370 | } |
| 371 | |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 372 | spi_enable_chip(dws, 1); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 373 | |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 374 | if (dws->dma_mapped) { |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 375 | ret = dws->dma_ops->dma_transfer(dws, transfer); |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 376 | if (ret < 0) |
| 377 | return ret; |
| 378 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 379 | |
| 380 | if (chip->poll_mode) |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 381 | return poll_transfer(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 382 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 383 | return 1; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 384 | } |
| 385 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 386 | static void dw_spi_handle_err(struct spi_master *master, |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 387 | struct spi_message *msg) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 388 | { |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 389 | struct dw_spi *dws = spi_master_get_devdata(master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 390 | |
Andy Shevchenko | 4d5ac1e | 2015-03-09 16:48:48 +0200 | [diff] [blame] | 391 | if (dws->dma_mapped) |
| 392 | dws->dma_ops->dma_stop(dws); |
| 393 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 394 | spi_reset_chip(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | /* This may be called twice for each spi dev */ |
| 398 | static int dw_spi_setup(struct spi_device *spi) |
| 399 | { |
| 400 | struct dw_spi_chip *chip_info = NULL; |
| 401 | struct chip_data *chip; |
Baruch Siach | d9c73bb | 2014-01-31 12:07:47 +0200 | [diff] [blame] | 402 | int ret; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 403 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 404 | /* Only alloc on first setup */ |
| 405 | chip = spi_get_ctldata(spi); |
| 406 | if (!chip) { |
Axel Lin | a97c883 | 2014-08-31 12:47:06 +0800 | [diff] [blame] | 407 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 408 | if (!chip) |
| 409 | return -ENOMEM; |
Baruch Siach | 43f627a | 2013-12-30 20:30:46 +0200 | [diff] [blame] | 410 | spi_set_ctldata(spi, chip); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | /* |
| 414 | * Protocol drivers may change the chip settings, so... |
| 415 | * if chip_info exists, use it |
| 416 | */ |
| 417 | chip_info = spi->controller_data; |
| 418 | |
| 419 | /* chip_info doesn't always exist */ |
| 420 | if (chip_info) { |
| 421 | if (chip_info->cs_control) |
| 422 | chip->cs_control = chip_info->cs_control; |
| 423 | |
| 424 | chip->poll_mode = chip_info->poll_mode; |
| 425 | chip->type = chip_info->type; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 426 | } |
| 427 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 428 | chip->tmode = 0; /* Tx & Rx */ |
Andy Shevchenko | c3ce15b | 2014-09-18 20:08:56 +0300 | [diff] [blame] | 429 | |
Baruch Siach | d9c73bb | 2014-01-31 12:07:47 +0200 | [diff] [blame] | 430 | if (gpio_is_valid(spi->cs_gpio)) { |
| 431 | ret = gpio_direction_output(spi->cs_gpio, |
| 432 | !(spi->mode & SPI_CS_HIGH)); |
| 433 | if (ret) |
| 434 | return ret; |
| 435 | } |
| 436 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 437 | return 0; |
| 438 | } |
| 439 | |
Axel Lin | a97c883 | 2014-08-31 12:47:06 +0800 | [diff] [blame] | 440 | static void dw_spi_cleanup(struct spi_device *spi) |
| 441 | { |
| 442 | struct chip_data *chip = spi_get_ctldata(spi); |
| 443 | |
| 444 | kfree(chip); |
| 445 | spi_set_ctldata(spi, NULL); |
| 446 | } |
| 447 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 448 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
Andy Shevchenko | 30b4b70 | 2015-01-07 16:56:55 +0200 | [diff] [blame] | 449 | static void spi_hw_init(struct device *dev, struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 450 | { |
Andy Shevchenko | 45746e8 | 2015-03-02 14:58:55 +0200 | [diff] [blame] | 451 | spi_reset_chip(dws); |
Feng Tang | c587b6f | 2010-01-21 10:41:10 +0800 | [diff] [blame] | 452 | |
| 453 | /* |
| 454 | * Try to detect the FIFO depth if not set by interface driver, |
| 455 | * the depth could be from 2 to 256 from HW spec |
| 456 | */ |
| 457 | if (!dws->fifo_len) { |
| 458 | u32 fifo; |
Jingoo Han | fadcace | 2014-09-02 11:49:24 +0900 | [diff] [blame] | 459 | |
Andy Shevchenko | 9d239d3 | 2015-02-25 11:39:36 +0200 | [diff] [blame] | 460 | for (fifo = 1; fifo < 256; fifo++) { |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 461 | dw_writel(dws, DW_SPI_TXFLTR, fifo); |
| 462 | if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) |
Feng Tang | c587b6f | 2010-01-21 10:41:10 +0800 | [diff] [blame] | 463 | break; |
| 464 | } |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 465 | dw_writel(dws, DW_SPI_TXFLTR, 0); |
Feng Tang | c587b6f | 2010-01-21 10:41:10 +0800 | [diff] [blame] | 466 | |
Andy Shevchenko | 9d239d3 | 2015-02-25 11:39:36 +0200 | [diff] [blame] | 467 | dws->fifo_len = (fifo == 1) ? 0 : fifo; |
Andy Shevchenko | 30b4b70 | 2015-01-07 16:56:55 +0200 | [diff] [blame] | 468 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); |
Feng Tang | c587b6f | 2010-01-21 10:41:10 +0800 | [diff] [blame] | 469 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 470 | } |
| 471 | |
Baruch Siach | 04f421e | 2013-12-30 20:30:44 +0200 | [diff] [blame] | 472 | int dw_spi_add_host(struct device *dev, struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 473 | { |
| 474 | struct spi_master *master; |
| 475 | int ret; |
| 476 | |
| 477 | BUG_ON(dws == NULL); |
| 478 | |
Baruch Siach | 04f421e | 2013-12-30 20:30:44 +0200 | [diff] [blame] | 479 | master = spi_alloc_master(dev, 0); |
| 480 | if (!master) |
| 481 | return -ENOMEM; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 482 | |
| 483 | dws->master = master; |
| 484 | dws->type = SSI_MOTO_SPI; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 485 | dws->dma_inited = 0; |
Andy Shevchenko | d7ef54c | 2015-10-27 17:48:16 +0200 | [diff] [blame^] | 486 | dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); |
Andy Shevchenko | c3c6e23 | 2014-09-18 20:08:57 +0300 | [diff] [blame] | 487 | snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 488 | |
Andy Shevchenko | 02f2038 | 2015-10-20 12:11:40 +0300 | [diff] [blame] | 489 | ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dws->name, master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 490 | if (ret < 0) { |
Andy Shevchenko | 5f0966e | 2015-10-14 23:12:17 +0300 | [diff] [blame] | 491 | dev_err(dev, "can not get IRQ\n"); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 492 | goto err_free_master; |
| 493 | } |
| 494 | |
Andy Shevchenko | c3ce15b | 2014-09-18 20:08:56 +0300 | [diff] [blame] | 495 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 496 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 497 | master->bus_num = dws->bus_num; |
| 498 | master->num_chipselect = dws->num_cs; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 499 | master->setup = dw_spi_setup; |
Axel Lin | a97c883 | 2014-08-31 12:47:06 +0800 | [diff] [blame] | 500 | master->cleanup = dw_spi_cleanup; |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 501 | master->set_cs = dw_spi_set_cs; |
| 502 | master->transfer_one = dw_spi_transfer_one; |
| 503 | master->handle_err = dw_spi_handle_err; |
Axel Lin | 765ee70 | 2014-02-20 21:37:56 +0800 | [diff] [blame] | 504 | master->max_speed_hz = dws->max_freq; |
Thor Thayer | 9c6de47 | 2014-10-08 13:51:34 -0500 | [diff] [blame] | 505 | master->dev.of_node = dev->of_node; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 506 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 507 | /* Basic HW init */ |
Andy Shevchenko | 30b4b70 | 2015-01-07 16:56:55 +0200 | [diff] [blame] | 508 | spi_hw_init(dev, dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 509 | |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 510 | if (dws->dma_ops && dws->dma_ops->dma_init) { |
| 511 | ret = dws->dma_ops->dma_init(dws); |
| 512 | if (ret) { |
Andy Shevchenko | 3dbb3b9 | 2015-01-07 16:56:54 +0200 | [diff] [blame] | 513 | dev_warn(dev, "DMA init failed\n"); |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 514 | dws->dma_inited = 0; |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 515 | } else { |
| 516 | master->can_dma = dws->dma_ops->can_dma; |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 517 | } |
| 518 | } |
| 519 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 520 | spi_master_set_devdata(master, dws); |
Baruch Siach | 04f421e | 2013-12-30 20:30:44 +0200 | [diff] [blame] | 521 | ret = devm_spi_register_master(dev, master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 522 | if (ret) { |
| 523 | dev_err(&master->dev, "problem registering spi master\n"); |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 524 | goto err_dma_exit; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 525 | } |
| 526 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 527 | dw_spi_debugfs_init(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 528 | return 0; |
| 529 | |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 530 | err_dma_exit: |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 531 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
| 532 | dws->dma_ops->dma_exit(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 533 | spi_enable_chip(dws, 0); |
Andy Shevchenko | 02f2038 | 2015-10-20 12:11:40 +0300 | [diff] [blame] | 534 | free_irq(dws->irq, master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 535 | err_free_master: |
| 536 | spi_master_put(master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 537 | return ret; |
| 538 | } |
Feng Tang | 79290a2 | 2010-12-24 13:59:10 +0800 | [diff] [blame] | 539 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 540 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 541 | void dw_spi_remove_host(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 542 | { |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 543 | dw_spi_debugfs_remove(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 544 | |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 545 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
| 546 | dws->dma_ops->dma_exit(dws); |
Andy Shevchenko | 1cc3f14 | 2015-10-14 23:12:23 +0300 | [diff] [blame] | 547 | |
| 548 | spi_shutdown_chip(dws); |
Andy Shevchenko | 02f2038 | 2015-10-20 12:11:40 +0300 | [diff] [blame] | 549 | |
| 550 | free_irq(dws->irq, dws->master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 551 | } |
Feng Tang | 79290a2 | 2010-12-24 13:59:10 +0800 | [diff] [blame] | 552 | EXPORT_SYMBOL_GPL(dw_spi_remove_host); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 553 | |
| 554 | int dw_spi_suspend_host(struct dw_spi *dws) |
| 555 | { |
Andy Shevchenko | 1cc3f14 | 2015-10-14 23:12:23 +0300 | [diff] [blame] | 556 | int ret; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 557 | |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 558 | ret = spi_master_suspend(dws->master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 559 | if (ret) |
| 560 | return ret; |
Andy Shevchenko | 1cc3f14 | 2015-10-14 23:12:23 +0300 | [diff] [blame] | 561 | |
| 562 | spi_shutdown_chip(dws); |
| 563 | return 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 564 | } |
Feng Tang | 79290a2 | 2010-12-24 13:59:10 +0800 | [diff] [blame] | 565 | EXPORT_SYMBOL_GPL(dw_spi_suspend_host); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 566 | |
| 567 | int dw_spi_resume_host(struct dw_spi *dws) |
| 568 | { |
| 569 | int ret; |
| 570 | |
Andy Shevchenko | 30b4b70 | 2015-01-07 16:56:55 +0200 | [diff] [blame] | 571 | spi_hw_init(&dws->master->dev, dws); |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 572 | ret = spi_master_resume(dws->master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 573 | if (ret) |
| 574 | dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); |
| 575 | return ret; |
| 576 | } |
Feng Tang | 79290a2 | 2010-12-24 13:59:10 +0800 | [diff] [blame] | 577 | EXPORT_SYMBOL_GPL(dw_spi_resume_host); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 578 | |
| 579 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); |
| 580 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); |
| 581 | MODULE_LICENSE("GPL v2"); |