Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* Generic MTRR (Memory Type Range Register) driver. |
| 2 | |
| 3 | Copyright (C) 1997-2000 Richard Gooch |
| 4 | Copyright (c) 2002 Patrick Mochel |
| 5 | |
| 6 | This library is free software; you can redistribute it and/or |
| 7 | modify it under the terms of the GNU Library General Public |
| 8 | License as published by the Free Software Foundation; either |
| 9 | version 2 of the License, or (at your option) any later version. |
| 10 | |
| 11 | This library is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | Library General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU Library General Public |
| 17 | License along with this library; if not, write to the Free |
| 18 | Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | |
| 20 | Richard Gooch may be reached by email at rgooch@atnf.csiro.au |
| 21 | The postal address is: |
| 22 | Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia. |
| 23 | |
| 24 | Source: "Pentium Pro Family Developer's Manual, Volume 3: |
| 25 | Operating System Writer's Guide" (Intel document number 242692), |
| 26 | section 11.11.7 |
| 27 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 28 | This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> |
| 29 | on 6-7 March 2002. |
| 30 | Source: Intel Architecture Software Developers Manual, Volume 3: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | System Programming Guide; Section 9.11. (1997 edition - PPro). |
| 32 | */ |
| 33 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 34 | #define DEBUG |
| 35 | |
| 36 | #include <linux/types.h> /* FIXME: kvm_para.h needs this */ |
| 37 | |
Suresh Siddha | 68f202e | 2010-07-30 11:46:42 -0700 | [diff] [blame] | 38 | #include <linux/stop_machine.h> |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 39 | #include <linux/kvm_para.h> |
| 40 | #include <linux/uaccess.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | #include <linux/module.h> |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 42 | #include <linux/mutex.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | #include <linux/init.h> |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 44 | #include <linux/sort.h> |
| 45 | #include <linux/cpu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #include <linux/pci.h> |
| 47 | #include <linux/smp.h> |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 48 | #include <linux/syscore_ops.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 50 | #include <asm/processor.h> |
Jesse Barnes | 99fc8d4 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 51 | #include <asm/e820.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | #include <asm/mtrr.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | #include <asm/msr.h> |
Andy Lutomirski | d0d98ee | 2013-05-13 23:58:40 +0000 | [diff] [blame] | 54 | #include <asm/pat.h> |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 55 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | #include "mtrr.h" |
| 57 | |
Andy Lutomirski | d0d98ee | 2013-05-13 23:58:40 +0000 | [diff] [blame] | 58 | /* arch_phys_wc_add returns an MTRR register index plus this offset. */ |
| 59 | #define MTRR_TO_PHYS_WC_OFFSET 1000 |
| 60 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 61 | u32 num_var_ranges; |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 62 | static bool __mtrr_enabled; |
| 63 | |
| 64 | static bool mtrr_enabled(void) |
| 65 | { |
| 66 | return __mtrr_enabled; |
| 67 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | |
Sheng Yang | b558bc0 | 2008-10-09 16:01:52 +0800 | [diff] [blame] | 69 | unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; |
Ingo Molnar | 14cc3e2 | 2006-03-26 01:37:14 -0800 | [diff] [blame] | 70 | static DEFINE_MUTEX(mtrr_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | |
Andreas Herrmann | 6c5806c | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 72 | u64 size_or_mask, size_and_mask; |
H. Peter Anvin | 5400743 | 2009-08-21 17:00:02 -0700 | [diff] [blame] | 73 | static bool mtrr_aps_delayed_init; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | |
Emese Revfy | 3b9cfc0 | 2010-01-31 20:16:34 +0100 | [diff] [blame] | 75 | static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | |
Emese Revfy | 3b9cfc0 | 2010-01-31 20:16:34 +0100 | [diff] [blame] | 77 | const struct mtrr_ops *mtrr_if; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | |
| 79 | static void set_mtrr(unsigned int reg, unsigned long base, |
| 80 | unsigned long size, mtrr_type type); |
| 81 | |
Emese Revfy | 3b9cfc0 | 2010-01-31 20:16:34 +0100 | [diff] [blame] | 82 | void set_mtrr_ops(const struct mtrr_ops *ops) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | { |
| 84 | if (ops->vendor && ops->vendor < X86_VENDOR_NUM) |
| 85 | mtrr_ops[ops->vendor] = ops; |
| 86 | } |
| 87 | |
| 88 | /* Returns non-zero if we have the write-combining memory type */ |
| 89 | static int have_wrcomb(void) |
| 90 | { |
| 91 | struct pci_dev *dev; |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 92 | |
| 93 | dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL); |
| 94 | if (dev != NULL) { |
| 95 | /* |
| 96 | * ServerWorks LE chipsets < rev 6 have problems with |
| 97 | * write-combining. Don't allow it and leave room for other |
| 98 | * chipsets to be tagged |
| 99 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS && |
Sergei Shtylyov | 50c31e4 | 2011-07-01 22:42:08 +0400 | [diff] [blame] | 101 | dev->device == PCI_DEVICE_ID_SERVERWORKS_LE && |
| 102 | dev->revision <= 5) { |
| 103 | pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n"); |
| 104 | pci_dev_put(dev); |
| 105 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | } |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 107 | /* |
| 108 | * Intel 450NX errata # 23. Non ascending cacheline evictions to |
| 109 | * write combining memory may resulting in data corruption |
| 110 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | if (dev->vendor == PCI_VENDOR_ID_INTEL && |
| 112 | dev->device == PCI_DEVICE_ID_INTEL_82451NX) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 113 | pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | pci_dev_put(dev); |
| 115 | return 0; |
| 116 | } |
| 117 | pci_dev_put(dev); |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 118 | } |
| 119 | return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | /* This function returns the number of variable MTRRs */ |
| 123 | static void __init set_num_var_ranges(void) |
| 124 | { |
| 125 | unsigned long config = 0, dummy; |
| 126 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 127 | if (use_intel()) |
Jaswinder Singh Rajput | d9bcc01 | 2009-05-14 12:06:12 +0530 | [diff] [blame] | 128 | rdmsr(MSR_MTRRcap, config, dummy); |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 129 | else if (is_cpu(AMD)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | config = 2; |
| 131 | else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) |
| 132 | config = 8; |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 133 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | num_var_ranges = config & 0xff; |
| 135 | } |
| 136 | |
| 137 | static void __init init_table(void) |
| 138 | { |
| 139 | int i, max; |
| 140 | |
| 141 | max = num_var_ranges; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | for (i = 0; i < max; i++) |
Jesse Barnes | 99fc8d4 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 143 | mtrr_usage_table[i] = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | struct set_mtrr_data { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | unsigned long smp_base; |
| 148 | unsigned long smp_size; |
| 149 | unsigned int smp_reg; |
| 150 | mtrr_type smp_type; |
| 151 | }; |
| 152 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 153 | /** |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 154 | * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed |
| 155 | * by all the CPUs. |
Randy Dunlap | 6c550ee | 2010-03-05 09:52:52 -0800 | [diff] [blame] | 156 | * @info: pointer to mtrr configuration data |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 157 | * |
| 158 | * Returns nothing. |
| 159 | */ |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 160 | static int mtrr_rendezvous_handler(void *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | { |
| 162 | struct set_mtrr_data *data = info; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 164 | /* |
| 165 | * We use this same function to initialize the mtrrs during boot, |
| 166 | * resume, runtime cpu online and on an explicit request to set a |
| 167 | * specific MTRR. |
| 168 | * |
| 169 | * During boot or suspend, the state of the boot cpu's mtrrs has been |
| 170 | * saved, and we want to replicate that across all the cpus that come |
| 171 | * online (either at the end of boot or resume or during a runtime cpu |
| 172 | * online). If we're doing that, @reg is set to something special and on |
| 173 | * all the cpu's we do mtrr_if->set_all() (On the logical cpu that |
| 174 | * started the boot/resume sequence, this might be a duplicate |
| 175 | * set_all()). |
| 176 | */ |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 177 | if (data->smp_reg != ~0U) { |
| 178 | mtrr_if->set(data->smp_reg, data->smp_base, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | data->smp_size, data->smp_type); |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 180 | } else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | mtrr_if->set_all(); |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 182 | } |
Suresh Siddha | 68f202e | 2010-07-30 11:46:42 -0700 | [diff] [blame] | 183 | return 0; |
Ingo Molnar | 4e2947f | 2007-11-09 22:39:38 +0100 | [diff] [blame] | 184 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 186 | static inline int types_compatible(mtrr_type type1, mtrr_type type2) |
| 187 | { |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 188 | return type1 == MTRR_TYPE_UNCACHABLE || |
| 189 | type2 == MTRR_TYPE_UNCACHABLE || |
| 190 | (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) || |
| 191 | (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH); |
| 192 | } |
| 193 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | /** |
| 195 | * set_mtrr - update mtrrs on all processors |
| 196 | * @reg: mtrr in question |
| 197 | * @base: mtrr base |
| 198 | * @size: mtrr size |
| 199 | * @type: mtrr type |
| 200 | * |
| 201 | * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly: |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 202 | * |
Suresh Siddha | 68f202e | 2010-07-30 11:46:42 -0700 | [diff] [blame] | 203 | * 1. Queue work to do the following on all processors: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | * 2. Disable Interrupts |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 205 | * 3. Wait for all procs to do so |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | * 4. Enter no-fill cache mode |
| 207 | * 5. Flush caches |
| 208 | * 6. Clear PGE bit |
| 209 | * 7. Flush all TLBs |
| 210 | * 8. Disable all range registers |
| 211 | * 9. Update the MTRRs |
| 212 | * 10. Enable all range registers |
| 213 | * 11. Flush all TLBs and caches again |
| 214 | * 12. Enter normal cache mode and reenable caching |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 215 | * 13. Set PGE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | * 14. Wait for buddies to catch up |
| 217 | * 15. Enable interrupts. |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 218 | * |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 219 | * What does that mean for us? Well, stop_machine() will ensure that |
| 220 | * the rendezvous handler is started on each CPU. And in lockstep they |
| 221 | * do the state transition of disabling interrupts, updating MTRR's |
| 222 | * (the CPU vendors may each do it differently, so we call mtrr_if->set() |
| 223 | * callback and let them take care of it.) and enabling interrupts. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | * |
| 225 | * Note that the mechanism is the same for UP systems, too; all the SMP stuff |
| 226 | * becomes nops. |
| 227 | */ |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 228 | static void |
| 229 | set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 230 | { |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 231 | struct set_mtrr_data data = { .smp_reg = reg, |
| 232 | .smp_base = base, |
| 233 | .smp_size = size, |
| 234 | .smp_type = type |
| 235 | }; |
Suresh Siddha | 68f202e | 2010-07-30 11:46:42 -0700 | [diff] [blame] | 236 | |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 237 | stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask); |
| 238 | } |
Suresh Siddha | 6d3321e | 2011-06-23 11:19:26 -0700 | [diff] [blame] | 239 | |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 240 | static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base, |
| 241 | unsigned long size, mtrr_type type) |
| 242 | { |
| 243 | struct set_mtrr_data data = { .smp_reg = reg, |
| 244 | .smp_base = base, |
| 245 | .smp_size = size, |
| 246 | .smp_type = type |
| 247 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 249 | stop_machine_from_inactive_cpu(mtrr_rendezvous_handler, &data, |
| 250 | cpu_callout_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 251 | } |
| 252 | |
| 253 | /** |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 254 | * mtrr_add_page - Add a memory type region |
| 255 | * @base: Physical base address of region in pages (in units of 4 kB!) |
| 256 | * @size: Physical size of region in pages (4 kB) |
| 257 | * @type: Type of MTRR desired |
| 258 | * @increment: If this is true do usage counting on the region |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 259 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 260 | * Memory type region registers control the caching on newer Intel and |
| 261 | * non Intel processors. This function allows drivers to request an |
| 262 | * MTRR is added. The details and hardware specifics of each processor's |
| 263 | * implementation are hidden from the caller, but nevertheless the |
| 264 | * caller should expect to need to provide a power of two size on an |
| 265 | * equivalent power of two boundary. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 267 | * If the region cannot be added either because all regions are in use |
| 268 | * or the CPU cannot support it a negative value is returned. On success |
| 269 | * the register number for this entry is returned, but should be treated |
| 270 | * as a cookie only. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 272 | * On a multiprocessor machine the changes are made to all processors. |
| 273 | * This is required on x86 by the Intel processors. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 275 | * The available types are |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 277 | * %MTRR_TYPE_UNCACHABLE - No caching |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 279 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 280 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 281 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 283 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 284 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 285 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
| 286 | * failures and do not wish system log messages to be sent. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | */ |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 288 | int mtrr_add_page(unsigned long base, unsigned long size, |
Paul Jimenez | 2d2ee8d | 2008-01-30 13:30:31 +0100 | [diff] [blame] | 289 | unsigned int type, bool increment) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 291 | unsigned long lbase, lsize; |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 292 | int i, replace, error; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | mtrr_type ltype; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 295 | if (!mtrr_enabled()) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | return -ENXIO; |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 297 | |
| 298 | error = mtrr_if->validate_add_page(base, size, type); |
| 299 | if (error) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 300 | return error; |
| 301 | |
| 302 | if (type >= MTRR_NUM_TYPES) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 303 | pr_warning("mtrr: type: %u invalid\n", type); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 304 | return -EINVAL; |
| 305 | } |
| 306 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 307 | /* If the type is WC, check that this processor supports it */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 308 | if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 309 | pr_warning("mtrr: your processor doesn't support write-combining\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 310 | return -ENOSYS; |
| 311 | } |
| 312 | |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 313 | if (!size) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 314 | pr_warning("mtrr: zero sized request\n"); |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 315 | return -EINVAL; |
| 316 | } |
| 317 | |
Yinghai Lu | d5c7867 | 2013-06-13 15:33:35 -0700 | [diff] [blame] | 318 | if ((base | (base + size - 1)) >> |
| 319 | (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 320 | pr_warning("mtrr: base or size exceeds the MTRR width\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | return -EINVAL; |
| 322 | } |
| 323 | |
| 324 | error = -EINVAL; |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 325 | replace = -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 326 | |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 327 | /* No CPU hotplug when we change MTRR entries */ |
Gautham R Shenoy | 86ef5c9 | 2008-01-25 21:08:02 +0100 | [diff] [blame] | 328 | get_online_cpus(); |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 329 | |
| 330 | /* Search for existing MTRR */ |
Ingo Molnar | 14cc3e2 | 2006-03-26 01:37:14 -0800 | [diff] [blame] | 331 | mutex_lock(&mtrr_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | for (i = 0; i < num_var_ranges; ++i) { |
| 333 | mtrr_if->get(i, &lbase, &lsize, <ype); |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 334 | if (!lsize || base > lbase + lsize - 1 || |
| 335 | base + size - 1 < lbase) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 336 | continue; |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 337 | /* |
| 338 | * At this point we know there is some kind of |
| 339 | * overlap/enclosure |
| 340 | */ |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 341 | if (base < lbase || base + size - 1 > lbase + lsize - 1) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 342 | if (base <= lbase && |
| 343 | base + size - 1 >= lbase + lsize - 1) { |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 344 | /* New region encloses an existing region */ |
| 345 | if (type == ltype) { |
| 346 | replace = replace == -1 ? i : -2; |
| 347 | continue; |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 348 | } else if (types_compatible(type, ltype)) |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 349 | continue; |
| 350 | } |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 351 | pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing" |
| 352 | " 0x%lx000,0x%lx000\n", base, size, lbase, |
| 353 | lsize); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 354 | goto out; |
| 355 | } |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 356 | /* New region is enclosed by an existing region */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | if (ltype != type) { |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 358 | if (types_compatible(type, ltype)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 359 | continue; |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 360 | pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n", |
| 361 | base, size, mtrr_attrib_to_str(ltype), |
| 362 | mtrr_attrib_to_str(type)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 363 | goto out; |
| 364 | } |
| 365 | if (increment) |
Jesse Barnes | 99fc8d4 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 366 | ++mtrr_usage_table[i]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | error = i; |
| 368 | goto out; |
| 369 | } |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 370 | /* Search for an empty MTRR */ |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 371 | i = mtrr_if->get_free_region(base, size, replace); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 372 | if (i >= 0) { |
| 373 | set_mtrr(i, base, size, type); |
Jesse Barnes | 99fc8d4 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 374 | if (likely(replace < 0)) { |
| 375 | mtrr_usage_table[i] = 1; |
| 376 | } else { |
| 377 | mtrr_usage_table[i] = mtrr_usage_table[replace]; |
Paul Jimenez | 2d2ee8d | 2008-01-30 13:30:31 +0100 | [diff] [blame] | 378 | if (increment) |
Jesse Barnes | 99fc8d4 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 379 | mtrr_usage_table[i]++; |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 380 | if (unlikely(replace != i)) { |
| 381 | set_mtrr(replace, 0, 0, 0); |
Jesse Barnes | 99fc8d4 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 382 | mtrr_usage_table[replace] = 0; |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 383 | } |
| 384 | } |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 385 | } else { |
| 386 | pr_info("mtrr: no more MTRRs available\n"); |
| 387 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | error = i; |
| 389 | out: |
Ingo Molnar | 14cc3e2 | 2006-03-26 01:37:14 -0800 | [diff] [blame] | 390 | mutex_unlock(&mtrr_mutex); |
Gautham R Shenoy | 86ef5c9 | 2008-01-25 21:08:02 +0100 | [diff] [blame] | 391 | put_online_cpus(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | return error; |
| 393 | } |
| 394 | |
Andrew Morton | c92c6ff | 2005-06-23 00:08:35 -0700 | [diff] [blame] | 395 | static int mtrr_check(unsigned long base, unsigned long size) |
| 396 | { |
| 397 | if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 398 | pr_warning("mtrr: size and base must be multiples of 4 kiB\n"); |
| 399 | pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base); |
Andrew Morton | c92c6ff | 2005-06-23 00:08:35 -0700 | [diff] [blame] | 400 | dump_stack(); |
| 401 | return -1; |
| 402 | } |
| 403 | return 0; |
| 404 | } |
| 405 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | /** |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 407 | * mtrr_add - Add a memory type region |
| 408 | * @base: Physical base address of region |
| 409 | * @size: Physical size of region |
| 410 | * @type: Type of MTRR desired |
| 411 | * @increment: If this is true do usage counting on the region |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 413 | * Memory type region registers control the caching on newer Intel and |
| 414 | * non Intel processors. This function allows drivers to request an |
| 415 | * MTRR is added. The details and hardware specifics of each processor's |
| 416 | * implementation are hidden from the caller, but nevertheless the |
| 417 | * caller should expect to need to provide a power of two size on an |
| 418 | * equivalent power of two boundary. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 420 | * If the region cannot be added either because all regions are in use |
| 421 | * or the CPU cannot support it a negative value is returned. On success |
| 422 | * the register number for this entry is returned, but should be treated |
| 423 | * as a cookie only. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 424 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 425 | * On a multiprocessor machine the changes are made to all processors. |
| 426 | * This is required on x86 by the Intel processors. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 427 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 428 | * The available types are |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 430 | * %MTRR_TYPE_UNCACHABLE - No caching |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 432 | * %MTRR_TYPE_WRBACK - Write data back in bursts whenever |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 434 | * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 436 | * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 437 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 438 | * BUGS: Needs a quiet flag for the cases where drivers do not mind |
| 439 | * failures and do not wish system log messages to be sent. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | */ |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 441 | int mtrr_add(unsigned long base, unsigned long size, unsigned int type, |
| 442 | bool increment) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 443 | { |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 444 | if (!mtrr_enabled()) |
| 445 | return -ENODEV; |
Andrew Morton | c92c6ff | 2005-06-23 00:08:35 -0700 | [diff] [blame] | 446 | if (mtrr_check(base, size)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type, |
| 449 | increment); |
| 450 | } |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 451 | EXPORT_SYMBOL(mtrr_add); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 452 | |
| 453 | /** |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 454 | * mtrr_del_page - delete a memory type region |
| 455 | * @reg: Register returned by mtrr_add |
| 456 | * @base: Physical base address |
| 457 | * @size: Size of region |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 458 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 459 | * If register is supplied then base and size are ignored. This is |
| 460 | * how drivers should call it. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 462 | * Releases an MTRR region. If the usage count drops to zero the |
| 463 | * register is freed and the region returns to default state. |
| 464 | * On success the register is returned, on failure a negative error |
| 465 | * code. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | int mtrr_del_page(int reg, unsigned long base, unsigned long size) |
| 468 | { |
| 469 | int i, max; |
| 470 | mtrr_type ltype; |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 471 | unsigned long lbase, lsize; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 472 | int error = -EINVAL; |
| 473 | |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 474 | if (!mtrr_enabled()) |
| 475 | return -ENODEV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 476 | |
| 477 | max = num_var_ranges; |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 478 | /* No CPU hotplug when we change MTRR entries */ |
Gautham R Shenoy | 86ef5c9 | 2008-01-25 21:08:02 +0100 | [diff] [blame] | 479 | get_online_cpus(); |
Ingo Molnar | 14cc3e2 | 2006-03-26 01:37:14 -0800 | [diff] [blame] | 480 | mutex_lock(&mtrr_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | if (reg < 0) { |
| 482 | /* Search for existing MTRR */ |
| 483 | for (i = 0; i < max; ++i) { |
| 484 | mtrr_if->get(i, &lbase, &lsize, <ype); |
| 485 | if (lbase == base && lsize == size) { |
| 486 | reg = i; |
| 487 | break; |
| 488 | } |
| 489 | } |
| 490 | if (reg < 0) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 491 | pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n", |
| 492 | base, size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | goto out; |
| 494 | } |
| 495 | } |
| 496 | if (reg >= max) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 497 | pr_warning("mtrr: register: %d too big\n", reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 498 | goto out; |
| 499 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 500 | mtrr_if->get(reg, &lbase, &lsize, <ype); |
| 501 | if (lsize < 1) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 502 | pr_warning("mtrr: MTRR %d not used\n", reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | goto out; |
| 504 | } |
Jesse Barnes | 99fc8d4 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 505 | if (mtrr_usage_table[reg] < 1) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 506 | pr_warning("mtrr: reg: %d has count=0\n", reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 507 | goto out; |
| 508 | } |
Jesse Barnes | 99fc8d4 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 509 | if (--mtrr_usage_table[reg] < 1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 510 | set_mtrr(reg, 0, 0, 0); |
| 511 | error = reg; |
| 512 | out: |
Ingo Molnar | 14cc3e2 | 2006-03-26 01:37:14 -0800 | [diff] [blame] | 513 | mutex_unlock(&mtrr_mutex); |
Gautham R Shenoy | 86ef5c9 | 2008-01-25 21:08:02 +0100 | [diff] [blame] | 514 | put_online_cpus(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | return error; |
| 516 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 517 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 518 | /** |
| 519 | * mtrr_del - delete a memory type region |
| 520 | * @reg: Register returned by mtrr_add |
| 521 | * @base: Physical base address |
| 522 | * @size: Size of region |
| 523 | * |
| 524 | * If register is supplied then base and size are ignored. This is |
| 525 | * how drivers should call it. |
| 526 | * |
| 527 | * Releases an MTRR region. If the usage count drops to zero the |
| 528 | * register is freed and the region returns to default state. |
| 529 | * On success the register is returned, on failure a negative error |
| 530 | * code. |
| 531 | */ |
| 532 | int mtrr_del(int reg, unsigned long base, unsigned long size) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 533 | { |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 534 | if (!mtrr_enabled()) |
| 535 | return -ENODEV; |
Andrew Morton | c92c6ff | 2005-06-23 00:08:35 -0700 | [diff] [blame] | 536 | if (mtrr_check(base, size)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 537 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT); |
| 539 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | EXPORT_SYMBOL(mtrr_del); |
| 541 | |
Andy Lutomirski | d0d98ee | 2013-05-13 23:58:40 +0000 | [diff] [blame] | 542 | /** |
| 543 | * arch_phys_wc_add - add a WC MTRR and handle errors if PAT is unavailable |
| 544 | * @base: Physical base address |
| 545 | * @size: Size of region |
| 546 | * |
| 547 | * If PAT is available, this does nothing. If PAT is unavailable, it |
| 548 | * attempts to add a WC MTRR covering size bytes starting at base and |
| 549 | * logs an error if this fails. |
| 550 | * |
Luis R. Rodriguez | 2f9e897 | 2015-05-26 10:28:12 +0200 | [diff] [blame] | 551 | * The called should provide a power of two size on an equivalent |
| 552 | * power of two boundary. |
| 553 | * |
Andy Lutomirski | d0d98ee | 2013-05-13 23:58:40 +0000 | [diff] [blame] | 554 | * Drivers must store the return value to pass to mtrr_del_wc_if_needed, |
| 555 | * but drivers should not try to interpret that return value. |
| 556 | */ |
| 557 | int arch_phys_wc_add(unsigned long base, unsigned long size) |
| 558 | { |
| 559 | int ret; |
| 560 | |
Luis R. Rodriguez | cb32edf | 2015-05-26 10:28:15 +0200 | [diff] [blame] | 561 | if (pat_enabled() || !mtrr_enabled()) |
Andy Lutomirski | d0d98ee | 2013-05-13 23:58:40 +0000 | [diff] [blame] | 562 | return 0; /* Success! (We don't need to do anything.) */ |
| 563 | |
| 564 | ret = mtrr_add(base, size, MTRR_TYPE_WRCOMB, true); |
| 565 | if (ret < 0) { |
| 566 | pr_warn("Failed to add WC MTRR for [%p-%p]; performance may suffer.", |
| 567 | (void *)base, (void *)(base + size - 1)); |
| 568 | return ret; |
| 569 | } |
| 570 | return ret + MTRR_TO_PHYS_WC_OFFSET; |
| 571 | } |
| 572 | EXPORT_SYMBOL(arch_phys_wc_add); |
| 573 | |
| 574 | /* |
| 575 | * arch_phys_wc_del - undoes arch_phys_wc_add |
| 576 | * @handle: Return value from arch_phys_wc_add |
| 577 | * |
| 578 | * This cleans up after mtrr_add_wc_if_needed. |
| 579 | * |
| 580 | * The API guarantees that mtrr_del_wc_if_needed(error code) and |
| 581 | * mtrr_del_wc_if_needed(0) do nothing. |
| 582 | */ |
| 583 | void arch_phys_wc_del(int handle) |
| 584 | { |
| 585 | if (handle >= 1) { |
| 586 | WARN_ON(handle < MTRR_TO_PHYS_WC_OFFSET); |
| 587 | mtrr_del(handle - MTRR_TO_PHYS_WC_OFFSET, 0, 0); |
| 588 | } |
| 589 | } |
| 590 | EXPORT_SYMBOL(arch_phys_wc_del); |
| 591 | |
| 592 | /* |
Luis R. Rodriguez | 7d010fd | 2015-05-26 10:28:13 +0200 | [diff] [blame] | 593 | * arch_phys_wc_index - translates arch_phys_wc_add's return value |
Andy Lutomirski | d0d98ee | 2013-05-13 23:58:40 +0000 | [diff] [blame] | 594 | * @handle: Return value from arch_phys_wc_add |
| 595 | * |
| 596 | * This will turn the return value from arch_phys_wc_add into an mtrr |
| 597 | * index suitable for debugging. |
| 598 | * |
| 599 | * Note: There is no legitimate use for this function, except possibly |
| 600 | * in printk line. Alas there is an illegitimate use in some ancient |
| 601 | * drm ioctls. |
| 602 | */ |
Luis R. Rodriguez | 7d010fd | 2015-05-26 10:28:13 +0200 | [diff] [blame] | 603 | int arch_phys_wc_index(int handle) |
Andy Lutomirski | d0d98ee | 2013-05-13 23:58:40 +0000 | [diff] [blame] | 604 | { |
| 605 | if (handle < MTRR_TO_PHYS_WC_OFFSET) |
| 606 | return -1; |
| 607 | else |
| 608 | return handle - MTRR_TO_PHYS_WC_OFFSET; |
| 609 | } |
Luis R. Rodriguez | 7d010fd | 2015-05-26 10:28:13 +0200 | [diff] [blame] | 610 | EXPORT_SYMBOL_GPL(arch_phys_wc_index); |
Andy Lutomirski | d0d98ee | 2013-05-13 23:58:40 +0000 | [diff] [blame] | 611 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 612 | /* |
| 613 | * HACK ALERT! |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 614 | * These should be called implicitly, but we can't yet until all the initcall |
| 615 | * stuff is done... |
| 616 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | static void __init init_ifs(void) |
| 618 | { |
Jan Beulich | 475850c | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 619 | #ifndef CONFIG_X86_64 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | amd_init_mtrr(); |
| 621 | cyrix_init_mtrr(); |
| 622 | centaur_init_mtrr(); |
Jan Beulich | 475850c | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 623 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 624 | } |
| 625 | |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 626 | /* The suspend/resume methods are only for CPU without MTRR. CPU using generic |
| 627 | * MTRR driver doesn't require this |
| 628 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 629 | struct mtrr_value { |
| 630 | mtrr_type ltype; |
| 631 | unsigned long lbase; |
Jan Beulich | 365bff8 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 632 | unsigned long lsize; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | }; |
| 634 | |
Yinghai Lu | f0348c4 | 2009-03-16 16:33:59 -0700 | [diff] [blame] | 635 | static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 636 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 637 | static int mtrr_save(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 638 | { |
| 639 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | |
| 641 | for (i = 0; i < num_var_ranges; i++) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 642 | mtrr_if->get(i, &mtrr_value[i].lbase, |
| 643 | &mtrr_value[i].lsize, |
| 644 | &mtrr_value[i].ltype); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 645 | } |
| 646 | return 0; |
| 647 | } |
| 648 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 649 | static void mtrr_restore(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | { |
| 651 | int i; |
| 652 | |
| 653 | for (i = 0; i < num_var_ranges; i++) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 654 | if (mtrr_value[i].lsize) { |
| 655 | set_mtrr(i, mtrr_value[i].lbase, |
| 656 | mtrr_value[i].lsize, |
| 657 | mtrr_value[i].ltype); |
| 658 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 659 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | } |
| 661 | |
| 662 | |
| 663 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 664 | static struct syscore_ops mtrr_syscore_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 665 | .suspend = mtrr_save, |
| 666 | .resume = mtrr_restore, |
| 667 | }; |
| 668 | |
Yinghai Lu | 0d89035 | 2009-03-11 20:07:39 -0700 | [diff] [blame] | 669 | int __initdata changed_by_mtrr_cleanup; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 670 | |
Yinghai Lu | d5c7867 | 2013-06-13 15:33:35 -0700 | [diff] [blame] | 671 | #define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 672 | /** |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 673 | * mtrr_bp_init - initialize mtrrs on the boot CPU |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 674 | * |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 675 | * This needs to be called early; before any of the other CPUs are |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 676 | * initialized (i.e. before smp_init()). |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 677 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 678 | */ |
Sam Ravnborg | 9ef231a | 2007-07-21 17:10:39 +0200 | [diff] [blame] | 679 | void __init mtrr_bp_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | { |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 681 | u32 phys_addr; |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 682 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 683 | init_ifs(); |
| 684 | |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 685 | phys_addr = 32; |
| 686 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 687 | if (cpu_has_mtrr) { |
| 688 | mtrr_if = &generic_mtrr_ops; |
Yinghai Lu | d5c7867 | 2013-06-13 15:33:35 -0700 | [diff] [blame] | 689 | size_or_mask = SIZE_OR_MASK_BITS(36); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 690 | size_and_mask = 0x00f00000; |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 691 | phys_addr = 36; |
Andi Kleen | 1f2c958 | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 692 | |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 693 | /* |
| 694 | * This is an AMD specific MSR, but we assume(hope?) that |
Olaf Hering | 4319eb4 | 2012-12-06 21:16:11 +0100 | [diff] [blame] | 695 | * Intel will implement it too when they extend the address |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 696 | * bus of the Xeon. |
| 697 | */ |
Andi Kleen | 1f2c958 | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 698 | if (cpuid_eax(0x80000000) >= 0x80000008) { |
Andi Kleen | 1f2c958 | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 699 | phys_addr = cpuid_eax(0x80000008) & 0xff; |
Shaohua Li | af9c142 | 2005-11-05 17:25:54 +0100 | [diff] [blame] | 700 | /* CPUID workaround for Intel 0F33/0F34 CPU */ |
| 701 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && |
| 702 | boot_cpu_data.x86 == 0xF && |
| 703 | boot_cpu_data.x86_model == 0x3 && |
| 704 | (boot_cpu_data.x86_mask == 0x3 || |
| 705 | boot_cpu_data.x86_mask == 0x4)) |
| 706 | phys_addr = 36; |
| 707 | |
Yinghai Lu | d5c7867 | 2013-06-13 15:33:35 -0700 | [diff] [blame] | 708 | size_or_mask = SIZE_OR_MASK_BITS(phys_addr); |
Andreas Herrmann | 6c5806c | 2007-02-13 13:26:23 +0100 | [diff] [blame] | 709 | size_and_mask = ~size_or_mask & 0xfffff00000ULL; |
Andi Kleen | 1f2c958 | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 710 | } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && |
| 711 | boot_cpu_data.x86 == 6) { |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 712 | /* |
| 713 | * VIA C* family have Intel style MTRRs, |
| 714 | * but don't support PAE |
| 715 | */ |
Yinghai Lu | d5c7867 | 2013-06-13 15:33:35 -0700 | [diff] [blame] | 716 | size_or_mask = SIZE_OR_MASK_BITS(32); |
Andi Kleen | 1f2c958 | 2005-04-16 15:25:10 -0700 | [diff] [blame] | 717 | size_and_mask = 0; |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 718 | phys_addr = 32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 719 | } |
| 720 | } else { |
| 721 | switch (boot_cpu_data.x86_vendor) { |
| 722 | case X86_VENDOR_AMD: |
Dave Hansen | 9298b81 | 2014-09-11 14:15:24 -0700 | [diff] [blame] | 723 | if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 724 | /* Pre-Athlon (K6) AMD CPU MTRRs */ |
| 725 | mtrr_if = mtrr_ops[X86_VENDOR_AMD]; |
Yinghai Lu | d5c7867 | 2013-06-13 15:33:35 -0700 | [diff] [blame] | 726 | size_or_mask = SIZE_OR_MASK_BITS(32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | size_and_mask = 0; |
| 728 | } |
| 729 | break; |
| 730 | case X86_VENDOR_CENTAUR: |
Dave Hansen | 9298b81 | 2014-09-11 14:15:24 -0700 | [diff] [blame] | 731 | if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR]; |
Yinghai Lu | d5c7867 | 2013-06-13 15:33:35 -0700 | [diff] [blame] | 733 | size_or_mask = SIZE_OR_MASK_BITS(32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 734 | size_and_mask = 0; |
| 735 | } |
| 736 | break; |
| 737 | case X86_VENDOR_CYRIX: |
Dave Hansen | 9298b81 | 2014-09-11 14:15:24 -0700 | [diff] [blame] | 738 | if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 739 | mtrr_if = mtrr_ops[X86_VENDOR_CYRIX]; |
Yinghai Lu | d5c7867 | 2013-06-13 15:33:35 -0700 | [diff] [blame] | 740 | size_or_mask = SIZE_OR_MASK_BITS(32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 741 | size_and_mask = 0; |
| 742 | } |
| 743 | break; |
| 744 | default: |
| 745 | break; |
| 746 | } |
| 747 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 748 | |
| 749 | if (mtrr_if) { |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 750 | __mtrr_enabled = true; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 751 | set_num_var_ranges(); |
| 752 | init_table(); |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 753 | if (use_intel()) { |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 754 | /* BIOS may override */ |
| 755 | __mtrr_enabled = get_mtrr_state(); |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 756 | |
Yinghai Lu | 12031a6 | 2008-05-02 02:40:22 -0700 | [diff] [blame] | 757 | if (mtrr_cleanup(phys_addr)) { |
| 758 | changed_by_mtrr_cleanup = 1; |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 759 | mtrr_if->set_all(); |
Yinghai Lu | 12031a6 | 2008-05-02 02:40:22 -0700 | [diff] [blame] | 760 | } |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 761 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 762 | } |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 763 | |
| 764 | if (!mtrr_enabled()) |
| 765 | pr_info("MTRR: Disabled\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 766 | } |
| 767 | |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 768 | void mtrr_ap_init(void) |
| 769 | { |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 770 | if (!mtrr_enabled()) |
| 771 | return; |
| 772 | |
Suresh Siddha | d0af9ee | 2009-08-19 18:05:36 -0700 | [diff] [blame] | 773 | if (!use_intel() || mtrr_aps_delayed_init) |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 774 | return; |
| 775 | /* |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 776 | * Ideally we should hold mtrr_mutex here to avoid mtrr entries |
| 777 | * changed, but this routine will be called in cpu boot time, |
| 778 | * holding the lock breaks it. |
| 779 | * |
| 780 | * This routine is called in two cases: |
| 781 | * |
| 782 | * 1. very earily time of software resume, when there absolutely |
| 783 | * isn't mtrr entry changes; |
| 784 | * |
| 785 | * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug |
| 786 | * lock to prevent mtrr entry changes |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 787 | */ |
Suresh Siddha | 192d885 | 2011-06-23 11:19:29 -0700 | [diff] [blame] | 788 | set_mtrr_from_inactive_cpu(~0U, 0, 0, 0); |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 789 | } |
| 790 | |
Bernhard Kaindl | 2b1f627 | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 791 | /** |
Fenghua Yu | 30242aa | 2012-11-13 11:32:48 -0800 | [diff] [blame] | 792 | * Save current fixed-range MTRR state of the first cpu in cpu_online_mask. |
Bernhard Kaindl | 2b1f627 | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 793 | */ |
| 794 | void mtrr_save_state(void) |
| 795 | { |
Fenghua Yu | 30242aa | 2012-11-13 11:32:48 -0800 | [diff] [blame] | 796 | int first_cpu; |
| 797 | |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 798 | if (!mtrr_enabled()) |
| 799 | return; |
| 800 | |
Fenghua Yu | 30242aa | 2012-11-13 11:32:48 -0800 | [diff] [blame] | 801 | get_online_cpus(); |
| 802 | first_cpu = cpumask_first(cpu_online_mask); |
| 803 | smp_call_function_single(first_cpu, mtrr_save_fixed_ranges, NULL, 1); |
| 804 | put_online_cpus(); |
Bernhard Kaindl | 2b1f627 | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 805 | } |
| 806 | |
Suresh Siddha | d0af9ee | 2009-08-19 18:05:36 -0700 | [diff] [blame] | 807 | void set_mtrr_aps_delayed_init(void) |
| 808 | { |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 809 | if (!mtrr_enabled()) |
| 810 | return; |
Suresh Siddha | d0af9ee | 2009-08-19 18:05:36 -0700 | [diff] [blame] | 811 | if (!use_intel()) |
| 812 | return; |
| 813 | |
H. Peter Anvin | 5400743 | 2009-08-21 17:00:02 -0700 | [diff] [blame] | 814 | mtrr_aps_delayed_init = true; |
Suresh Siddha | d0af9ee | 2009-08-19 18:05:36 -0700 | [diff] [blame] | 815 | } |
| 816 | |
| 817 | /* |
Suresh Siddha | f744854 | 2011-02-02 17:02:55 -0800 | [diff] [blame] | 818 | * Delayed MTRR initialization for all AP's |
Suresh Siddha | d0af9ee | 2009-08-19 18:05:36 -0700 | [diff] [blame] | 819 | */ |
| 820 | void mtrr_aps_init(void) |
| 821 | { |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 822 | if (!use_intel() || !mtrr_enabled()) |
Suresh Siddha | d0af9ee | 2009-08-19 18:05:36 -0700 | [diff] [blame] | 823 | return; |
| 824 | |
Suresh Siddha | f744854 | 2011-02-02 17:02:55 -0800 | [diff] [blame] | 825 | /* |
| 826 | * Check if someone has requested the delay of AP MTRR initialization, |
| 827 | * by doing set_mtrr_aps_delayed_init(), prior to this point. If not, |
| 828 | * then we are done. |
| 829 | */ |
| 830 | if (!mtrr_aps_delayed_init) |
| 831 | return; |
| 832 | |
Suresh Siddha | d0af9ee | 2009-08-19 18:05:36 -0700 | [diff] [blame] | 833 | set_mtrr(~0U, 0, 0, 0); |
H. Peter Anvin | 5400743 | 2009-08-21 17:00:02 -0700 | [diff] [blame] | 834 | mtrr_aps_delayed_init = false; |
Suresh Siddha | d0af9ee | 2009-08-19 18:05:36 -0700 | [diff] [blame] | 835 | } |
| 836 | |
| 837 | void mtrr_bp_restore(void) |
| 838 | { |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 839 | if (!use_intel() || !mtrr_enabled()) |
Suresh Siddha | d0af9ee | 2009-08-19 18:05:36 -0700 | [diff] [blame] | 840 | return; |
| 841 | |
| 842 | mtrr_if->set_all(); |
| 843 | } |
| 844 | |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 845 | static int __init mtrr_init_finialize(void) |
| 846 | { |
Luis R. Rodriguez | f962610 | 2015-05-26 10:28:14 +0200 | [diff] [blame] | 847 | if (!mtrr_enabled()) |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 848 | return 0; |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 849 | |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 850 | if (use_intel()) { |
Yinghai Lu | 12031a6 | 2008-05-02 02:40:22 -0700 | [diff] [blame] | 851 | if (!changed_by_mtrr_cleanup) |
Yinghai Lu | 95ffa24 | 2008-04-29 03:52:33 -0700 | [diff] [blame] | 852 | mtrr_state_warn(); |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 853 | return 0; |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 854 | } |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 855 | |
| 856 | /* |
| 857 | * The CPU has no MTRR and seems to not support SMP. They have |
| 858 | * specific drivers, we use a tricky method to support |
| 859 | * suspend/resume for them. |
| 860 | * |
| 861 | * TBD: is there any system with such CPU which supports |
| 862 | * suspend/resume? If no, we should remove the code. |
| 863 | */ |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 864 | register_syscore_ops(&mtrr_syscore_ops); |
Jaswinder Singh Rajput | dbd51be | 2009-07-04 07:56:28 +0530 | [diff] [blame] | 865 | |
Shaohua Li | 3b520b2 | 2005-07-07 17:56:38 -0700 | [diff] [blame] | 866 | return 0; |
| 867 | } |
| 868 | subsys_initcall(mtrr_init_finialize); |