blob: 038e59a8bf0a67abc0bc8d5be3ec73464e00e075 [file] [log] [blame]
Andrei Konovalovae918c02007-07-17 04:04:11 -07001/*
Andrei Konovalovae918c02007-07-17 04:04:11 -07002 * Xilinx SPI controller driver (master mode only)
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
Grant Likely8fd88212010-10-14 09:04:29 -06007 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
8 * Copyright (c) 2009 Intel Corporation
9 * 2002-2007 (c) MontaVista Software, Inc.
10
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
Andrei Konovalovae918c02007-07-17 04:04:11 -070014 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
Grant Likelyeae6cb32010-10-14 09:32:53 -060019#include <linux/of.h>
Grant Likely8fd88212010-10-14 09:04:29 -060020#include <linux/platform_device.h>
Andrei Konovalovae918c02007-07-17 04:04:11 -070021#include <linux/spi/spi.h>
22#include <linux/spi/spi_bitbang.h>
Richard Röjforsd5af91a2009-11-13 12:28:39 +010023#include <linux/spi/xilinx_spi.h>
Grant Likelyeae6cb32010-10-14 09:32:53 -060024#include <linux/io.h>
Richard Röjforsd5af91a2009-11-13 12:28:39 +010025
David Brownellfc3ba952007-08-30 23:56:24 -070026#define XILINX_SPI_NAME "xilinx_spi"
Andrei Konovalovae918c02007-07-17 04:04:11 -070027
28/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
29 * Product Specification", DS464
30 */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010031#define XSPI_CR_OFFSET 0x60 /* Control Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070032
Michal Simek082339b2013-06-04 16:02:36 +020033#define XSPI_CR_LOOP 0x01
Andrei Konovalovae918c02007-07-17 04:04:11 -070034#define XSPI_CR_ENABLE 0x02
35#define XSPI_CR_MASTER_MODE 0x04
36#define XSPI_CR_CPOL 0x08
37#define XSPI_CR_CPHA 0x10
38#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
39#define XSPI_CR_TXFIFO_RESET 0x20
40#define XSPI_CR_RXFIFO_RESET 0x40
41#define XSPI_CR_MANUAL_SSELECT 0x80
42#define XSPI_CR_TRANS_INHIBIT 0x100
Richard Röjforsc9da2e12009-11-13 12:28:55 +010043#define XSPI_CR_LSB_FIRST 0x200
Andrei Konovalovae918c02007-07-17 04:04:11 -070044
Richard Röjforsc9da2e12009-11-13 12:28:55 +010045#define XSPI_SR_OFFSET 0x64 /* Status Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070046
47#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
48#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
49#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
50#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
51#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
52
Richard Röjforsc9da2e12009-11-13 12:28:55 +010053#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
54#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070055
56#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
57
58/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
59 * IPIF registers are 32 bit
60 */
61#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
62#define XIPIF_V123B_GINTR_ENABLE 0x80000000
63
64#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
65#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
66
67#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
68#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
69 * disabled */
70#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
71#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
72#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
73#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010074#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
Andrei Konovalovae918c02007-07-17 04:04:11 -070075
76#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
77#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
78
79struct xilinx_spi {
80 /* bitbang has to be first */
81 struct spi_bitbang bitbang;
82 struct completion done;
Richard Röjforsd5af91a2009-11-13 12:28:39 +010083 struct resource mem; /* phys mem */
Andrei Konovalovae918c02007-07-17 04:04:11 -070084 void __iomem *regs; /* virt. address of the control registers */
85
86 u32 irq;
87
Andrei Konovalovae918c02007-07-17 04:04:11 -070088 u8 *rx_ptr; /* pointer in the Tx buffer */
89 const u8 *tx_ptr; /* pointer in the Rx buffer */
90 int remaining_bytes; /* the number of bytes left to transfer */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010091 u8 bits_per_word;
Richard Röjfors86fc5932009-11-13 12:28:49 +010092 unsigned int (*read_fn) (void __iomem *);
93 void (*write_fn) (u32, void __iomem *);
Richard Röjforsc9da2e12009-11-13 12:28:55 +010094 void (*tx_fn) (struct xilinx_spi *);
95 void (*rx_fn) (struct xilinx_spi *);
Andrei Konovalovae918c02007-07-17 04:04:11 -070096};
97
Paul Mundt97782142010-01-20 13:49:45 -070098static void xspi_write32(u32 val, void __iomem *addr)
99{
100 iowrite32(val, addr);
101}
102
103static unsigned int xspi_read32(void __iomem *addr)
104{
105 return ioread32(addr);
106}
107
108static void xspi_write32_be(u32 val, void __iomem *addr)
109{
110 iowrite32be(val, addr);
111}
112
113static unsigned int xspi_read32_be(void __iomem *addr)
114{
115 return ioread32be(addr);
116}
117
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100118static void xspi_tx8(struct xilinx_spi *xspi)
119{
120 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
121 xspi->tx_ptr++;
122}
123
124static void xspi_tx16(struct xilinx_spi *xspi)
125{
126 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
127 xspi->tx_ptr += 2;
128}
129
130static void xspi_tx32(struct xilinx_spi *xspi)
131{
132 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
133 xspi->tx_ptr += 4;
134}
135
136static void xspi_rx8(struct xilinx_spi *xspi)
137{
138 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
139 if (xspi->rx_ptr) {
140 *xspi->rx_ptr = data & 0xff;
141 xspi->rx_ptr++;
142 }
143}
144
145static void xspi_rx16(struct xilinx_spi *xspi)
146{
147 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
148 if (xspi->rx_ptr) {
149 *(u16 *)(xspi->rx_ptr) = data & 0xffff;
150 xspi->rx_ptr += 2;
151 }
152}
153
154static void xspi_rx32(struct xilinx_spi *xspi)
155{
156 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
157 if (xspi->rx_ptr) {
158 *(u32 *)(xspi->rx_ptr) = data;
159 xspi->rx_ptr += 4;
160 }
161}
162
Richard Röjfors86fc5932009-11-13 12:28:49 +0100163static void xspi_init_hw(struct xilinx_spi *xspi)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700164{
Richard Röjfors86fc5932009-11-13 12:28:49 +0100165 void __iomem *regs_base = xspi->regs;
166
Andrei Konovalovae918c02007-07-17 04:04:11 -0700167 /* Reset the SPI device */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100168 xspi->write_fn(XIPIF_V123B_RESET_MASK,
169 regs_base + XIPIF_V123B_RESETR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700170 /* Disable all the interrupts just in case */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100171 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700172 /* Enable the global IPIF interrupt */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100173 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
174 regs_base + XIPIF_V123B_DGIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700175 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100176 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700177 /* Disable the transmitter, enable Manual Slave Select Assertion,
178 * put SPI controller into master mode, and enable it */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100179 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100180 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
181 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700182}
183
184static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
185{
186 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
187
188 if (is_on == BITBANG_CS_INACTIVE) {
189 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100190 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700191 } else if (is_on == BITBANG_CS_ACTIVE) {
192 /* Set the SPI clock phase and polarity */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100193 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700194 & ~XSPI_CR_MODE_MASK;
195 if (spi->mode & SPI_CPHA)
196 cr |= XSPI_CR_CPHA;
197 if (spi->mode & SPI_CPOL)
198 cr |= XSPI_CR_CPOL;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100199 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700200
201 /* We do not check spi->max_speed_hz here as the SPI clock
202 * frequency is not software programmable (the IP block design
203 * parameter)
204 */
205
206 /* Activate the chip select */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100207 xspi->write_fn(~(0x0001 << spi->chip_select),
208 xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700209 }
210}
211
212/* spi_bitbang requires custom setup_transfer() to be defined if there is a
213 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100214 * supports 8 or 16 bits per word which cannot be changed in software.
215 * SPI clock can't be changed in software either.
216 * Check for correct bits per word. Chip select delay calculations could be
Andrei Konovalovae918c02007-07-17 04:04:11 -0700217 * added here as soon as bitbang_work() can be made aware of the delay value.
218 */
219static int xilinx_spi_setup_transfer(struct spi_device *spi,
220 struct spi_transfer *t)
221{
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100222 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700223 u8 bits_per_word;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700224
John Linn1a8d3b72009-09-14 08:17:05 +0000225 bits_per_word = (t && t->bits_per_word)
226 ? t->bits_per_word : spi->bits_per_word;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100227 if (bits_per_word != xspi->bits_per_word) {
Andrei Konovalovae918c02007-07-17 04:04:11 -0700228 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
Harvey Harrisonb687d2a2008-04-28 02:14:19 -0700229 __func__, bits_per_word);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700230 return -EINVAL;
231 }
232
Andrei Konovalovae918c02007-07-17 04:04:11 -0700233 return 0;
234}
235
Andrei Konovalovae918c02007-07-17 04:04:11 -0700236static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
237{
238 u8 sr;
239
240 /* Fill the Tx FIFO with as many bytes as possible */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100241 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700242 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
Richard Röjfors86fc5932009-11-13 12:28:49 +0100243 if (xspi->tx_ptr)
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100244 xspi->tx_fn(xspi);
Richard Röjfors86fc5932009-11-13 12:28:49 +0100245 else
246 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100247 xspi->remaining_bytes -= xspi->bits_per_word / 8;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100248 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700249 }
250}
251
252static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
253{
254 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
255 u32 ipif_ier;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700256
257 /* We get here with transmitter inhibited */
258
259 xspi->tx_ptr = t->tx_buf;
260 xspi->rx_ptr = t->rx_buf;
261 xspi->remaining_bytes = t->len;
262 INIT_COMPLETION(xspi->done);
263
Andrei Konovalovae918c02007-07-17 04:04:11 -0700264
265 /* Enable the transmit empty interrupt, which we use to determine
266 * progress on the transmission.
267 */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100268 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
269 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
270 xspi->regs + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700271
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200272 for (;;) {
273 u16 cr;
274 u8 sr;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700275
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200276 xilinx_spi_fill_tx_fifo(xspi);
277
278 /* Start the transfer by not inhibiting the transmitter any
279 * longer
280 */
281 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
282 ~XSPI_CR_TRANS_INHIBIT;
283 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
284
285 wait_for_completion(&xspi->done);
286
287 /* A transmit has just completed. Process received data and
288 * check for more data to transmit. Always inhibit the
289 * transmitter while the Isr refills the transmit register/FIFO,
290 * or make sure it is stopped if we're done.
291 */
292 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
293 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
294 xspi->regs + XSPI_CR_OFFSET);
295
296 /* Read out all the data from the Rx FIFO */
297 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
298 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
299 xspi->rx_fn(xspi);
300 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
301 }
302
303 /* See if there is more data to send */
dan.carpenter@oracle.come33d0852013-06-09 16:07:28 +0300304 if (xspi->remaining_bytes <= 0)
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200305 break;
306 }
Andrei Konovalovae918c02007-07-17 04:04:11 -0700307
308 /* Disable the transmit empty interrupt */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100309 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700310
311 return t->len - xspi->remaining_bytes;
312}
313
314
315/* This driver supports single master mode only. Hence Tx FIFO Empty
316 * is the only interrupt we care about.
317 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
318 * Fault are not to happen.
319 */
320static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
321{
322 struct xilinx_spi *xspi = dev_id;
323 u32 ipif_isr;
324
325 /* Get the IPIF interrupts, and clear them immediately */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100326 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
327 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700328
329 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200330 complete(&xspi->done);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700331 }
332
333 return IRQ_HANDLED;
334}
335
Grant Likelyeae6cb32010-10-14 09:32:53 -0600336static const struct of_device_id xilinx_spi_of_match[] = {
337 { .compatible = "xlnx,xps-spi-2.00.a", },
338 { .compatible = "xlnx,xps-spi-2.00.b", },
339 {}
340};
341MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
Grant Likelyeae6cb32010-10-14 09:32:53 -0600342
Mark Brownd81c0bb2013-07-03 12:05:42 +0100343static int xilinx_spi_probe(struct platform_device *dev)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700344{
Andrei Konovalovae918c02007-07-17 04:04:11 -0700345 struct xilinx_spi *xspi;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100346 struct xspi_platform_data *pdata;
347 struct resource *r;
348 int ret, irq, num_cs = 0, bits_per_word = 8;
349 struct spi_master *master;
Michal Simek082339b2013-06-04 16:02:36 +0200350 u32 tmp;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100351 u8 i;
John Linnff82c582009-01-09 16:01:53 -0700352
Mark Brownd81c0bb2013-07-03 12:05:42 +0100353 pdata = dev->dev.platform_data;
354 if (pdata) {
355 num_cs = pdata->num_chipselect;
356 bits_per_word = pdata->bits_per_word;
357 }
358
359#ifdef CONFIG_OF
360 if (dev->dev.of_node) {
361 const __be32 *prop;
362 int len;
363
364 /* number of slave select bits is required */
365 prop = of_get_property(dev->dev.of_node, "xlnx,num-ss-bits",
366 &len);
367 if (prop && len >= sizeof(*prop))
368 num_cs = __be32_to_cpup(prop);
369 }
370#endif
371
372 if (!num_cs) {
373 dev_err(&dev->dev, "Missing slave select configuration data\n");
374 return -EINVAL;
375 }
376
377 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
378 if (!r)
379 return -ENODEV;
380
381 irq = platform_get_irq(dev, 0);
382 if (irq < 0)
383 return -ENXIO;
384
385 master = spi_alloc_master(&dev->dev, sizeof(struct xilinx_spi));
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100386 if (!master)
Mark Brownd81c0bb2013-07-03 12:05:42 +0100387 return -ENODEV;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700388
David Brownelle7db06b2009-06-17 16:26:04 -0700389 /* the spi->mode bits understood by this driver: */
390 master->mode_bits = SPI_CPOL | SPI_CPHA;
391
Andrei Konovalovae918c02007-07-17 04:04:11 -0700392 xspi = spi_master_get_devdata(master);
393 xspi->bitbang.master = spi_master_get(master);
394 xspi->bitbang.chipselect = xilinx_spi_chipselect;
395 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
396 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700397 init_completion(&xspi->done);
398
Mark Brownd81c0bb2013-07-03 12:05:42 +0100399 xspi->regs = devm_ioremap_resource(&dev->dev, r);
Mark Brownc40537d2013-07-01 20:33:01 +0100400 if (IS_ERR(xspi->regs)) {
401 ret = PTR_ERR(xspi->regs);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700402 goto put_master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700403 }
404
Mark Brownd81c0bb2013-07-03 12:05:42 +0100405 master->bus_num = dev->dev.id;
Grant Likely91565c42010-10-14 08:54:55 -0600406 master->num_chipselect = num_cs;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100407 master->dev.of_node = dev->dev.of_node;
John Linnff82c582009-01-09 16:01:53 -0700408
Mark Brownd81c0bb2013-07-03 12:05:42 +0100409 xspi->mem = *r;
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100410 xspi->irq = irq;
Michal Simek082339b2013-06-04 16:02:36 +0200411
412 /*
413 * Detect endianess on the IP via loop bit in CR. Detection
414 * must be done before reset is sent because incorrect reset
415 * value generates error interrupt.
416 * Setup little endian helper functions first and try to use them
417 * and check if bit was correctly setup or not.
418 */
419 xspi->read_fn = xspi_read32;
420 xspi->write_fn = xspi_write32;
421
422 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
423 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
424 tmp &= XSPI_CR_LOOP;
425 if (tmp != XSPI_CR_LOOP) {
Paul Mundt97782142010-01-20 13:49:45 -0700426 xspi->read_fn = xspi_read32_be;
427 xspi->write_fn = xspi_write32_be;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100428 }
Michal Simek082339b2013-06-04 16:02:36 +0200429
Grant Likely91565c42010-10-14 08:54:55 -0600430 xspi->bits_per_word = bits_per_word;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100431 if (xspi->bits_per_word == 8) {
432 xspi->tx_fn = xspi_tx8;
433 xspi->rx_fn = xspi_rx8;
434 } else if (xspi->bits_per_word == 16) {
435 xspi->tx_fn = xspi_tx16;
436 xspi->rx_fn = xspi_rx16;
437 } else if (xspi->bits_per_word == 32) {
438 xspi->tx_fn = xspi_tx32;
439 xspi->rx_fn = xspi_rx32;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100440 } else {
441 ret = -EINVAL;
Mark Brownc40537d2013-07-01 20:33:01 +0100442 goto put_master;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100443 }
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100444
Andrei Konovalovae918c02007-07-17 04:04:11 -0700445
446 /* SPI controller initializations */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100447 xspi_init_hw(xspi);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700448
449 /* Register for SPI Interrupt */
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100450 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
451 if (ret)
Mark Brownc40537d2013-07-01 20:33:01 +0100452 goto put_master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700453
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100454 ret = spi_bitbang_start(&xspi->bitbang);
455 if (ret) {
Mark Brownd81c0bb2013-07-03 12:05:42 +0100456 dev_err(&dev->dev, "spi_bitbang_start FAILED\n");
Andrei Konovalovae918c02007-07-17 04:04:11 -0700457 goto free_irq;
458 }
459
Mark Brownd81c0bb2013-07-03 12:05:42 +0100460 dev_info(&dev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
461 (unsigned long long)r->start, xspi->regs, xspi->irq);
Grant Likely8fd88212010-10-14 09:04:29 -0600462
Grant Likelyeae6cb32010-10-14 09:32:53 -0600463 if (pdata) {
464 for (i = 0; i < pdata->num_devices; i++)
465 spi_new_device(master, pdata->devices + i);
466 }
Grant Likely8fd88212010-10-14 09:04:29 -0600467
468 platform_set_drvdata(dev, master);
469 return 0;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100470
471free_irq:
472 free_irq(xspi->irq, xspi);
473put_master:
474 spi_master_put(master);
475
476 return ret;
Grant Likely8fd88212010-10-14 09:04:29 -0600477}
478
Grant Likelyfd4a3192012-12-07 16:57:14 +0000479static int xilinx_spi_remove(struct platform_device *dev)
Grant Likely8fd88212010-10-14 09:04:29 -0600480{
Mark Brownd81c0bb2013-07-03 12:05:42 +0100481 struct spi_master *master = platform_get_drvdata(dev);
482 struct xilinx_spi *xspi = spi_master_get_devdata(master);
483
484 spi_bitbang_stop(&xspi->bitbang);
485 free_irq(xspi->irq, xspi);
486
487 spi_master_put(xspi->bitbang.master);
Grant Likely8fd88212010-10-14 09:04:29 -0600488
489 return 0;
490}
491
492/* work with hotplug and coldplug */
493MODULE_ALIAS("platform:" XILINX_SPI_NAME);
494
495static struct platform_driver xilinx_spi_driver = {
496 .probe = xilinx_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000497 .remove = xilinx_spi_remove,
Grant Likely8fd88212010-10-14 09:04:29 -0600498 .driver = {
499 .name = XILINX_SPI_NAME,
500 .owner = THIS_MODULE,
Grant Likelyeae6cb32010-10-14 09:32:53 -0600501 .of_match_table = xilinx_spi_of_match,
Grant Likely8fd88212010-10-14 09:04:29 -0600502 },
503};
Grant Likely940ab882011-10-05 11:29:49 -0600504module_platform_driver(xilinx_spi_driver);
Grant Likely8fd88212010-10-14 09:04:29 -0600505
Andrei Konovalovae918c02007-07-17 04:04:11 -0700506MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
507MODULE_DESCRIPTION("Xilinx SPI driver");
508MODULE_LICENSE("GPL");