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David Gibson26ef5c02005-11-10 11:50:16 +11001#ifndef _ASM_POWERPC_CACHE_H
2#define _ASM_POWERPC_CACHE_H
3
4#ifdef __KERNEL__
5
David Gibson26ef5c02005-11-10 11:50:16 +11006
7/* bytes per L1 cache line */
8#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
9#define L1_CACHE_SHIFT 4
10#define MAX_COPY_PREFETCH 1
Kumar Gala3dfa8772008-06-16 09:41:32 -050011#elif defined(CONFIG_PPC_E500MC)
12#define L1_CACHE_SHIFT 6
13#define MAX_COPY_PREFETCH 4
David Gibson26ef5c02005-11-10 11:50:16 +110014#elif defined(CONFIG_PPC32)
David Gibson26ef5c02005-11-10 11:50:16 +110015#define MAX_COPY_PREFETCH 4
Dave Kleikampe7f75ad2010-03-05 10:43:12 +000016#if defined(CONFIG_PPC_47x)
17#define L1_CACHE_SHIFT 7
18#else
19#define L1_CACHE_SHIFT 5
20#endif
David Gibson26ef5c02005-11-10 11:50:16 +110021#else /* CONFIG_PPC64 */
22#define L1_CACHE_SHIFT 7
23#endif
24
25#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
26
27#define SMP_CACHE_BYTES L1_CACHE_BYTES
David Gibson26ef5c02005-11-10 11:50:16 +110028
29#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
30struct ppc64_caches {
31 u32 dsize; /* L1 d-cache size */
32 u32 dline_size; /* L1 d-cache line size */
33 u32 log_dline_size;
34 u32 dlines_per_page;
35 u32 isize; /* L1 i-cache size */
36 u32 iline_size; /* L1 i-cache line size */
37 u32 log_iline_size;
38 u32 ilines_per_page;
39};
40
41extern struct ppc64_caches ppc64_caches;
42#endif /* __powerpc64__ && ! __ASSEMBLY__ */
43
Tony Breedsbd67fcf2007-07-04 14:04:31 +100044#if !defined(__ASSEMBLY__)
Denys Vlasenko54cb27a2010-02-20 01:03:44 +010045#define __read_mostly __attribute__((__section__(".data..read_mostly")))
Tony Breedsbd67fcf2007-07-04 14:04:31 +100046#endif
47
David Gibson26ef5c02005-11-10 11:50:16 +110048#endif /* __KERNEL__ */
49#endif /* _ASM_POWERPC_CACHE_H */