blob: 211ae46e3e0ca2101d0cf5bb1d8d7039422e95df [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
Sergei Shtylyov35198232007-09-11 22:28:34 +020012 * Copyright (C) 2005-2007 MontaVista Software, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/ide.h>
25
26#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
28#ifdef CONFIG_PPC_PMAC
29#include <asm/prom.h>
30#include <asm/pci-bridge.h>
31#endif
32
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +020033#define DRV_NAME "pdc202xx_new"
34
Sergei Shtylyov47694bb2006-12-10 02:19:13 -080035#undef DEBUG
36
37#ifdef DEBUG
Harvey Harrisoneb639632008-04-26 22:25:20 +020038#define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
Sergei Shtylyov47694bb2006-12-10 02:19:13 -080039#else
40#define DBG(fmt, args...)
41#endif
42
Jesper Juhl3c6bee12006-01-09 20:54:01 -080043static const char *pdc_quirk_drives[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 "QUANTUM FIREBALLlct08 08",
45 "QUANTUM FIREBALLP KA6.4",
46 "QUANTUM FIREBALLP KA9.1",
47 "QUANTUM FIREBALLP LM20.4",
48 "QUANTUM FIREBALLP KX13.6",
49 "QUANTUM FIREBALLP KX20.5",
50 "QUANTUM FIREBALLP KX27.3",
51 "QUANTUM FIREBALLP LM20.5",
52 NULL
53};
54
Sergei Shtylyov47694bb2006-12-10 02:19:13 -080055static u8 max_dma_rate(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070056{
57 u8 mode;
58
Sergei Shtylyov47694bb2006-12-10 02:19:13 -080059 switch(pdev->device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070060 case PCI_DEVICE_ID_PROMISE_20277:
61 case PCI_DEVICE_ID_PROMISE_20276:
62 case PCI_DEVICE_ID_PROMISE_20275:
63 case PCI_DEVICE_ID_PROMISE_20271:
64 case PCI_DEVICE_ID_PROMISE_20269:
65 mode = 4;
66 break;
67 case PCI_DEVICE_ID_PROMISE_20270:
68 case PCI_DEVICE_ID_PROMISE_20268:
69 mode = 3;
70 break;
71 default:
72 return 0;
73 }
Sergei Shtylyov47694bb2006-12-10 02:19:13 -080074
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 return mode;
76}
77
Sergei Shtylyov47694bb2006-12-10 02:19:13 -080078/**
79 * get_indexed_reg - Get indexed register
80 * @hwif: for the port address
81 * @index: index of the indexed register
82 */
83static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
84{
85 u8 value;
86
Bartlomiej Zolnierkiewicz41051a12008-04-28 23:44:42 +020087 outb(index, hwif->dma_base + 1);
88 value = inb(hwif->dma_base + 3);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -080089
90 DBG("index[%02X] value[%02X]\n", index, value);
91 return value;
92}
93
94/**
95 * set_indexed_reg - Set indexed register
96 * @hwif: for the port address
97 * @index: index of the indexed register
98 */
99static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
100{
Bartlomiej Zolnierkiewicz41051a12008-04-28 23:44:42 +0200101 outb(index, hwif->dma_base + 1);
102 outb(value, hwif->dma_base + 3);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800103 DBG("index[%02X] value[%02X]\n", index, value);
104}
105
106/*
107 * ATA Timing Tables based on 133 MHz PLL output clock.
108 *
109 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
110 * the timing registers automatically when "set features" command is
111 * issued to the device. However, if the PLL output clock is 133 MHz,
112 * the following tables must be used.
113 */
114static struct pio_timing {
115 u8 reg0c, reg0d, reg13;
116} pio_timings [] = {
117 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
118 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
119 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
120 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
121 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
122};
123
124static struct mwdma_timing {
125 u8 reg0e, reg0f;
126} mwdma_timings [] = {
127 { 0xdf, 0x5f }, /* MWDMA mode 0 */
128 { 0x6b, 0x27 }, /* MWDMA mode 1 */
129 { 0x69, 0x25 }, /* MWDMA mode 2 */
130};
131
132static struct udma_timing {
133 u8 reg10, reg11, reg12;
134} udma_timings [] = {
135 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
136 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
137 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
138 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
139 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
140 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
141 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
142};
143
Bartlomiej Zolnierkiewiczad4ba7d2008-01-25 22:17:18 +0100144static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145{
146 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100147 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800148 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800150 /*
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200151 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
152 * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800153 * automatically set the timing registers based on 100 MHz PLL output.
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200154 *
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800155 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
156 * chips, we must override the default register settings...
157 */
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100158 if (max_dma_rate(dev) == 4) {
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800159 u8 mode = speed & 0x07;
160
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +0100161 if (speed >= XFER_UDMA_0) {
162 set_indexed_reg(hwif, 0x10 + adj,
163 udma_timings[mode].reg10);
164 set_indexed_reg(hwif, 0x11 + adj,
165 udma_timings[mode].reg11);
166 set_indexed_reg(hwif, 0x12 + adj,
167 udma_timings[mode].reg12);
168 } else {
169 set_indexed_reg(hwif, 0x0e + adj,
170 mwdma_timings[mode].reg0e);
171 set_indexed_reg(hwif, 0x0f + adj,
172 mwdma_timings[mode].reg0f);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800173 }
174 } else if (speed == XFER_UDMA_2) {
175 /* Set tHOLD bit to 0 if using UDMA mode 2 */
176 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
177
178 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
179 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180}
181
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200182static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183{
Bartlomiej Zolnierkiewiczad4ba7d2008-01-25 22:17:18 +0100184 ide_hwif_t *hwif = drive->hwif;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100185 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewiczad4ba7d2008-01-25 22:17:18 +0100186 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
187
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100188 if (max_dma_rate(dev) == 4) {
Bartlomiej Zolnierkiewiczad4ba7d2008-01-25 22:17:18 +0100189 set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
190 set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
191 set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
192 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193}
194
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +0200195static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196{
Bartlomiej Zolnierkiewicz49521f92007-07-09 23:17:58 +0200197 if (get_indexed_reg(hwif, 0x0b) & 0x04)
198 return ATA_CBL_PATA40;
199 else
200 return ATA_CBL_PATA80;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201}
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800202
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100203static void pdcnew_quirkproc(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204{
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200205 const char **list, *m = (char *)&drive->id[ATA_ID_PROD];
Sergei Shtylyovd24ec422007-02-07 18:18:39 +0100206
207 for (list = pdc_quirk_drives; *list != NULL; list++)
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200208 if (strstr(m, *list) != NULL) {
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100209 drive->quirk_list = 2;
210 return;
211 }
212
213 drive->quirk_list = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214}
215
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800216static void pdcnew_reset(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217{
218 /*
219 * Deleted this because it is redundant from the caller.
220 */
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800221 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 HWIF(drive)->channel ? "Secondary" : "Primary");
223}
224
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800225/**
226 * read_counter - Read the byte count registers
227 * @dma_base: for the port address
228 */
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200229static long read_counter(u32 dma_base)
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800230{
231 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
232 u8 cnt0, cnt1, cnt2, cnt3;
233 long count = 0, last;
234 int retry = 3;
235
236 do {
237 last = count;
238
239 /* Read the current count */
240 outb(0x20, pri_dma_base + 0x01);
241 cnt0 = inb(pri_dma_base + 0x03);
242 outb(0x21, pri_dma_base + 0x01);
243 cnt1 = inb(pri_dma_base + 0x03);
244 outb(0x20, sec_dma_base + 0x01);
245 cnt2 = inb(sec_dma_base + 0x03);
246 outb(0x21, sec_dma_base + 0x01);
247 cnt3 = inb(sec_dma_base + 0x03);
248
249 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
250
251 /*
252 * The 30-bit decrementing counter is read in 4 pieces.
253 * Incorrect value may be read when the most significant bytes
254 * are changing...
255 */
256 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
257
258 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
259 cnt0, cnt1, cnt2, cnt3);
260
261 return count;
262}
263
264/**
265 * detect_pll_input_clock - Detect the PLL input clock in Hz.
266 * @dma_base: for the port address
267 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
268 */
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200269static long detect_pll_input_clock(unsigned long dma_base)
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800270{
Albert Lee8006bf52007-07-03 22:28:36 +0200271 struct timeval start_time, end_time;
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800272 long start_count, end_count;
Albert Lee8006bf52007-07-03 22:28:36 +0200273 long pll_input, usec_elapsed;
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800274 u8 scr1;
275
276 start_count = read_counter(dma_base);
Albert Lee8006bf52007-07-03 22:28:36 +0200277 do_gettimeofday(&start_time);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800278
279 /* Start the test mode */
280 outb(0x01, dma_base + 0x01);
281 scr1 = inb(dma_base + 0x03);
282 DBG("scr1[%02X]\n", scr1);
283 outb(scr1 | 0x40, dma_base + 0x03);
284
285 /* Let the counter run for 10 ms. */
286 mdelay(10);
287
288 end_count = read_counter(dma_base);
Albert Lee8006bf52007-07-03 22:28:36 +0200289 do_gettimeofday(&end_time);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800290
291 /* Stop the test mode */
292 outb(0x01, dma_base + 0x01);
293 scr1 = inb(dma_base + 0x03);
294 DBG("scr1[%02X]\n", scr1);
295 outb(scr1 & ~0x40, dma_base + 0x03);
296
297 /*
298 * Calculate the input clock in Hz
299 * (the clock counter is 30 bit wide and counts down)
300 */
Albert Lee8006bf52007-07-03 22:28:36 +0200301 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
302 (end_time.tv_usec - start_time.tv_usec);
Mikael Pettersson56fe23d2007-09-11 22:28:37 +0200303 pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
Albert Lee8006bf52007-07-03 22:28:36 +0200304 (10000000 / usec_elapsed);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800305
306 DBG("start[%ld] end[%ld]\n", start_count, end_count);
307
308 return pll_input;
309}
310
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311#ifdef CONFIG_PPC_PMAC
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200312static void apple_kiwi_init(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700313{
314 struct device_node *np = pci_device_to_OF_node(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 u8 conf;
316
Stephen Rothwell55b61fe2007-05-03 17:26:52 +1000317 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318 return;
319
Bartlomiej Zolnierkiewiczfc212bb2007-10-19 00:30:08 +0200320 if (pdev->revision >= 0x03) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 /* Setup chip magic config stuff (from darwin) */
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800322 pci_read_config_byte (pdev, 0x40, &conf);
323 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325}
326#endif /* CONFIG_PPC_PMAC */
327
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200328static unsigned int init_chipset_pdcnew(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329{
Bartlomiej Zolnierkiewicza326b022008-07-24 22:53:33 +0200330 const char *name = DRV_NAME;
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800331 unsigned long dma_base = pci_resource_start(dev, 4);
332 unsigned long sec_dma_base = dma_base + 0x08;
333 long pll_input, pll_output, ratio;
334 int f, r;
335 u8 pll_ctl0, pll_ctl1;
336
Bartlomiej Zolnierkiewicz01cc6432007-08-20 22:42:56 +0200337 if (dma_base == 0)
338 return -EFAULT;
339
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340#ifdef CONFIG_PPC_PMAC
341 apple_kiwi_init(dev);
342#endif
343
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800344 /* Calculate the required PLL output frequency */
345 switch(max_dma_rate(dev)) {
346 case 4: /* it's 133 MHz for Ultra133 chips */
347 pll_output = 133333333;
348 break;
349 case 3: /* and 100 MHz for Ultra100 chips */
350 default:
351 pll_output = 100000000;
352 break;
353 }
354
355 /*
356 * Detect PLL input clock.
357 * On some systems, where PCI bus is running at non-standard clock rate
358 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
359 * PDC20268 and newer chips employ PLL circuit to help correct timing
360 * registers setting.
361 */
362 pll_input = detect_pll_input_clock(dma_base);
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200363 printk(KERN_INFO "%s %s: PLL input clock is %ld kHz\n",
364 name, pci_name(dev), pll_input / 1000);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800365
366 /* Sanity check */
367 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200368 printk(KERN_ERR "%s %s: Bad PLL input clock %ld Hz, giving up!"
369 "\n", name, pci_name(dev), pll_input);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800370 goto out;
371 }
372
373#ifdef DEBUG
374 DBG("pll_output is %ld Hz\n", pll_output);
375
376 /* Show the current clock value of PLL control register
377 * (maybe already configured by the BIOS)
378 */
379 outb(0x02, sec_dma_base + 0x01);
380 pll_ctl0 = inb(sec_dma_base + 0x03);
381 outb(0x03, sec_dma_base + 0x01);
382 pll_ctl1 = inb(sec_dma_base + 0x03);
383
384 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
385#endif
386
387 /*
388 * Calculate the ratio of F, R and NO
389 * POUT = (F + 2) / (( R + 2) * NO)
390 */
391 ratio = pll_output / (pll_input / 1000);
392 if (ratio < 8600L) { /* 8.6x */
393 /* Using NO = 0x01, R = 0x0d */
394 r = 0x0d;
395 } else if (ratio < 12900L) { /* 12.9x */
396 /* Using NO = 0x01, R = 0x08 */
397 r = 0x08;
398 } else if (ratio < 16100L) { /* 16.1x */
399 /* Using NO = 0x01, R = 0x06 */
400 r = 0x06;
401 } else if (ratio < 64000L) { /* 64x */
402 r = 0x00;
403 } else {
404 /* Invalid ratio */
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200405 printk(KERN_ERR "%s %s: Bad ratio %ld, giving up!\n",
406 name, pci_name(dev), ratio);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800407 goto out;
408 }
409
410 f = (ratio * (r + 2)) / 1000 - 2;
411
412 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
413
414 if (unlikely(f < 0 || f > 127)) {
415 /* Invalid F */
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200416 printk(KERN_ERR "%s %s: F[%d] invalid!\n",
417 name, pci_name(dev), f);
Sergei Shtylyov47694bb2006-12-10 02:19:13 -0800418 goto out;
419 }
420
421 pll_ctl0 = (u8) f;
422 pll_ctl1 = (u8) r;
423
424 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
425
426 outb(0x02, sec_dma_base + 0x01);
427 outb(pll_ctl0, sec_dma_base + 0x03);
428 outb(0x03, sec_dma_base + 0x01);
429 outb(pll_ctl1, sec_dma_base + 0x03);
430
431 /* Wait the PLL circuit to be stable */
432 mdelay(30);
433
434#ifdef DEBUG
435 /*
436 * Show the current clock value of PLL control register
437 */
438 outb(0x02, sec_dma_base + 0x01);
439 pll_ctl0 = inb(sec_dma_base + 0x03);
440 outb(0x03, sec_dma_base + 0x01);
441 pll_ctl1 = inb(sec_dma_base + 0x03);
442
443 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
444#endif
445
446 out:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447 return dev->irq;
448}
449
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200450static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451{
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200452 struct pci_dev *dev2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453
Bartlomiej Zolnierkiewiczeadb6ec2007-12-12 23:31:58 +0100454 dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200455 PCI_FUNC(dev->devfn)));
Bartlomiej Zolnierkiewiczeadb6ec2007-12-12 23:31:58 +0100456
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200457 if (dev2 &&
458 dev2->vendor == dev->vendor &&
459 dev2->device == dev->device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200461 if (dev2->irq != dev->irq) {
462 dev2->irq = dev->irq;
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200463 printk(KERN_INFO DRV_NAME " %s: PCI config space "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200464 "interrupt fixed\n", pci_name(dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465 }
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200466
467 return dev2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200470 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471}
472
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200473static const struct ide_port_ops pdcnew_port_ops = {
474 .set_pio_mode = pdcnew_set_pio_mode,
475 .set_dma_mode = pdcnew_set_dma_mode,
476 .quirkproc = pdcnew_quirkproc,
477 .resetproc = pdcnew_reset,
478 .cable_detect = pdcnew_cable_detect,
479};
480
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200481#define DECLARE_PDCNEW_DEV(udma) \
Bartlomiej Zolnierkiewicz05d7e6c2007-10-19 00:30:10 +0200482 { \
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200483 .name = DRV_NAME, \
Bartlomiej Zolnierkiewicz05d7e6c2007-10-19 00:30:10 +0200484 .init_chipset = init_chipset_pdcnew, \
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200485 .port_ops = &pdcnew_port_ops, \
Bartlomiej Zolnierkiewicz05d7e6c2007-10-19 00:30:10 +0200486 .host_flags = IDE_HFLAG_POST_SET_MODE | \
Bartlomiej Zolnierkiewiczed67b922007-10-19 00:30:10 +0200487 IDE_HFLAG_ERROR_STOPS_FIFO | \
Bartlomiej Zolnierkiewicz05d7e6c2007-10-19 00:30:10 +0200488 IDE_HFLAG_OFF_BOARD, \
489 .pio_mask = ATA_PIO4, \
490 .mwdma_mask = ATA_MWDMA2, \
491 .udma_mask = udma, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492 }
Bartlomiej Zolnierkiewicz05d7e6c2007-10-19 00:30:10 +0200493
Bartlomiej Zolnierkiewicz85620432007-10-20 00:32:34 +0200494static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200495 /* 0: PDC202{68,70} */ DECLARE_PDCNEW_DEV(ATA_UDMA5),
496 /* 1: PDC202{69,71,75,76,77} */ DECLARE_PDCNEW_DEV(ATA_UDMA6),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497};
498
499/**
500 * pdc202new_init_one - called when a pdc202xx is found
501 * @dev: the pdc202new device
502 * @id: the matching pci id
503 *
504 * Called when the PCI registration layer (or the IDE initialization)
505 * finds a device matching our IDE device tables.
506 */
507
508static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
509{
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200510 const struct ide_port_info *d = &pdcnew_chipsets[id->driver_data];
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200511 struct pci_dev *bridge = dev->bus->self;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200513 if (dev->device == PCI_DEVICE_ID_PROMISE_20270 && bridge &&
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200514 bridge->vendor == PCI_VENDOR_ID_DEC &&
515 bridge->device == PCI_DEVICE_ID_DEC_21150) {
516 struct pci_dev *dev2;
517
518 if (PCI_SLOT(dev->devfn) & 2)
519 return -ENODEV;
520
521 dev2 = pdc20270_get_dev2(dev);
522
523 if (dev2) {
Bartlomiej Zolnierkiewicz6cdf6eb2008-07-24 22:53:14 +0200524 int ret = ide_pci_init_two(dev, dev2, d, NULL);
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200525 if (ret < 0)
526 pci_dev_put(dev2);
527 return ret;
528 }
529 }
530
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200531 if (dev->device == PCI_DEVICE_ID_PROMISE_20276 && bridge &&
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200532 bridge->vendor == PCI_VENDOR_ID_INTEL &&
533 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
534 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200535 printk(KERN_INFO DRV_NAME " %s: attached to I2O RAID controller,"
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +0200536 " skipping\n", pci_name(dev));
Bartlomiej Zolnierkiewicz099b1f42007-10-19 00:30:09 +0200537 return -ENODEV;
538 }
539
Bartlomiej Zolnierkiewicz6cdf6eb2008-07-24 22:53:14 +0200540 return ide_pci_init_one(dev, d, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541}
542
Bartlomiej Zolnierkiewiczd69c8f82008-07-24 22:53:23 +0200543static void __devexit pdc202new_remove(struct pci_dev *dev)
544{
545 struct ide_host *host = pci_get_drvdata(dev);
546 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
547
548 ide_pci_remove(dev);
549 pci_dev_put(dev2);
550}
551
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +0200552static const struct pci_device_id pdc202new_pci_tbl[] = {
553 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
554 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200555 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 0 },
556 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 1 },
557 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 1 },
558 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 1 },
559 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 1 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 { 0, },
561};
562MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
563
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200564static struct pci_driver pdc202new_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 .name = "Promise_IDE",
566 .id_table = pdc202new_pci_tbl,
567 .probe = pdc202new_init_one,
Adrian Bunka69999e2008-08-18 21:40:03 +0200568 .remove = __devexit_p(pdc202new_remove),
Bartlomiej Zolnierkiewiczfeb22b72008-10-10 22:39:32 +0200569 .suspend = ide_pci_suspend,
570 .resume = ide_pci_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571};
572
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +0100573static int __init pdc202new_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200575 return ide_pci_register_driver(&pdc202new_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576}
577
Bartlomiej Zolnierkiewiczd69c8f82008-07-24 22:53:23 +0200578static void __exit pdc202new_ide_exit(void)
579{
Bartlomiej Zolnierkiewicza9ab09e2008-10-13 21:39:41 +0200580 pci_unregister_driver(&pdc202new_pci_driver);
Bartlomiej Zolnierkiewiczd69c8f82008-07-24 22:53:23 +0200581}
582
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583module_init(pdc202new_ide_init);
Bartlomiej Zolnierkiewiczd69c8f82008-07-24 22:53:23 +0200584module_exit(pdc202new_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700585
586MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
587MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
588MODULE_LICENSE("GPL");