Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 1 | /* |
| 2 | * EHRPWM PWM driver |
| 3 | * |
| 4 | * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/pwm.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/err.h> |
| 26 | #include <linux/clk.h> |
| 27 | #include <linux/pm_runtime.h> |
| 28 | |
| 29 | /* EHRPWM registers and bits definitions */ |
| 30 | |
| 31 | /* Time base module registers */ |
| 32 | #define TBCTL 0x00 |
| 33 | #define TBPRD 0x0A |
| 34 | |
| 35 | #define TBCTL_RUN_MASK (BIT(15) | BIT(14)) |
| 36 | #define TBCTL_STOP_NEXT 0 |
| 37 | #define TBCTL_STOP_ON_CYCLE BIT(14) |
| 38 | #define TBCTL_FREE_RUN (BIT(15) | BIT(14)) |
| 39 | #define TBCTL_PRDLD_MASK BIT(3) |
| 40 | #define TBCTL_PRDLD_SHDW 0 |
| 41 | #define TBCTL_PRDLD_IMDT BIT(3) |
| 42 | #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \ |
| 43 | BIT(8) | BIT(7)) |
| 44 | #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0)) |
| 45 | #define TBCTL_CTRMODE_UP 0 |
| 46 | #define TBCTL_CTRMODE_DOWN BIT(0) |
| 47 | #define TBCTL_CTRMODE_UPDOWN BIT(1) |
| 48 | #define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0)) |
| 49 | |
| 50 | #define TBCTL_HSPCLKDIV_SHIFT 7 |
| 51 | #define TBCTL_CLKDIV_SHIFT 10 |
| 52 | |
| 53 | #define CLKDIV_MAX 7 |
| 54 | #define HSPCLKDIV_MAX 7 |
| 55 | #define PERIOD_MAX 0xFFFF |
| 56 | |
| 57 | /* compare module registers */ |
| 58 | #define CMPA 0x12 |
| 59 | #define CMPB 0x14 |
| 60 | |
| 61 | /* Action qualifier module registers */ |
| 62 | #define AQCTLA 0x16 |
| 63 | #define AQCTLB 0x18 |
| 64 | #define AQSFRC 0x1A |
| 65 | #define AQCSFRC 0x1C |
| 66 | |
| 67 | #define AQCTL_CBU_MASK (BIT(9) | BIT(8)) |
| 68 | #define AQCTL_CBU_FRCLOW BIT(8) |
| 69 | #define AQCTL_CBU_FRCHIGH BIT(9) |
| 70 | #define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8)) |
| 71 | #define AQCTL_CAU_MASK (BIT(5) | BIT(4)) |
| 72 | #define AQCTL_CAU_FRCLOW BIT(4) |
| 73 | #define AQCTL_CAU_FRCHIGH BIT(5) |
| 74 | #define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4)) |
| 75 | #define AQCTL_PRD_MASK (BIT(3) | BIT(2)) |
| 76 | #define AQCTL_PRD_FRCLOW BIT(2) |
| 77 | #define AQCTL_PRD_FRCHIGH BIT(3) |
| 78 | #define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2)) |
| 79 | #define AQCTL_ZRO_MASK (BIT(1) | BIT(0)) |
| 80 | #define AQCTL_ZRO_FRCLOW BIT(0) |
| 81 | #define AQCTL_ZRO_FRCHIGH BIT(1) |
| 82 | #define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0)) |
| 83 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 84 | #define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \ |
| 85 | AQCTL_ZRO_FRCHIGH) |
| 86 | #define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \ |
| 87 | AQCTL_ZRO_FRCLOW) |
| 88 | #define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \ |
| 89 | AQCTL_ZRO_FRCHIGH) |
| 90 | #define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \ |
| 91 | AQCTL_ZRO_FRCLOW) |
| 92 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 93 | #define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6)) |
| 94 | #define AQSFRC_RLDCSF_ZRO 0 |
| 95 | #define AQSFRC_RLDCSF_PRD BIT(6) |
| 96 | #define AQSFRC_RLDCSF_ZROPRD BIT(7) |
| 97 | #define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6)) |
| 98 | |
| 99 | #define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2)) |
| 100 | #define AQCSFRC_CSFB_FRCDIS 0 |
| 101 | #define AQCSFRC_CSFB_FRCLOW BIT(2) |
| 102 | #define AQCSFRC_CSFB_FRCHIGH BIT(3) |
| 103 | #define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2)) |
| 104 | #define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0)) |
| 105 | #define AQCSFRC_CSFA_FRCDIS 0 |
| 106 | #define AQCSFRC_CSFA_FRCLOW BIT(0) |
| 107 | #define AQCSFRC_CSFA_FRCHIGH BIT(1) |
| 108 | #define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) |
| 109 | |
| 110 | #define NUM_PWM_CHANNEL 2 /* EHRPWM channels */ |
| 111 | |
| 112 | struct ehrpwm_pwm_chip { |
| 113 | struct pwm_chip chip; |
| 114 | unsigned int clk_rate; |
| 115 | void __iomem *mmio_base; |
Philip, Avinash | 01b2d45 | 2012-09-06 10:44:25 +0530 | [diff] [blame] | 116 | unsigned long period_cycles[NUM_PWM_CHANNEL]; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 117 | enum pwm_polarity polarity[NUM_PWM_CHANNEL]; |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame^] | 118 | struct clk *tbclk; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 119 | }; |
| 120 | |
| 121 | static inline struct ehrpwm_pwm_chip *to_ehrpwm_pwm_chip(struct pwm_chip *chip) |
| 122 | { |
| 123 | return container_of(chip, struct ehrpwm_pwm_chip, chip); |
| 124 | } |
| 125 | |
| 126 | static void ehrpwm_write(void *base, int offset, unsigned int val) |
| 127 | { |
| 128 | writew(val & 0xFFFF, base + offset); |
| 129 | } |
| 130 | |
| 131 | static void ehrpwm_modify(void *base, int offset, |
| 132 | unsigned short mask, unsigned short val) |
| 133 | { |
| 134 | unsigned short regval; |
| 135 | |
| 136 | regval = readw(base + offset); |
| 137 | regval &= ~mask; |
| 138 | regval |= val & mask; |
| 139 | writew(regval, base + offset); |
| 140 | } |
| 141 | |
| 142 | /** |
| 143 | * set_prescale_div - Set up the prescaler divider function |
| 144 | * @rqst_prescaler: prescaler value min |
| 145 | * @prescale_div: prescaler value set |
| 146 | * @tb_clk_div: Time Base Control prescaler bits |
| 147 | */ |
| 148 | static int set_prescale_div(unsigned long rqst_prescaler, |
| 149 | unsigned short *prescale_div, unsigned short *tb_clk_div) |
| 150 | { |
| 151 | unsigned int clkdiv, hspclkdiv; |
| 152 | |
| 153 | for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { |
| 154 | for (hspclkdiv = 0; hspclkdiv <= HSPCLKDIV_MAX; hspclkdiv++) { |
| 155 | |
| 156 | /* |
| 157 | * calculations for prescaler value : |
| 158 | * prescale_div = HSPCLKDIVIDER * CLKDIVIDER. |
| 159 | * HSPCLKDIVIDER = 2 ** hspclkdiv |
| 160 | * CLKDIVIDER = (1), if clkdiv == 0 *OR* |
| 161 | * (2 * clkdiv), if clkdiv != 0 |
| 162 | * |
| 163 | * Configure prescale_div value such that period |
| 164 | * register value is less than 65535. |
| 165 | */ |
| 166 | |
| 167 | *prescale_div = (1 << clkdiv) * |
| 168 | (hspclkdiv ? (hspclkdiv * 2) : 1); |
| 169 | if (*prescale_div > rqst_prescaler) { |
| 170 | *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | |
| 171 | (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT); |
| 172 | return 0; |
| 173 | } |
| 174 | } |
| 175 | } |
| 176 | return 1; |
| 177 | } |
| 178 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 179 | static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan) |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 180 | { |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 181 | int aqctl_reg; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 182 | unsigned short aqctl_val, aqctl_mask; |
| 183 | |
| 184 | /* |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 185 | * Configure PWM output to HIGH/LOW level on counter |
| 186 | * reaches compare register value and LOW/HIGH level |
| 187 | * on counter value reaches period register value and |
| 188 | * zero value on counter |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 189 | */ |
| 190 | if (chan == 1) { |
| 191 | aqctl_reg = AQCTLB; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 192 | aqctl_mask = AQCTL_CBU_MASK; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 193 | |
| 194 | if (pc->polarity[chan] == PWM_POLARITY_INVERSED) |
| 195 | aqctl_val = AQCTL_CHANB_POLINVERSED; |
| 196 | else |
| 197 | aqctl_val = AQCTL_CHANB_POLNORMAL; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 198 | } else { |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 199 | aqctl_reg = AQCTLA; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 200 | aqctl_mask = AQCTL_CAU_MASK; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 201 | |
| 202 | if (pc->polarity[chan] == PWM_POLARITY_INVERSED) |
| 203 | aqctl_val = AQCTL_CHANA_POLINVERSED; |
| 204 | else |
| 205 | aqctl_val = AQCTL_CHANA_POLNORMAL; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 206 | } |
| 207 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 208 | aqctl_mask |= AQCTL_PRD_MASK | AQCTL_ZRO_MASK; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 209 | ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | /* |
| 213 | * period_ns = 10^9 * (ps_divval * period_cycles) / PWM_CLK_RATE |
| 214 | * duty_ns = 10^9 * (ps_divval * duty_cycles) / PWM_CLK_RATE |
| 215 | */ |
| 216 | static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
| 217 | int duty_ns, int period_ns) |
| 218 | { |
| 219 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 220 | unsigned long long c; |
| 221 | unsigned long period_cycles, duty_cycles; |
| 222 | unsigned short ps_divval, tb_divval; |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 223 | int i, cmp_reg; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 224 | |
Thierry Reding | c2d476a | 2012-09-02 22:13:40 +0200 | [diff] [blame] | 225 | if (period_ns > NSEC_PER_SEC) |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 226 | return -ERANGE; |
| 227 | |
| 228 | c = pc->clk_rate; |
| 229 | c = c * period_ns; |
| 230 | do_div(c, NSEC_PER_SEC); |
| 231 | period_cycles = (unsigned long)c; |
| 232 | |
| 233 | if (period_cycles < 1) { |
| 234 | period_cycles = 1; |
| 235 | duty_cycles = 1; |
| 236 | } else { |
| 237 | c = pc->clk_rate; |
| 238 | c = c * duty_ns; |
| 239 | do_div(c, NSEC_PER_SEC); |
| 240 | duty_cycles = (unsigned long)c; |
| 241 | } |
| 242 | |
Philip, Avinash | 01b2d45 | 2012-09-06 10:44:25 +0530 | [diff] [blame] | 243 | /* |
| 244 | * Period values should be same for multiple PWM channels as IP uses |
| 245 | * same period register for multiple channels. |
| 246 | */ |
| 247 | for (i = 0; i < NUM_PWM_CHANNEL; i++) { |
| 248 | if (pc->period_cycles[i] && |
| 249 | (pc->period_cycles[i] != period_cycles)) { |
| 250 | /* |
| 251 | * Allow channel to reconfigure period if no other |
| 252 | * channels being configured. |
| 253 | */ |
| 254 | if (i == pwm->hwpwm) |
| 255 | continue; |
| 256 | |
| 257 | dev_err(chip->dev, "Period value conflicts with channel %d\n", |
| 258 | i); |
| 259 | return -EINVAL; |
| 260 | } |
| 261 | } |
| 262 | |
| 263 | pc->period_cycles[pwm->hwpwm] = period_cycles; |
| 264 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 265 | /* Configure clock prescaler to support Low frequency PWM wave */ |
| 266 | if (set_prescale_div(period_cycles/PERIOD_MAX, &ps_divval, |
| 267 | &tb_divval)) { |
| 268 | dev_err(chip->dev, "Unsupported values\n"); |
| 269 | return -EINVAL; |
| 270 | } |
| 271 | |
| 272 | pm_runtime_get_sync(chip->dev); |
| 273 | |
| 274 | /* Update clock prescaler values */ |
| 275 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); |
| 276 | |
| 277 | /* Update period & duty cycle with presacler division */ |
| 278 | period_cycles = period_cycles / ps_divval; |
| 279 | duty_cycles = duty_cycles / ps_divval; |
| 280 | |
| 281 | /* Configure shadow loading on Period register */ |
| 282 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW); |
| 283 | |
| 284 | ehrpwm_write(pc->mmio_base, TBPRD, period_cycles); |
| 285 | |
| 286 | /* Configure ehrpwm counter for up-count mode */ |
| 287 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, |
| 288 | TBCTL_CTRMODE_UP); |
| 289 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 290 | if (pwm->hwpwm == 1) |
| 291 | /* Channel 1 configured with compare B register */ |
| 292 | cmp_reg = CMPB; |
| 293 | else |
| 294 | /* Channel 0 configured with compare A register */ |
| 295 | cmp_reg = CMPA; |
| 296 | |
| 297 | ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); |
| 298 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 299 | pm_runtime_put_sync(chip->dev); |
| 300 | return 0; |
| 301 | } |
| 302 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 303 | static int ehrpwm_pwm_set_polarity(struct pwm_chip *chip, |
| 304 | struct pwm_device *pwm, enum pwm_polarity polarity) |
| 305 | { |
| 306 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 307 | |
| 308 | /* Configuration of polarity in hardware delayed, do at enable */ |
| 309 | pc->polarity[pwm->hwpwm] = polarity; |
| 310 | return 0; |
| 311 | } |
| 312 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 313 | static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 314 | { |
| 315 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 316 | unsigned short aqcsfrc_val, aqcsfrc_mask; |
| 317 | |
| 318 | /* Leave clock enabled on enabling PWM */ |
| 319 | pm_runtime_get_sync(chip->dev); |
| 320 | |
| 321 | /* Disabling Action Qualifier on PWM output */ |
| 322 | if (pwm->hwpwm) { |
| 323 | aqcsfrc_val = AQCSFRC_CSFB_FRCDIS; |
| 324 | aqcsfrc_mask = AQCSFRC_CSFB_MASK; |
| 325 | } else { |
| 326 | aqcsfrc_val = AQCSFRC_CSFA_FRCDIS; |
| 327 | aqcsfrc_mask = AQCSFRC_CSFA_MASK; |
| 328 | } |
| 329 | |
| 330 | /* Changes to shadow mode */ |
| 331 | ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, |
| 332 | AQSFRC_RLDCSF_ZRO); |
| 333 | |
| 334 | ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); |
| 335 | |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 336 | /* Channels polarity can be configured from action qualifier module */ |
| 337 | configure_polarity(pc, pwm->hwpwm); |
| 338 | |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame^] | 339 | /* Enable TBCLK before enabling PWM device */ |
| 340 | clk_enable(pc->tbclk); |
| 341 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 342 | /* Enable time counter for free_run */ |
| 343 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN); |
| 344 | return 0; |
| 345 | } |
| 346 | |
| 347 | static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 348 | { |
| 349 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 350 | unsigned short aqcsfrc_val, aqcsfrc_mask; |
| 351 | |
| 352 | /* Action Qualifier puts PWM output low forcefully */ |
| 353 | if (pwm->hwpwm) { |
| 354 | aqcsfrc_val = AQCSFRC_CSFB_FRCLOW; |
| 355 | aqcsfrc_mask = AQCSFRC_CSFB_MASK; |
| 356 | } else { |
| 357 | aqcsfrc_val = AQCSFRC_CSFA_FRCLOW; |
| 358 | aqcsfrc_mask = AQCSFRC_CSFA_MASK; |
| 359 | } |
| 360 | |
| 361 | /* |
| 362 | * Changes to immediate action on Action Qualifier. This puts |
| 363 | * Action Qualifier control on PWM output from next TBCLK |
| 364 | */ |
| 365 | ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, |
| 366 | AQSFRC_RLDCSF_IMDT); |
| 367 | |
| 368 | ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); |
| 369 | |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame^] | 370 | /* Disabling TBCLK on PWM disable */ |
| 371 | clk_disable(pc->tbclk); |
| 372 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 373 | /* Stop Time base counter */ |
| 374 | ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT); |
| 375 | |
| 376 | /* Disable clock on PWM disable */ |
| 377 | pm_runtime_put_sync(chip->dev); |
| 378 | } |
| 379 | |
| 380 | static void ehrpwm_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
| 381 | { |
Philip, Avinash | 01b2d45 | 2012-09-06 10:44:25 +0530 | [diff] [blame] | 382 | struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip); |
| 383 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 384 | if (test_bit(PWMF_ENABLED, &pwm->flags)) { |
| 385 | dev_warn(chip->dev, "Removing PWM device without disabling\n"); |
| 386 | pm_runtime_put_sync(chip->dev); |
| 387 | } |
Philip, Avinash | 01b2d45 | 2012-09-06 10:44:25 +0530 | [diff] [blame] | 388 | |
| 389 | /* set period value to zero on free */ |
| 390 | pc->period_cycles[pwm->hwpwm] = 0; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 391 | } |
| 392 | |
| 393 | static const struct pwm_ops ehrpwm_pwm_ops = { |
| 394 | .free = ehrpwm_pwm_free, |
| 395 | .config = ehrpwm_pwm_config, |
Philip, Avinash | daa5629 | 2012-09-06 10:40:03 +0530 | [diff] [blame] | 396 | .set_polarity = ehrpwm_pwm_set_polarity, |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 397 | .enable = ehrpwm_pwm_enable, |
| 398 | .disable = ehrpwm_pwm_disable, |
| 399 | .owner = THIS_MODULE, |
| 400 | }; |
| 401 | |
| 402 | static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) |
| 403 | { |
| 404 | int ret; |
| 405 | struct resource *r; |
| 406 | struct clk *clk; |
| 407 | struct ehrpwm_pwm_chip *pc; |
| 408 | |
| 409 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
| 410 | if (!pc) { |
| 411 | dev_err(&pdev->dev, "failed to allocate memory\n"); |
| 412 | return -ENOMEM; |
| 413 | } |
| 414 | |
| 415 | clk = devm_clk_get(&pdev->dev, "fck"); |
| 416 | if (IS_ERR(clk)) { |
| 417 | dev_err(&pdev->dev, "failed to get clock\n"); |
| 418 | return PTR_ERR(clk); |
| 419 | } |
| 420 | |
| 421 | pc->clk_rate = clk_get_rate(clk); |
| 422 | if (!pc->clk_rate) { |
| 423 | dev_err(&pdev->dev, "failed to get clock rate\n"); |
| 424 | return -EINVAL; |
| 425 | } |
| 426 | |
| 427 | pc->chip.dev = &pdev->dev; |
| 428 | pc->chip.ops = &ehrpwm_pwm_ops; |
| 429 | pc->chip.base = -1; |
| 430 | pc->chip.npwm = NUM_PWM_CHANNEL; |
| 431 | |
| 432 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 433 | if (!r) { |
| 434 | dev_err(&pdev->dev, "no memory resource defined\n"); |
| 435 | return -ENODEV; |
| 436 | } |
| 437 | |
| 438 | pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r); |
Axel Lin | 2ffdc9a | 2012-08-03 21:43:54 +0800 | [diff] [blame] | 439 | if (!pc->mmio_base) |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 440 | return -EADDRNOTAVAIL; |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 441 | |
Philip, Avinash | d91861d | 2012-11-27 14:18:12 +0530 | [diff] [blame^] | 442 | /* Acquire tbclk for Time Base EHRPWM submodule */ |
| 443 | pc->tbclk = devm_clk_get(&pdev->dev, "tbclk"); |
| 444 | if (IS_ERR(pc->tbclk)) { |
| 445 | dev_err(&pdev->dev, "Failed to get tbclk\n"); |
| 446 | return PTR_ERR(pc->tbclk); |
| 447 | } |
| 448 | |
Philip, Avinash | 19891b2 | 2012-07-25 16:58:19 +0530 | [diff] [blame] | 449 | ret = pwmchip_add(&pc->chip); |
| 450 | if (ret < 0) { |
| 451 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); |
| 452 | return ret; |
| 453 | } |
| 454 | |
| 455 | pm_runtime_enable(&pdev->dev); |
| 456 | platform_set_drvdata(pdev, pc); |
| 457 | return 0; |
| 458 | } |
| 459 | |
| 460 | static int __devexit ehrpwm_pwm_remove(struct platform_device *pdev) |
| 461 | { |
| 462 | struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev); |
| 463 | |
| 464 | pm_runtime_put_sync(&pdev->dev); |
| 465 | pm_runtime_disable(&pdev->dev); |
| 466 | return pwmchip_remove(&pc->chip); |
| 467 | } |
| 468 | |
| 469 | static struct platform_driver ehrpwm_pwm_driver = { |
| 470 | .driver = { |
| 471 | .name = "ehrpwm", |
| 472 | }, |
| 473 | .probe = ehrpwm_pwm_probe, |
| 474 | .remove = __devexit_p(ehrpwm_pwm_remove), |
| 475 | }; |
| 476 | |
| 477 | module_platform_driver(ehrpwm_pwm_driver); |
| 478 | |
| 479 | MODULE_DESCRIPTION("EHRPWM PWM driver"); |
| 480 | MODULE_AUTHOR("Texas Instruments"); |
| 481 | MODULE_LICENSE("GPL"); |