Christian König | d93f793 | 2013-05-23 12:10:04 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 20 | * |
| 21 | * The above copyright notice and this permission notice (including the |
| 22 | * next paragraph) shall be included in all copies or substantial portions |
| 23 | * of the Software. |
| 24 | * |
| 25 | * Authors: Christian König <christian.koenig@amd.com> |
| 26 | */ |
| 27 | |
| 28 | #include <linux/firmware.h> |
| 29 | #include <drm/drmP.h> |
| 30 | #include "radeon.h" |
| 31 | #include "radeon_asic.h" |
| 32 | #include "cikd.h" |
| 33 | |
| 34 | int vce_v2_0_resume(struct radeon_device *rdev) |
| 35 | { |
| 36 | uint64_t addr = rdev->vce.gpu_addr; |
| 37 | uint32_t size; |
| 38 | |
| 39 | WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); |
| 40 | WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); |
| 41 | WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); |
| 42 | WREG32(VCE_CLOCK_GATING_B, 0xf7); |
| 43 | |
| 44 | WREG32(VCE_LMI_CTRL, 0x00398000); |
| 45 | WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); |
| 46 | WREG32(VCE_LMI_SWAP_CNTL, 0); |
| 47 | WREG32(VCE_LMI_SWAP_CNTL1, 0); |
| 48 | WREG32(VCE_LMI_VM_CTRL, 0); |
| 49 | |
| 50 | size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size); |
| 51 | WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); |
| 52 | WREG32(VCE_VCPU_CACHE_SIZE0, size); |
| 53 | |
| 54 | addr += size; |
| 55 | size = RADEON_VCE_STACK_SIZE; |
| 56 | WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); |
| 57 | WREG32(VCE_VCPU_CACHE_SIZE1, size); |
| 58 | |
| 59 | addr += size; |
| 60 | size = RADEON_VCE_HEAP_SIZE; |
| 61 | WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); |
| 62 | WREG32(VCE_VCPU_CACHE_SIZE2, size); |
| 63 | |
| 64 | WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); |
| 65 | |
| 66 | WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, |
| 67 | ~VCE_SYS_INT_TRAP_INTERRUPT_EN); |
| 68 | |
| 69 | return 0; |
| 70 | } |