blob: 79e5aa2250c89d48541d8d9eb263410c2aa66ac6 [file] [log] [blame]
Marek Vasut646781d2012-08-03 17:26:11 +02001/*
2 * Freescale MXS SPI master driver
3 *
4 * Copyright 2012 DENX Software Engineering, GmbH.
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
7 *
8 * Rework and transition to new API by:
9 * Marek Vasut <marex@denx.de>
10 *
11 * Based on previous attempt by:
12 * Fabio Estevam <fabio.estevam@freescale.com>
13 *
14 * Based on code from U-Boot bootloader by:
15 * Marek Vasut <marex@denx.de>
16 *
17 * Based on spi-stmp.c, which is:
18 * Author: Dmitry Pervushin <dimka@embeddedalley.com>
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 */
30
31#include <linux/kernel.h>
32#include <linux/init.h>
33#include <linux/ioport.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/of_gpio.h>
37#include <linux/platform_device.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/dma-mapping.h>
41#include <linux/dmaengine.h>
42#include <linux/highmem.h>
43#include <linux/clk.h>
44#include <linux/err.h>
45#include <linux/completion.h>
46#include <linux/gpio.h>
47#include <linux/regulator/consumer.h>
48#include <linux/module.h>
Marek Vasut646781d2012-08-03 17:26:11 +020049#include <linux/stmp_device.h>
50#include <linux/spi/spi.h>
51#include <linux/spi/mxs-spi.h>
52
53#define DRIVER_NAME "mxs-spi"
54
Marek Vasut010b4812012-09-04 04:40:15 +020055/* Use 10S timeout for very long transfers, it should suffice. */
56#define SSP_TIMEOUT 10000
Marek Vasut646781d2012-08-03 17:26:11 +020057
Marek Vasut474afc02012-08-03 17:26:13 +020058#define SG_MAXLEN 0xff00
59
Trent Piepho28cad122013-10-01 13:14:50 -070060/*
61 * Flags for txrx functions. More efficient that using an argument register for
62 * each one.
63 */
64#define TXRX_WRITE (1<<0) /* This is a write */
65#define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
66
Marek Vasut646781d2012-08-03 17:26:11 +020067struct mxs_spi {
68 struct mxs_ssp ssp;
Marek Vasut474afc02012-08-03 17:26:13 +020069 struct completion c;
Trent Piephoa5609432013-10-01 13:15:47 -070070 unsigned int sck; /* Rate requested (vs actual) */
Marek Vasut646781d2012-08-03 17:26:11 +020071};
72
73static int mxs_spi_setup_transfer(struct spi_device *dev,
Trent Piephoaa9e0c62013-10-01 13:15:40 -070074 const struct spi_transfer *t)
Marek Vasut646781d2012-08-03 17:26:11 +020075{
76 struct mxs_spi *spi = spi_master_get_devdata(dev->master);
77 struct mxs_ssp *ssp = &spi->ssp;
Trent Piephoaa9e0c62013-10-01 13:15:40 -070078 const unsigned int hz = min(dev->max_speed_hz, t->speed_hz);
Marek Vasut646781d2012-08-03 17:26:11 +020079
Marek Vasut646781d2012-08-03 17:26:11 +020080 if (hz == 0) {
Trent Piephoaa9e0c62013-10-01 13:15:40 -070081 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n");
Marek Vasut646781d2012-08-03 17:26:11 +020082 return -EINVAL;
83 }
84
Trent Piephoa5609432013-10-01 13:15:47 -070085 if (hz != spi->sck) {
86 mxs_ssp_set_clk_rate(ssp, hz);
87 /*
88 * Save requested rate, hz, rather than the actual rate,
89 * ssp->clk_rate. Otherwise we would set the rate every trasfer
90 * when the actual rate is not quite the same as requested rate.
91 */
92 spi->sck = hz;
93 /*
94 * Perhaps we should return an error if the actual clock is
95 * nowhere close to what was requested?
96 */
97 }
Marek Vasut646781d2012-08-03 17:26:11 +020098
Trent Piepho58f46e42013-10-01 13:14:25 -070099 writel(BM_SSP_CTRL0_LOCK_CS,
100 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
Marek Vasut646781d2012-08-03 17:26:11 +0200101
102 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
Trent Piephoaa9e0c62013-10-01 13:15:40 -0700103 BF_SSP_CTRL1_WORD_LENGTH(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
104 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
105 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
106 ssp->base + HW_SSP_CTRL1(ssp));
Marek Vasut646781d2012-08-03 17:26:11 +0200107
108 writel(0x0, ssp->base + HW_SSP_CMD0);
109 writel(0x0, ssp->base + HW_SSP_CMD1);
110
111 return 0;
112}
113
Trent Piepho42e182f2013-10-01 13:15:54 -0700114static u32 mxs_spi_cs_to_reg(unsigned cs)
Marek Vasut646781d2012-08-03 17:26:11 +0200115{
Trent Piepho42e182f2013-10-01 13:15:54 -0700116 u32 select = 0;
Marek Vasut646781d2012-08-03 17:26:11 +0200117
118 /*
119 * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
120 *
121 * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
122 * in HW_SSP_CTRL0 register do have multiple usage, please refer to
123 * the datasheet for further details. In SPI mode, they are used to
124 * toggle the chip-select lines (nCS pins).
125 */
126 if (cs & 1)
127 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
128 if (cs & 2)
129 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
130
131 return select;
132}
133
Marek Vasut646781d2012-08-03 17:26:11 +0200134static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
135{
Marek Vasutf13639d2012-09-04 04:40:18 +0200136 const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
Marek Vasut646781d2012-08-03 17:26:11 +0200137 struct mxs_ssp *ssp = &spi->ssp;
Trent Piepho42e182f2013-10-01 13:15:54 -0700138 u32 reg;
Marek Vasut646781d2012-08-03 17:26:11 +0200139
Marek Vasutf13639d2012-09-04 04:40:18 +0200140 do {
Marek Vasut646781d2012-08-03 17:26:11 +0200141 reg = readl_relaxed(ssp->base + offset);
142
Marek Vasutf13639d2012-09-04 04:40:18 +0200143 if (!set)
144 reg = ~reg;
Marek Vasut646781d2012-08-03 17:26:11 +0200145
Marek Vasutf13639d2012-09-04 04:40:18 +0200146 reg &= mask;
Marek Vasut646781d2012-08-03 17:26:11 +0200147
Marek Vasutf13639d2012-09-04 04:40:18 +0200148 if (reg == mask)
149 return 0;
150 } while (time_before(jiffies, timeout));
Marek Vasut646781d2012-08-03 17:26:11 +0200151
Marek Vasutf13639d2012-09-04 04:40:18 +0200152 return -ETIMEDOUT;
Marek Vasut646781d2012-08-03 17:26:11 +0200153}
154
Marek Vasut474afc02012-08-03 17:26:13 +0200155static void mxs_ssp_dma_irq_callback(void *param)
156{
157 struct mxs_spi *spi = param;
158 complete(&spi->c);
159}
160
161static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
162{
163 struct mxs_ssp *ssp = dev_id;
164 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
165 __func__, __LINE__,
166 readl(ssp->base + HW_SSP_CTRL1(ssp)),
167 readl(ssp->base + HW_SSP_STATUS(ssp)));
168 return IRQ_HANDLED;
169}
170
Trent Piepho0b782f72013-10-01 13:15:04 -0700171static int mxs_spi_txrx_dma(struct mxs_spi *spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200172 unsigned char *buf, int len,
Trent Piepho28cad122013-10-01 13:14:50 -0700173 unsigned int flags)
Marek Vasut474afc02012-08-03 17:26:13 +0200174{
175 struct mxs_ssp *ssp = &spi->ssp;
Marek Vasut010b4812012-09-04 04:40:15 +0200176 struct dma_async_tx_descriptor *desc = NULL;
177 const bool vmalloced_buf = is_vmalloc_addr(buf);
178 const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
179 const int sgs = DIV_ROUND_UP(len, desc_len);
Marek Vasut474afc02012-08-03 17:26:13 +0200180 int sg_count;
Marek Vasut010b4812012-09-04 04:40:15 +0200181 int min, ret;
Trent Piepho42e182f2013-10-01 13:15:54 -0700182 u32 ctrl0;
Marek Vasut010b4812012-09-04 04:40:15 +0200183 struct page *vm_page;
184 void *sg_buf;
185 struct {
Trent Piepho42e182f2013-10-01 13:15:54 -0700186 u32 pio[4];
Marek Vasut010b4812012-09-04 04:40:15 +0200187 struct scatterlist sg;
188 } *dma_xfer;
Marek Vasut474afc02012-08-03 17:26:13 +0200189
Marek Vasut010b4812012-09-04 04:40:15 +0200190 if (!len)
Marek Vasut474afc02012-08-03 17:26:13 +0200191 return -EINVAL;
Marek Vasut010b4812012-09-04 04:40:15 +0200192
193 dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
194 if (!dma_xfer)
195 return -ENOMEM;
Marek Vasut474afc02012-08-03 17:26:13 +0200196
Wolfram Sang16735d02013-11-14 14:32:02 -0800197 reinit_completion(&spi->c);
Marek Vasut474afc02012-08-03 17:26:13 +0200198
Trent Piepho0b782f72013-10-01 13:15:04 -0700199 /* Chip select was already programmed into CTRL0 */
Marek Vasut010b4812012-09-04 04:40:15 +0200200 ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
Trent Piephodf232862013-10-01 13:14:57 -0700201 ctrl0 &= ~(BM_SSP_CTRL0_XFER_COUNT | BM_SSP_CTRL0_IGNORE_CRC |
202 BM_SSP_CTRL0_READ);
Trent Piepho0b782f72013-10-01 13:15:04 -0700203 ctrl0 |= BM_SSP_CTRL0_DATA_XFER;
Marek Vasut010b4812012-09-04 04:40:15 +0200204
Trent Piepho28cad122013-10-01 13:14:50 -0700205 if (!(flags & TXRX_WRITE))
Marek Vasut010b4812012-09-04 04:40:15 +0200206 ctrl0 |= BM_SSP_CTRL0_READ;
Marek Vasut474afc02012-08-03 17:26:13 +0200207
208 /* Queue the DMA data transfer. */
Marek Vasut010b4812012-09-04 04:40:15 +0200209 for (sg_count = 0; sg_count < sgs; sg_count++) {
Trent Piepho28cad122013-10-01 13:14:50 -0700210 /* Prepare the transfer descriptor. */
Marek Vasut010b4812012-09-04 04:40:15 +0200211 min = min(len, desc_len);
Marek Vasut474afc02012-08-03 17:26:13 +0200212
Trent Piepho28cad122013-10-01 13:14:50 -0700213 /*
214 * De-assert CS on last segment if flag is set (i.e., no more
215 * transfers will follow)
216 */
217 if ((sg_count + 1 == sgs) && (flags & TXRX_DEASSERT_CS))
Marek Vasut010b4812012-09-04 04:40:15 +0200218 ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
Marek Vasut474afc02012-08-03 17:26:13 +0200219
Juha Lummeba486a22012-12-26 14:48:51 +0900220 if (ssp->devid == IMX23_SSP) {
221 ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
Marek Vasut010b4812012-09-04 04:40:15 +0200222 ctrl0 |= min;
Juha Lummeba486a22012-12-26 14:48:51 +0900223 }
Marek Vasut010b4812012-09-04 04:40:15 +0200224
225 dma_xfer[sg_count].pio[0] = ctrl0;
226 dma_xfer[sg_count].pio[3] = min;
227
228 if (vmalloced_buf) {
229 vm_page = vmalloc_to_page(buf);
230 if (!vm_page) {
231 ret = -ENOMEM;
232 goto err_vmalloc;
233 }
234 sg_buf = page_address(vm_page) +
235 ((size_t)buf & ~PAGE_MASK);
236 } else {
237 sg_buf = buf;
238 }
239
240 sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
241 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
Trent Piepho28cad122013-10-01 13:14:50 -0700242 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
Marek Vasut010b4812012-09-04 04:40:15 +0200243
244 len -= min;
245 buf += min;
246
247 /* Queue the PIO register write transfer. */
248 desc = dmaengine_prep_slave_sg(ssp->dmach,
249 (struct scatterlist *)dma_xfer[sg_count].pio,
250 (ssp->devid == IMX23_SSP) ? 1 : 4,
251 DMA_TRANS_NONE,
252 sg_count ? DMA_PREP_INTERRUPT : 0);
253 if (!desc) {
254 dev_err(ssp->dev,
255 "Failed to get PIO reg. write descriptor.\n");
256 ret = -EINVAL;
257 goto err_mapped;
258 }
259
260 desc = dmaengine_prep_slave_sg(ssp->dmach,
261 &dma_xfer[sg_count].sg, 1,
Trent Piepho28cad122013-10-01 13:14:50 -0700262 (flags & TXRX_WRITE) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
Marek Vasut010b4812012-09-04 04:40:15 +0200263 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
264
265 if (!desc) {
266 dev_err(ssp->dev,
267 "Failed to get DMA data write descriptor.\n");
268 ret = -EINVAL;
269 goto err_mapped;
270 }
Marek Vasut474afc02012-08-03 17:26:13 +0200271 }
272
273 /*
274 * The last descriptor must have this callback,
275 * to finish the DMA transaction.
276 */
277 desc->callback = mxs_ssp_dma_irq_callback;
278 desc->callback_param = spi;
279
280 /* Start the transfer. */
281 dmaengine_submit(desc);
282 dma_async_issue_pending(ssp->dmach);
283
284 ret = wait_for_completion_timeout(&spi->c,
285 msecs_to_jiffies(SSP_TIMEOUT));
Marek Vasut474afc02012-08-03 17:26:13 +0200286 if (!ret) {
287 dev_err(ssp->dev, "DMA transfer timeout\n");
288 ret = -ETIMEDOUT;
Marek Vasut44968462012-10-14 04:32:56 +0200289 dmaengine_terminate_all(ssp->dmach);
Marek Vasut010b4812012-09-04 04:40:15 +0200290 goto err_vmalloc;
Marek Vasut474afc02012-08-03 17:26:13 +0200291 }
292
293 ret = 0;
294
Marek Vasut010b4812012-09-04 04:40:15 +0200295err_vmalloc:
296 while (--sg_count >= 0) {
297err_mapped:
298 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
Trent Piepho28cad122013-10-01 13:14:50 -0700299 (flags & TXRX_WRITE) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
Marek Vasut474afc02012-08-03 17:26:13 +0200300 }
301
Marek Vasut010b4812012-09-04 04:40:15 +0200302 kfree(dma_xfer);
303
Marek Vasut474afc02012-08-03 17:26:13 +0200304 return ret;
305}
306
Trent Piepho0b782f72013-10-01 13:15:04 -0700307static int mxs_spi_txrx_pio(struct mxs_spi *spi,
Marek Vasut646781d2012-08-03 17:26:11 +0200308 unsigned char *buf, int len,
Trent Piepho28cad122013-10-01 13:14:50 -0700309 unsigned int flags)
Marek Vasut646781d2012-08-03 17:26:11 +0200310{
311 struct mxs_ssp *ssp = &spi->ssp;
312
Trent Piepho75e73fa2013-10-01 13:14:39 -0700313 writel(BM_SSP_CTRL0_IGNORE_CRC,
314 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
Marek Vasut646781d2012-08-03 17:26:11 +0200315
316 while (len--) {
Trent Piepho28cad122013-10-01 13:14:50 -0700317 if (len == 0 && (flags & TXRX_DEASSERT_CS))
Trent Piephof5bc7382013-10-01 13:14:32 -0700318 writel(BM_SSP_CTRL0_IGNORE_CRC,
319 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
Marek Vasut646781d2012-08-03 17:26:11 +0200320
321 if (ssp->devid == IMX23_SSP) {
322 writel(BM_SSP_CTRL0_XFER_COUNT,
323 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
324 writel(1,
325 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
326 } else {
327 writel(1, ssp->base + HW_SSP_XFER_SIZE);
328 }
329
Trent Piepho28cad122013-10-01 13:14:50 -0700330 if (flags & TXRX_WRITE)
Marek Vasut646781d2012-08-03 17:26:11 +0200331 writel(BM_SSP_CTRL0_READ,
332 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
333 else
334 writel(BM_SSP_CTRL0_READ,
335 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
336
337 writel(BM_SSP_CTRL0_RUN,
338 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
339
340 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
341 return -ETIMEDOUT;
342
Trent Piepho28cad122013-10-01 13:14:50 -0700343 if (flags & TXRX_WRITE)
Marek Vasut646781d2012-08-03 17:26:11 +0200344 writel(*buf, ssp->base + HW_SSP_DATA(ssp));
345
346 writel(BM_SSP_CTRL0_DATA_XFER,
347 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
348
Trent Piepho28cad122013-10-01 13:14:50 -0700349 if (!(flags & TXRX_WRITE)) {
Marek Vasut646781d2012-08-03 17:26:11 +0200350 if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
351 BM_SSP_STATUS_FIFO_EMPTY, 0))
352 return -ETIMEDOUT;
353
354 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
355 }
356
357 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
358 return -ETIMEDOUT;
359
360 buf++;
361 }
362
363 if (len <= 0)
364 return 0;
365
366 return -ETIMEDOUT;
367}
368
369static int mxs_spi_transfer_one(struct spi_master *master,
370 struct spi_message *m)
371{
372 struct mxs_spi *spi = spi_master_get_devdata(master);
373 struct mxs_ssp *ssp = &spi->ssp;
Marek Vasut646781d2012-08-03 17:26:11 +0200374 struct spi_transfer *t, *tmp_t;
Trent Piepho28cad122013-10-01 13:14:50 -0700375 unsigned int flag;
Marek Vasut646781d2012-08-03 17:26:11 +0200376 int status = 0;
Marek Vasut646781d2012-08-03 17:26:11 +0200377
Trent Piepho0b782f72013-10-01 13:15:04 -0700378 /* Program CS register bits here, it will be used for all transfers. */
379 writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ,
380 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
381 writel(mxs_spi_cs_to_reg(m->spi->chip_select),
382 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
Marek Vasut646781d2012-08-03 17:26:11 +0200383
384 list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
385
386 status = mxs_spi_setup_transfer(m->spi, t);
387 if (status)
388 break;
389
Trent Piepho28cad122013-10-01 13:14:50 -0700390 /* De-assert on last transfer, inverted by cs_change flag */
391 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ?
392 TXRX_DEASSERT_CS : 0;
Marek Vasut646781d2012-08-03 17:26:11 +0200393
Marek Vasut474afc02012-08-03 17:26:13 +0200394 /*
395 * Small blocks can be transfered via PIO.
396 * Measured by empiric means:
397 *
398 * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
399 *
400 * DMA only: 2.164808 seconds, 473.0KB/s
401 * Combined: 1.676276 seconds, 610.9KB/s
402 */
Marek Vasut727c10e2012-09-04 04:40:17 +0200403 if (t->len < 32) {
Marek Vasut474afc02012-08-03 17:26:13 +0200404 writel(BM_SSP_CTRL1_DMA_ENABLE,
405 ssp->base + HW_SSP_CTRL1(ssp) +
406 STMP_OFFSET_REG_CLR);
407
408 if (t->tx_buf)
Trent Piepho0b782f72013-10-01 13:15:04 -0700409 status = mxs_spi_txrx_pio(spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200410 (void *)t->tx_buf,
Trent Piepho28cad122013-10-01 13:14:50 -0700411 t->len, flag | TXRX_WRITE);
Marek Vasut474afc02012-08-03 17:26:13 +0200412 if (t->rx_buf)
Trent Piepho0b782f72013-10-01 13:15:04 -0700413 status = mxs_spi_txrx_pio(spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200414 t->rx_buf, t->len,
Trent Piepho28cad122013-10-01 13:14:50 -0700415 flag);
Marek Vasut474afc02012-08-03 17:26:13 +0200416 } else {
417 writel(BM_SSP_CTRL1_DMA_ENABLE,
418 ssp->base + HW_SSP_CTRL1(ssp) +
419 STMP_OFFSET_REG_SET);
420
421 if (t->tx_buf)
Trent Piepho0b782f72013-10-01 13:15:04 -0700422 status = mxs_spi_txrx_dma(spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200423 (void *)t->tx_buf, t->len,
Trent Piepho28cad122013-10-01 13:14:50 -0700424 flag | TXRX_WRITE);
Marek Vasut474afc02012-08-03 17:26:13 +0200425 if (t->rx_buf)
Trent Piepho0b782f72013-10-01 13:15:04 -0700426 status = mxs_spi_txrx_dma(spi,
Marek Vasut474afc02012-08-03 17:26:13 +0200427 t->rx_buf, t->len,
Trent Piepho28cad122013-10-01 13:14:50 -0700428 flag);
Marek Vasut474afc02012-08-03 17:26:13 +0200429 }
Marek Vasut646781d2012-08-03 17:26:11 +0200430
Marek Vasutc895db02012-08-24 04:34:18 +0200431 if (status) {
432 stmp_reset_block(ssp->base);
Marek Vasut646781d2012-08-03 17:26:11 +0200433 break;
Marek Vasutc895db02012-08-24 04:34:18 +0200434 }
Marek Vasut646781d2012-08-03 17:26:11 +0200435
Marek Vasut204e7062012-09-04 04:40:16 +0200436 m->actual_length += t->len;
Marek Vasut646781d2012-08-03 17:26:11 +0200437 }
438
Marek Vasutd856f1eb2012-10-14 04:32:55 +0200439 m->status = status;
Marek Vasut646781d2012-08-03 17:26:11 +0200440 spi_finalize_current_message(master);
441
442 return status;
443}
444
445static const struct of_device_id mxs_spi_dt_ids[] = {
446 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
447 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
448 { /* sentinel */ }
449};
450MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
451
Grant Likelyfd4a3192012-12-07 16:57:14 +0000452static int mxs_spi_probe(struct platform_device *pdev)
Marek Vasut646781d2012-08-03 17:26:11 +0200453{
454 const struct of_device_id *of_id =
455 of_match_device(mxs_spi_dt_ids, &pdev->dev);
456 struct device_node *np = pdev->dev.of_node;
457 struct spi_master *master;
458 struct mxs_spi *spi;
459 struct mxs_ssp *ssp;
Shawn Guo26aafa72013-02-26 11:07:32 +0800460 struct resource *iores;
Marek Vasut646781d2012-08-03 17:26:11 +0200461 struct clk *clk;
462 void __iomem *base;
Shawn Guo26aafa72013-02-26 11:07:32 +0800463 int devid, clk_freq;
464 int ret = 0, irq_err;
Marek Vasut646781d2012-08-03 17:26:11 +0200465
Marek Vasute64d07a2012-08-22 22:38:35 +0200466 /*
467 * Default clock speed for the SPI core. 160MHz seems to
468 * work reasonably well with most SPI flashes, so use this
469 * as a default. Override with "clock-frequency" DT prop.
470 */
471 const int clk_freq_default = 160000000;
472
Marek Vasut646781d2012-08-03 17:26:11 +0200473 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Marek Vasut474afc02012-08-03 17:26:13 +0200474 irq_err = platform_get_irq(pdev, 0);
Fabio Estevam796305a2013-07-21 22:29:54 -0300475 if (irq_err < 0)
Marek Vasut646781d2012-08-03 17:26:11 +0200476 return -EINVAL;
477
Thierry Redingb0ee5602013-01-21 11:09:18 +0100478 base = devm_ioremap_resource(&pdev->dev, iores);
479 if (IS_ERR(base))
480 return PTR_ERR(base);
Marek Vasut646781d2012-08-03 17:26:11 +0200481
Marek Vasut646781d2012-08-03 17:26:11 +0200482 clk = devm_clk_get(&pdev->dev, NULL);
483 if (IS_ERR(clk))
484 return PTR_ERR(clk);
485
Shawn Guo26aafa72013-02-26 11:07:32 +0800486 devid = (enum mxs_ssp_id) of_id->data;
487 ret = of_property_read_u32(np, "clock-frequency",
488 &clk_freq);
489 if (ret)
Marek Vasute64d07a2012-08-22 22:38:35 +0200490 clk_freq = clk_freq_default;
Marek Vasut646781d2012-08-03 17:26:11 +0200491
492 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
493 if (!master)
494 return -ENOMEM;
495
496 master->transfer_one_message = mxs_spi_transfer_one;
Stephen Warren24778be2013-05-21 20:36:35 -0600497 master->bits_per_word_mask = SPI_BPW_MASK(8);
Marek Vasut646781d2012-08-03 17:26:11 +0200498 master->mode_bits = SPI_CPOL | SPI_CPHA;
499 master->num_chipselect = 3;
500 master->dev.of_node = np;
501 master->flags = SPI_MASTER_HALF_DUPLEX;
502
503 spi = spi_master_get_devdata(master);
504 ssp = &spi->ssp;
505 ssp->dev = &pdev->dev;
506 ssp->clk = clk;
507 ssp->base = base;
508 ssp->devid = devid;
509
Marek Vasut41682e02012-08-24 04:56:27 +0200510 init_completion(&spi->c);
511
Marek Vasut474afc02012-08-03 17:26:13 +0200512 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
513 DRIVER_NAME, ssp);
514 if (ret)
515 goto out_master_free;
516
Shawn Guo26aafa72013-02-26 11:07:32 +0800517 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
Marek Vasut474afc02012-08-03 17:26:13 +0200518 if (!ssp->dmach) {
519 dev_err(ssp->dev, "Failed to request DMA\n");
Wei Yongjun58ad60b2013-04-03 21:06:40 +0800520 ret = -ENODEV;
Marek Vasut474afc02012-08-03 17:26:13 +0200521 goto out_master_free;
522 }
523
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300524 ret = clk_prepare_enable(ssp->clk);
525 if (ret)
526 goto out_dma_release;
527
Marek Vasute64d07a2012-08-22 22:38:35 +0200528 clk_set_rate(ssp->clk, clk_freq);
Marek Vasut646781d2012-08-03 17:26:11 +0200529
Fabio Estevam8498bce2013-07-10 00:16:29 -0300530 ret = stmp_reset_block(ssp->base);
531 if (ret)
532 goto out_disable_clk;
Marek Vasut646781d2012-08-03 17:26:11 +0200533
534 platform_set_drvdata(pdev, master);
535
Jingoo Han33e195a2013-09-24 13:32:56 +0900536 ret = devm_spi_register_master(&pdev->dev, master);
Marek Vasut646781d2012-08-03 17:26:11 +0200537 if (ret) {
538 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300539 goto out_disable_clk;
Marek Vasut646781d2012-08-03 17:26:11 +0200540 }
541
542 return 0;
543
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300544out_disable_clk:
Marek Vasut646781d2012-08-03 17:26:11 +0200545 clk_disable_unprepare(ssp->clk);
Fabio Estevam9c4a39a2013-07-10 00:16:28 -0300546out_dma_release:
Fabio Estevame11933f2013-07-10 00:16:27 -0300547 dma_release_channel(ssp->dmach);
Marek Vasut474afc02012-08-03 17:26:13 +0200548out_master_free:
Marek Vasut646781d2012-08-03 17:26:11 +0200549 spi_master_put(master);
550 return ret;
551}
552
Grant Likelyfd4a3192012-12-07 16:57:14 +0000553static int mxs_spi_remove(struct platform_device *pdev)
Marek Vasut646781d2012-08-03 17:26:11 +0200554{
555 struct spi_master *master;
556 struct mxs_spi *spi;
557 struct mxs_ssp *ssp;
558
Wei Yongjune322ce92013-11-15 15:50:31 +0800559 master = platform_get_drvdata(pdev);
Marek Vasut646781d2012-08-03 17:26:11 +0200560 spi = spi_master_get_devdata(master);
561 ssp = &spi->ssp;
562
Marek Vasut646781d2012-08-03 17:26:11 +0200563 clk_disable_unprepare(ssp->clk);
Fabio Estevame11933f2013-07-10 00:16:27 -0300564 dma_release_channel(ssp->dmach);
Marek Vasut646781d2012-08-03 17:26:11 +0200565
566 return 0;
567}
568
569static struct platform_driver mxs_spi_driver = {
570 .probe = mxs_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000571 .remove = mxs_spi_remove,
Marek Vasut646781d2012-08-03 17:26:11 +0200572 .driver = {
573 .name = DRIVER_NAME,
574 .owner = THIS_MODULE,
575 .of_match_table = mxs_spi_dt_ids,
576 },
577};
578
579module_platform_driver(mxs_spi_driver);
580
581MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
582MODULE_DESCRIPTION("MXS SPI master driver");
583MODULE_LICENSE("GPL");
584MODULE_ALIAS("platform:mxs-spi");