blob: 94924d52a9b96d10121ac34f26d3447702eb0ae7 [file] [log] [blame]
David Woodhouse179fdc32006-05-11 22:35:28 +01001/*
2 * drivers/mtd/nand/cs553x_nand.c
3 *
4 * (C) 2005, 2006 Red Hat Inc.
5 *
6 * Author: David Woodhouse <dwmw2@infradead.org>
David Woodhouse9d754142006-05-13 04:12:40 +01007 * Tom Sylla <tom.sylla@amd.com>
David Woodhouse179fdc32006-05-11 22:35:28 +01008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Overview:
14 * This is a device driver for the NAND flash controller found on
15 * the AMD CS5535/CS5536 companion chipsets for the Geode processor.
16 *
17 */
18
19#include <linux/slab.h>
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/delay.h>
23#include <linux/pci.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h>
David Woodhouse9d754142006-05-13 04:12:40 +010026#include <linux/mtd/nand_ecc.h>
David Woodhouse179fdc32006-05-11 22:35:28 +010027#include <linux/mtd/partitions.h>
28
29#include <asm/msr.h>
30#include <asm/io.h>
31
32#define NR_CS553X_CONTROLLERS 4
33
David Woodhousee4d222f2006-05-26 02:06:27 +010034#define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
35#define CAP_CS5535 0x2df000ULL
36#define CAP_CS5536 0x5df500ULL
37
David Woodhouse179fdc32006-05-11 22:35:28 +010038/* NAND Timing MSRs */
39#define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
40#define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
41#define MSR_NANDF_RSVD 0x5140001d /* Reserved */
42
43/* NAND BAR MSRs */
44#define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
45#define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
46#define MSR_DIVIL_LBAR_FLSH2 0x51400012 /* Flash Chip Select 2 */
47#define MSR_DIVIL_LBAR_FLSH3 0x51400013 /* Flash Chip Select 3 */
48 /* Each made up of... */
49#define FLSH_LBAR_EN (1ULL<<32)
50#define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */
51#define FLSH_MEM_IO (1ULL<<34) /* 1 for MMIO */
52 /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
53 /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
54
55/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
56#define MSR_DIVIL_BALL_OPTS 0x51400015
David Woodhousee0c7d762006-05-13 18:07:53 +010057#define PIN_OPT_IDE (1<<0) /* 0 for flash, 1 for IDE */
David Woodhouse179fdc32006-05-11 22:35:28 +010058
59/* Registers within the NAND flash controller BAR -- memory mapped */
60#define MM_NAND_DATA 0x00 /* 0 to 0x7ff, in fact */
61#define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */
62#define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */
63#define MM_NAND_STS 0x810
64#define MM_NAND_ECC_LSB 0x811
65#define MM_NAND_ECC_MSB 0x812
66#define MM_NAND_ECC_COL 0x813
67#define MM_NAND_LAC 0x814
68#define MM_NAND_ECC_CTL 0x815
69
70/* Registers within the NAND flash controller BAR -- I/O mapped */
71#define IO_NAND_DATA 0x00 /* 0 to 3, in fact */
72#define IO_NAND_CTL 0x04
73#define IO_NAND_IO 0x05
74#define IO_NAND_STS 0x06
75#define IO_NAND_ECC_CTL 0x08
76#define IO_NAND_ECC_LSB 0x09
77#define IO_NAND_ECC_MSB 0x0a
78#define IO_NAND_ECC_COL 0x0b
79#define IO_NAND_LAC 0x0c
80
81#define CS_NAND_CTL_DIST_EN (1<<4) /* Enable NAND Distract interrupt */
82#define CS_NAND_CTL_RDY_INT_MASK (1<<3) /* Enable RDY/BUSY# interrupt */
83#define CS_NAND_CTL_ALE (1<<2)
84#define CS_NAND_CTL_CLE (1<<1)
85#define CS_NAND_CTL_CE (1<<0) /* Keep low; 1 to reset */
86
87#define CS_NAND_STS_FLASH_RDY (1<<3)
88#define CS_NAND_CTLR_BUSY (1<<2)
89#define CS_NAND_CMD_COMP (1<<1)
90#define CS_NAND_DIST_ST (1<<0)
91
92#define CS_NAND_ECC_PARITY (1<<2)
93#define CS_NAND_ECC_CLRECC (1<<1)
94#define CS_NAND_ECC_ENECC (1<<0)
95
David Woodhouse9d754142006-05-13 04:12:40 +010096static void cs553x_read_buf(struct mtd_info *mtd, u_char *buf, int len)
97{
98 struct nand_chip *this = mtd->priv;
99
100 while (unlikely(len > 0x800)) {
101 memcpy_fromio(buf, this->IO_ADDR_R, 0x800);
102 buf += 0x800;
103 len -= 0x800;
104 }
105 memcpy_fromio(buf, this->IO_ADDR_R, len);
106}
107
108static void cs553x_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
109{
110 struct nand_chip *this = mtd->priv;
111
112 while (unlikely(len > 0x800)) {
113 memcpy_toio(this->IO_ADDR_R, buf, 0x800);
114 buf += 0x800;
115 len -= 0x800;
116 }
117 memcpy_toio(this->IO_ADDR_R, buf, len);
118}
119
David Woodhouse179fdc32006-05-11 22:35:28 +0100120static unsigned char cs553x_read_byte(struct mtd_info *mtd)
121{
122 struct nand_chip *this = mtd->priv;
David Woodhouse9d754142006-05-13 04:12:40 +0100123 return readb(this->IO_ADDR_R);
David Woodhouse179fdc32006-05-11 22:35:28 +0100124}
125
126static void cs553x_write_byte(struct mtd_info *mtd, u_char byte)
127{
128 struct nand_chip *this = mtd->priv;
129 int i = 100000;
130
131 while (i && readb(this->IO_ADDR_R + MM_NAND_STS) & CS_NAND_CTLR_BUSY) {
132 udelay(1);
133 i--;
134 }
David Woodhousee0c7d762006-05-13 18:07:53 +0100135 writeb(byte, this->IO_ADDR_W + 0x801);
David Woodhouse179fdc32006-05-11 22:35:28 +0100136}
137
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200138static void cs553x_hwcontrol(struct mtd_info *mtd, int cmd,
139 unsigned int ctrl)
David Woodhouse179fdc32006-05-11 22:35:28 +0100140{
141 struct nand_chip *this = mtd->priv;
142 void __iomem *mmio_base = this->IO_ADDR_R;
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200143 if (ctrl & NAND_CTRL_CHANGE) {
144 unsigned char ctl = (ctrl & ~NAND_CTRL_CHANGE ) ^ 0x01;
145 writeb(ctl, mmio_base + MM_NAND_CTL);
David Woodhouse179fdc32006-05-11 22:35:28 +0100146 }
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200147 if (cmd != NAND_CMD_NONE)
148 cs553x_write_byte(mtd, cmd);
David Woodhouse179fdc32006-05-11 22:35:28 +0100149}
150
David Woodhouse179fdc32006-05-11 22:35:28 +0100151static int cs553x_device_ready(struct mtd_info *mtd)
152{
153 struct nand_chip *this = mtd->priv;
154 void __iomem *mmio_base = this->IO_ADDR_R;
155 unsigned char foo = readb(mmio_base + MM_NAND_STS);
156
David Woodhousee0c7d762006-05-13 18:07:53 +0100157 return (foo & CS_NAND_STS_FLASH_RDY) && !(foo & CS_NAND_CTLR_BUSY);
David Woodhouse179fdc32006-05-11 22:35:28 +0100158}
159
David Woodhouse9d754142006-05-13 04:12:40 +0100160static void cs_enable_hwecc(struct mtd_info *mtd, int mode)
161{
162 struct nand_chip *this = mtd->priv;
163 void __iomem *mmio_base = this->IO_ADDR_R;
164
165 writeb(0x07, mmio_base + MM_NAND_ECC_CTL);
166}
167
168static int cs_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
169{
170 uint32_t ecc;
171 struct nand_chip *this = mtd->priv;
172 void __iomem *mmio_base = this->IO_ADDR_R;
173
174 ecc = readl(mmio_base + MM_NAND_STS);
175
176 ecc_code[1] = ecc >> 8;
177 ecc_code[0] = ecc >> 16;
178 ecc_code[2] = ecc >> 24;
179 return 0;
180}
181
David Woodhouse179fdc32006-05-11 22:35:28 +0100182static struct mtd_info *cs553x_mtd[4];
183
184static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
185{
186 int err = 0;
187 struct nand_chip *this;
188 struct mtd_info *new_mtd;
189
190 printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr);
191
192 if (!mmio) {
193 printk(KERN_NOTICE "PIO mode not yet implemented for CS553X NAND controller\n");
194 return -ENXIO;
195 }
196
197 /* Allocate memory for MTD device structure and private data */
David Woodhousee0c7d762006-05-13 18:07:53 +0100198 new_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
David Woodhouse179fdc32006-05-11 22:35:28 +0100199 if (!new_mtd) {
200 printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n");
201 err = -ENOMEM;
202 goto out;
203 }
204
205 /* Get pointer to private data */
David Woodhousee0c7d762006-05-13 18:07:53 +0100206 this = (struct nand_chip *)(&new_mtd[1]);
David Woodhouse179fdc32006-05-11 22:35:28 +0100207
208 /* Initialize structures */
David Woodhouse9d754142006-05-13 04:12:40 +0100209 memset(new_mtd, 0, sizeof(struct mtd_info));
210 memset(this, 0, sizeof(struct nand_chip));
David Woodhouse179fdc32006-05-11 22:35:28 +0100211
212 /* Link the private data with the MTD structure */
213 new_mtd->priv = this;
David Woodhouse552d9202006-05-14 01:20:46 +0100214 new_mtd->owner = THIS_MODULE;
David Woodhouse179fdc32006-05-11 22:35:28 +0100215
216 /* map physical address */
217 this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
218 if (!this->IO_ADDR_R) {
219 printk(KERN_WARNING "ioremap cs553x NAND @0x%08lx failed\n", adr);
220 err = -EIO;
221 goto out_mtd;
222 }
223
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200224 this->cmd_ctrl = cs553x_hwcontrol;
David Woodhouse179fdc32006-05-11 22:35:28 +0100225 this->dev_ready = cs553x_device_ready;
226 this->read_byte = cs553x_read_byte;
David Woodhouse9d754142006-05-13 04:12:40 +0100227 this->read_buf = cs553x_read_buf;
228 this->write_buf = cs553x_write_buf;
David Woodhouse179fdc32006-05-11 22:35:28 +0100229
David Woodhouse9d754142006-05-13 04:12:40 +0100230 this->chip_delay = 0;
David Woodhouse179fdc32006-05-11 22:35:28 +0100231
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200232 this->ecc.mode = NAND_ECC_HW;
233 this->ecc.size = 256;
234 this->ecc.bytes = 3;
235 this->ecc.hwctl = cs_enable_hwecc;
236 this->ecc.calculate = cs_calculate_ecc;
237 this->ecc.correct = nand_correct_data;
238
David Woodhouse179fdc32006-05-11 22:35:28 +0100239 /* Enable the following for a flash based bad block table */
David Woodhouse9d754142006-05-13 04:12:40 +0100240 this->options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR;
David Woodhouse179fdc32006-05-11 22:35:28 +0100241
242 /* Scan to find existance of the device */
David Woodhouse9d754142006-05-13 04:12:40 +0100243 if (nand_scan(new_mtd, 1)) {
David Woodhouse179fdc32006-05-11 22:35:28 +0100244 err = -ENXIO;
245 goto out_ior;
246 }
247
248 cs553x_mtd[cs] = new_mtd;
249 goto out;
250
251out_ior:
Al Viroafc12d32006-10-10 22:46:37 +0100252 iounmap(this->IO_ADDR_R);
David Woodhouse179fdc32006-05-11 22:35:28 +0100253out_mtd:
David Woodhouse9d754142006-05-13 04:12:40 +0100254 kfree(new_mtd);
David Woodhouse179fdc32006-05-11 22:35:28 +0100255out:
256 return err;
257}
258
David Woodhousee4d222f2006-05-26 02:06:27 +0100259static int is_geode(void)
260{
261 /* These are the CPUs which will have a CS553[56] companion chip */
262 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
263 boot_cpu_data.x86 == 5 &&
264 boot_cpu_data.x86_model == 10)
265 return 1; /* Geode LX */
266
267 if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC ||
268 boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) &&
269 boot_cpu_data.x86 == 5 &&
270 boot_cpu_data.x86_model == 5)
271 return 1; /* Geode GX (née GX2) */
272
273 return 0;
274}
275
David Woodhousecead4db2006-05-16 13:54:50 +0100276static int __init cs553x_init(void)
David Woodhouse179fdc32006-05-11 22:35:28 +0100277{
278 int err = -ENXIO;
279 int i;
280 uint64_t val;
281
David Woodhousee4d222f2006-05-26 02:06:27 +0100282 /* If the CPU isn't a Geode GX or LX, abort */
283 if (!is_geode())
David Woodhouse179fdc32006-05-11 22:35:28 +0100284 return -ENXIO;
285
David Woodhousee4d222f2006-05-26 02:06:27 +0100286 /* If it doesn't have the CS553[56], abort */
287 rdmsrl(MSR_DIVIL_GLD_CAP, val);
288 val &= ~0xFFULL;
289 if (val != CAP_CS5535 && val != CAP_CS5536)
290 return -ENXIO;
291
292 /* If it doesn't have the NAND controller enabled, abort */
David Woodhouse179fdc32006-05-11 22:35:28 +0100293 rdmsrl(MSR_DIVIL_BALL_OPTS, val);
294 if (val & 1) {
295 printk(KERN_INFO "CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
296 return -ENXIO;
297 }
298
David Woodhousee0c7d762006-05-13 18:07:53 +0100299 for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
300 rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
David Woodhouse179fdc32006-05-11 22:35:28 +0100301
302 if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
303 err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
304 }
David Woodhousee0c7d762006-05-13 18:07:53 +0100305
David Woodhouse179fdc32006-05-11 22:35:28 +0100306 /* Register all devices together here. This means we can easily hack it to
307 do mtdconcat etc. if we want to. */
David Woodhousee0c7d762006-05-13 18:07:53 +0100308 for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
David Woodhouse179fdc32006-05-11 22:35:28 +0100309 if (cs553x_mtd[i]) {
310 add_mtd_device(cs553x_mtd[i]);
311
312 /* If any devices registered, return success. Else the last error. */
313 err = 0;
314 }
315 }
316
317 return err;
318}
David Woodhousee0c7d762006-05-13 18:07:53 +0100319
David Woodhouse179fdc32006-05-11 22:35:28 +0100320module_init(cs553x_init);
321
David Woodhousee0c7d762006-05-13 18:07:53 +0100322static void __exit cs553x_cleanup(void)
David Woodhouse179fdc32006-05-11 22:35:28 +0100323{
324 int i;
325
David Woodhousee0c7d762006-05-13 18:07:53 +0100326 for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
David Woodhouse179fdc32006-05-11 22:35:28 +0100327 struct mtd_info *mtd = cs553x_mtd[i];
328 struct nand_chip *this;
329 void __iomem *mmio_base;
330
331 if (!mtd)
332 break;
333
334 this = cs553x_mtd[i]->priv;
335 mmio_base = this->IO_ADDR_R;
336
337 /* Release resources, unregister device */
David Woodhousee0c7d762006-05-13 18:07:53 +0100338 nand_release(cs553x_mtd[i]);
David Woodhouse179fdc32006-05-11 22:35:28 +0100339 cs553x_mtd[i] = NULL;
340
341 /* unmap physical adress */
342 iounmap(mmio_base);
343
344 /* Free the MTD device structure */
David Woodhouse9d754142006-05-13 04:12:40 +0100345 kfree(mtd);
David Woodhouse179fdc32006-05-11 22:35:28 +0100346 }
347}
David Woodhousee0c7d762006-05-13 18:07:53 +0100348
David Woodhouse179fdc32006-05-11 22:35:28 +0100349module_exit(cs553x_cleanup);
350
351MODULE_LICENSE("GPL");
352MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
353MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");