Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP2xxx DVFS virtual clock functions |
| 3 | * |
Paul Walmsley | baa689b | 2012-10-29 20:56:00 -0600 | [diff] [blame] | 4 | * Copyright (C) 2005-2008, 2012 Texas Instruments, Inc. |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
| 6 | * |
| 7 | * Contacts: |
| 8 | * Richard Woodruff <r-woodruff2@ti.com> |
| 9 | * Paul Walmsley |
| 10 | * |
| 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, |
| 12 | * Gordon McNutt and RidgeRun, Inc. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | * |
| 18 | * XXX Some of this code should be replaceable by the upcoming OPP layer |
| 19 | * code. However, some notion of "rate set" is probably still necessary |
| 20 | * for OMAP2xxx at least. Rate sets should be generalized so they can be |
| 21 | * used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff |
| 22 | * has in the past expressed a preference to use rate sets for OPP changes, |
| 23 | * rather than dynamically recalculating the clock tree, so if someone wants |
| 24 | * this badly enough to write the code to handle it, we should support it |
| 25 | * as an option. |
| 26 | */ |
| 27 | #undef DEBUG |
| 28 | |
| 29 | #include <linux/kernel.h> |
| 30 | #include <linux/errno.h> |
| 31 | #include <linux/clk.h> |
| 32 | #include <linux/io.h> |
| 33 | #include <linux/cpufreq.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 35 | |
Tony Lindgren | 622297f | 2012-10-02 14:19:52 -0700 | [diff] [blame] | 36 | #include "../plat-omap/sram.h" |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 37 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 38 | #include "soc.h" |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 39 | #include "clock.h" |
| 40 | #include "clock2xxx.h" |
| 41 | #include "opp2xxx.h" |
Paul Walmsley | d9a16f9 | 2012-10-29 20:57:39 -0600 | [diff] [blame^] | 42 | #include "cm2xxx.h" |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 43 | #include "cm-regbits-24xx.h" |
Paul Walmsley | 3e6ece1 | 2012-10-17 00:46:45 +0000 | [diff] [blame] | 44 | #include "sdrc.h" |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 45 | |
| 46 | const struct prcm_config *curr_prcm_set; |
| 47 | const struct prcm_config *rate_table; |
| 48 | |
Paul Walmsley | baa689b | 2012-10-29 20:56:00 -0600 | [diff] [blame] | 49 | /* |
| 50 | * sys_ck_rate: the rate of the external high-frequency clock |
| 51 | * oscillator on the board. Set by the SoC-specific clock init code. |
| 52 | * Once set during a boot, will not change. |
| 53 | */ |
| 54 | static unsigned long sys_ck_rate; |
| 55 | |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 56 | /** |
| 57 | * omap2_table_mpu_recalc - just return the MPU speed |
| 58 | * @clk: virt_prcm_set struct clk |
| 59 | * |
| 60 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. |
| 61 | */ |
| 62 | unsigned long omap2_table_mpu_recalc(struct clk *clk) |
| 63 | { |
| 64 | return curr_prcm_set->mpu_speed; |
| 65 | } |
| 66 | |
| 67 | /* |
| 68 | * Look for a rate equal or less than the target rate given a configuration set. |
| 69 | * |
| 70 | * What's not entirely clear is "which" field represents the key field. |
| 71 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and |
| 72 | * just uses the ARM rates. |
| 73 | */ |
| 74 | long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) |
| 75 | { |
| 76 | const struct prcm_config *ptr; |
Paul Walmsley | baa689b | 2012-10-29 20:56:00 -0600 | [diff] [blame] | 77 | long highest_rate; |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 78 | |
| 79 | highest_rate = -EINVAL; |
| 80 | |
| 81 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { |
| 82 | if (!(ptr->flags & cpu_mask)) |
| 83 | continue; |
Paul Walmsley | baa689b | 2012-10-29 20:56:00 -0600 | [diff] [blame] | 84 | if (ptr->xtal_speed != sys_ck_rate) |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 85 | continue; |
| 86 | |
| 87 | highest_rate = ptr->mpu_speed; |
| 88 | |
| 89 | /* Can check only after xtal frequency check */ |
| 90 | if (ptr->mpu_speed <= rate) |
| 91 | break; |
| 92 | } |
| 93 | return highest_rate; |
| 94 | } |
| 95 | |
| 96 | /* Sets basic clocks based on the specified rate */ |
| 97 | int omap2_select_table_rate(struct clk *clk, unsigned long rate) |
| 98 | { |
| 99 | u32 cur_rate, done_rate, bypass = 0, tmp; |
| 100 | const struct prcm_config *prcm; |
| 101 | unsigned long found_speed = 0; |
| 102 | unsigned long flags; |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 103 | |
| 104 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
| 105 | if (!(prcm->flags & cpu_mask)) |
| 106 | continue; |
| 107 | |
Paul Walmsley | baa689b | 2012-10-29 20:56:00 -0600 | [diff] [blame] | 108 | if (prcm->xtal_speed != sys_ck_rate) |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 109 | continue; |
| 110 | |
| 111 | if (prcm->mpu_speed <= rate) { |
| 112 | found_speed = prcm->mpu_speed; |
| 113 | break; |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | if (!found_speed) { |
| 118 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", |
| 119 | rate / 1000000); |
| 120 | return -EINVAL; |
| 121 | } |
| 122 | |
| 123 | curr_prcm_set = prcm; |
Paul Walmsley | 5f03937 | 2012-10-29 20:55:53 -0600 | [diff] [blame] | 124 | cur_rate = omap2xxx_clk_get_core_rate(); |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 125 | |
| 126 | if (prcm->dpll_speed == cur_rate / 2) { |
| 127 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
| 128 | } else if (prcm->dpll_speed == cur_rate * 2) { |
| 129 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
| 130 | } else if (prcm->dpll_speed != cur_rate) { |
| 131 | local_irq_save(flags); |
| 132 | |
| 133 | if (prcm->dpll_speed == prcm->xtal_speed) |
| 134 | bypass = 1; |
| 135 | |
| 136 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == |
| 137 | CORE_CLK_SRC_DPLL_X2) |
| 138 | done_rate = CORE_CLK_SRC_DPLL_X2; |
| 139 | else |
| 140 | done_rate = CORE_CLK_SRC_DPLL; |
| 141 | |
| 142 | /* MPU divider */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 143 | omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 144 | |
| 145 | /* dsp + iva1 div(2420), iva2.1(2430) */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 146 | omap2_cm_write_mod_reg(prcm->cm_clksel_dsp, |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 147 | OMAP24XX_DSP_MOD, CM_CLKSEL); |
| 148 | |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 149 | omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 150 | |
| 151 | /* Major subsystem dividers */ |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 152 | tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; |
| 153 | omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 154 | CM_CLKSEL1); |
| 155 | |
| 156 | if (cpu_is_omap2430()) |
Paul Walmsley | c4d7e58 | 2010-12-21 21:05:14 -0700 | [diff] [blame] | 157 | omap2_cm_write_mod_reg(prcm->cm_clksel_mdm, |
Paul Walmsley | 734f69a | 2010-01-26 20:13:06 -0700 | [diff] [blame] | 158 | OMAP2430_MDM_MOD, CM_CLKSEL); |
| 159 | |
| 160 | /* x2 to enter omap2xxx_sdrc_init_params() */ |
| 161 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
| 162 | |
| 163 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, |
| 164 | bypass); |
| 165 | |
| 166 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); |
| 167 | omap2xxx_sdrc_reprogram(done_rate, 0); |
| 168 | |
| 169 | local_irq_restore(flags); |
| 170 | } |
| 171 | |
| 172 | return 0; |
| 173 | } |
Paul Walmsley | baa689b | 2012-10-29 20:56:00 -0600 | [diff] [blame] | 174 | |
| 175 | /** |
| 176 | * omap2xxx_clkt_vps_check_bootloader_rate - determine which of the rate |
| 177 | * table sets matches the current CORE DPLL hardware rate |
| 178 | * |
| 179 | * Check the MPU rate set by bootloader. Sets the 'curr_prcm_set' |
| 180 | * global to point to the active rate set when found; otherwise, sets |
| 181 | * it to NULL. No return value; |
| 182 | */ |
| 183 | void omap2xxx_clkt_vps_check_bootloader_rates(void) |
| 184 | { |
| 185 | const struct prcm_config *prcm = NULL; |
| 186 | unsigned long rate; |
| 187 | |
| 188 | rate = omap2xxx_clk_get_core_rate(); |
| 189 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
| 190 | if (!(prcm->flags & cpu_mask)) |
| 191 | continue; |
| 192 | if (prcm->xtal_speed != sys_ck_rate) |
| 193 | continue; |
| 194 | if (prcm->dpll_speed <= rate) |
| 195 | break; |
| 196 | } |
| 197 | curr_prcm_set = prcm; |
| 198 | } |
| 199 | |
| 200 | /** |
| 201 | * omap2xxx_clkt_vps_late_init - store a copy of the sys_ck rate |
| 202 | * |
| 203 | * Store a copy of the sys_ck rate for later use by the OMAP2xxx DVFS |
| 204 | * code. (The sys_ck rate does not -- or rather, must not -- change |
| 205 | * during kernel runtime.) Must be called after we have a valid |
| 206 | * sys_ck rate, but before the virt_prcm_set clock rate is |
| 207 | * recalculated. No return value. |
| 208 | */ |
| 209 | void omap2xxx_clkt_vps_late_init(void) |
| 210 | { |
| 211 | struct clk *c; |
| 212 | |
| 213 | c = clk_get(NULL, "sys_ck"); |
| 214 | if (IS_ERR(c)) { |
| 215 | WARN(1, "could not locate sys_ck\n"); |
| 216 | } else { |
| 217 | sys_ck_rate = clk_get_rate(c); |
| 218 | clk_put(c); |
| 219 | } |
| 220 | } |