blob: 10a6dc3d37ac835568083698b1165ea027893739 [file] [log] [blame]
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001/*
Mike Frysinger26fdc1f2008-02-06 01:38:21 -08002 * Blackfin On-Chip SPI Driver
Wu, Bryana5f6abd2007-05-06 14:50:34 -07003 *
Bryan Wu131b17d2007-12-04 23:45:12 -08004 * Copyright 2004-2007 Analog Devices Inc.
Wu, Bryana5f6abd2007-05-06 14:50:34 -07005 *
Mike Frysinger26fdc1f2008-02-06 01:38:21 -08006 * Enter bugs at http://blackfin.uclinux.org/
Wu, Bryana5f6abd2007-05-06 14:50:34 -07007 *
Mike Frysinger26fdc1f2008-02-06 01:38:21 -08008 * Licensed under the GPL-2 or later.
Wu, Bryana5f6abd2007-05-06 14:50:34 -07009 */
10
11#include <linux/init.h>
12#include <linux/module.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080013#include <linux/delay.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070014#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080016#include <linux/io.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070017#include <linux/ioport.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080018#include <linux/irq.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070019#include <linux/errno.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/spi/spi.h>
24#include <linux/workqueue.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070025
Wu, Bryana5f6abd2007-05-06 14:50:34 -070026#include <asm/dma.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080027#include <asm/portmux.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070028#include <asm/bfin5xx_spi.h>
Vitja Makarov8cf58582009-04-06 19:00:31 -070029#include <asm/cacheflush.h>
30
Bryan Wua32c6912007-12-04 23:45:15 -080031#define DRV_NAME "bfin-spi"
32#define DRV_AUTHOR "Bryan Wu, Luke Yang"
Mike Frysinger138f97c2009-04-06 19:00:50 -070033#define DRV_DESC "Blackfin on-chip SPI Controller Driver"
Bryan Wua32c6912007-12-04 23:45:15 -080034#define DRV_VERSION "1.0"
35
36MODULE_AUTHOR(DRV_AUTHOR);
37MODULE_DESCRIPTION(DRV_DESC);
Wu, Bryana5f6abd2007-05-06 14:50:34 -070038MODULE_LICENSE("GPL");
39
Bryan Wubb90eb02007-12-04 23:45:18 -080040#define START_STATE ((void *)0)
41#define RUNNING_STATE ((void *)1)
42#define DONE_STATE ((void *)2)
43#define ERROR_STATE ((void *)-1)
44#define QUEUE_RUNNING 0
45#define QUEUE_STOPPED 1
Wu, Bryana5f6abd2007-05-06 14:50:34 -070046
Wolfgang Muees93b61bd2009-04-06 19:00:53 -070047/* Value to send if no TX value is supplied */
48#define SPI_IDLE_TXVAL 0x0000
49
Wu, Bryana5f6abd2007-05-06 14:50:34 -070050struct driver_data {
51 /* Driver model hookup */
52 struct platform_device *pdev;
53
54 /* SPI framework hookup */
55 struct spi_master *master;
56
Bryan Wubb90eb02007-12-04 23:45:18 -080057 /* Regs base of SPI controller */
Bryan Wuf4521262007-12-04 23:45:22 -080058 void __iomem *regs_base;
Bryan Wubb90eb02007-12-04 23:45:18 -080059
Bryan Wu003d9222007-12-04 23:45:22 -080060 /* Pin request list */
61 u16 *pin_req;
62
Wu, Bryana5f6abd2007-05-06 14:50:34 -070063 /* BFIN hookup */
64 struct bfin5xx_spi_master *master_info;
65
66 /* Driver message queue */
67 struct workqueue_struct *workqueue;
68 struct work_struct pump_messages;
69 spinlock_t lock;
70 struct list_head queue;
71 int busy;
72 int run;
73
74 /* Message Transfer pump */
75 struct tasklet_struct pump_transfers;
76
77 /* Current message transfer state info */
78 struct spi_message *cur_msg;
79 struct spi_transfer *cur_transfer;
80 struct chip_data *cur_chip;
81 size_t len_in_bytes;
82 size_t len;
83 void *tx;
84 void *tx_end;
85 void *rx;
86 void *rx_end;
Bryan Wubb90eb02007-12-04 23:45:18 -080087
88 /* DMA stuffs */
89 int dma_channel;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070090 int dma_mapped;
Bryan Wubb90eb02007-12-04 23:45:18 -080091 int dma_requested;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070092 dma_addr_t rx_dma;
93 dma_addr_t tx_dma;
Bryan Wubb90eb02007-12-04 23:45:18 -080094
Wu, Bryana5f6abd2007-05-06 14:50:34 -070095 size_t rx_map_len;
96 size_t tx_map_len;
97 u8 n_bytes;
Bryan Wufad91c82007-12-04 23:45:14 -080098 int cs_change;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070099 void (*write) (struct driver_data *);
100 void (*read) (struct driver_data *);
101 void (*duplex) (struct driver_data *);
102};
103
104struct chip_data {
105 u16 ctl_reg;
106 u16 baud;
107 u16 flag;
108
109 u8 chip_select_num;
110 u8 n_bytes;
Bryan Wu88b40362007-05-21 18:32:16 +0800111 u8 width; /* 0 or 1 */
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700112 u8 enable_dma;
113 u8 bits_per_word; /* 8 or 16 */
114 u8 cs_change_per_word;
Bryan Wu62310e52007-12-04 23:45:20 -0800115 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
Michael Hennerich42c78b22009-04-06 19:00:51 -0700116 u32 cs_gpio;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700117 u16 idle_tx_val;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700118 void (*write) (struct driver_data *);
119 void (*read) (struct driver_data *);
120 void (*duplex) (struct driver_data *);
121};
122
Bryan Wubb90eb02007-12-04 23:45:18 -0800123#define DEFINE_SPI_REG(reg, off) \
124static inline u16 read_##reg(struct driver_data *drv_data) \
125 { return bfin_read16(drv_data->regs_base + off); } \
126static inline void write_##reg(struct driver_data *drv_data, u16 v) \
127 { bfin_write16(drv_data->regs_base + off, v); }
128
129DEFINE_SPI_REG(CTRL, 0x00)
130DEFINE_SPI_REG(FLAG, 0x04)
131DEFINE_SPI_REG(STAT, 0x08)
132DEFINE_SPI_REG(TDBR, 0x0C)
133DEFINE_SPI_REG(RDBR, 0x10)
134DEFINE_SPI_REG(BAUD, 0x14)
135DEFINE_SPI_REG(SHAW, 0x18)
136
Bryan Wu88b40362007-05-21 18:32:16 +0800137static void bfin_spi_enable(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700138{
139 u16 cr;
140
Bryan Wubb90eb02007-12-04 23:45:18 -0800141 cr = read_CTRL(drv_data);
142 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700143}
144
Bryan Wu88b40362007-05-21 18:32:16 +0800145static void bfin_spi_disable(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700146{
147 u16 cr;
148
Bryan Wubb90eb02007-12-04 23:45:18 -0800149 cr = read_CTRL(drv_data);
150 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700151}
152
153/* Caculate the SPI_BAUD register value based on input HZ */
154static u16 hz_to_spi_baud(u32 speed_hz)
155{
156 u_long sclk = get_sclk();
157 u16 spi_baud = (sclk / (2 * speed_hz));
158
159 if ((sclk % (2 * speed_hz)) > 0)
160 spi_baud++;
161
Michael Hennerich7513e002009-04-06 19:00:32 -0700162 if (spi_baud < MIN_SPI_BAUD_VAL)
163 spi_baud = MIN_SPI_BAUD_VAL;
164
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700165 return spi_baud;
166}
167
Mike Frysinger138f97c2009-04-06 19:00:50 -0700168static int bfin_spi_flush(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700169{
170 unsigned long limit = loops_per_jiffy << 1;
171
172 /* wait for stop and clear stat */
Roel Kluinb4bd2ab2009-06-17 16:26:02 -0700173 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
Bryan Wud8c05002007-12-04 23:45:21 -0800174 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700175
Bryan Wubb90eb02007-12-04 23:45:18 -0800176 write_STAT(drv_data, BIT_STAT_CLR);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700177
178 return limit;
179}
180
Bryan Wufad91c82007-12-04 23:45:14 -0800181/* Chip select operation functions for cs_change flag */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700182static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip)
Bryan Wufad91c82007-12-04 23:45:14 -0800183{
Michael Hennerich42c78b22009-04-06 19:00:51 -0700184 if (likely(chip->chip_select_num)) {
185 u16 flag = read_FLAG(drv_data);
Bryan Wufad91c82007-12-04 23:45:14 -0800186
Michael Hennerich42c78b22009-04-06 19:00:51 -0700187 flag |= chip->flag;
188 flag &= ~(chip->flag << 8);
Bryan Wufad91c82007-12-04 23:45:14 -0800189
Michael Hennerich42c78b22009-04-06 19:00:51 -0700190 write_FLAG(drv_data, flag);
191 } else {
192 gpio_set_value(chip->cs_gpio, 0);
193 }
Bryan Wufad91c82007-12-04 23:45:14 -0800194}
195
Mike Frysinger138f97c2009-04-06 19:00:50 -0700196static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
Bryan Wufad91c82007-12-04 23:45:14 -0800197{
Michael Hennerich42c78b22009-04-06 19:00:51 -0700198 if (likely(chip->chip_select_num)) {
199 u16 flag = read_FLAG(drv_data);
Bryan Wufad91c82007-12-04 23:45:14 -0800200
Michael Hennerich42c78b22009-04-06 19:00:51 -0700201 flag &= ~chip->flag;
202 flag |= (chip->flag << 8);
Bryan Wufad91c82007-12-04 23:45:14 -0800203
Michael Hennerich42c78b22009-04-06 19:00:51 -0700204 write_FLAG(drv_data, flag);
205 } else {
206 gpio_set_value(chip->cs_gpio, 1);
207 }
Bryan Wu62310e52007-12-04 23:45:20 -0800208
209 /* Move delay here for consistency */
210 if (chip->cs_chg_udelay)
211 udelay(chip->cs_chg_udelay);
Bryan Wufad91c82007-12-04 23:45:14 -0800212}
213
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700214/* stop controller and re-config current chip*/
Mike Frysinger138f97c2009-04-06 19:00:50 -0700215static void bfin_spi_restore_state(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700216{
217 struct chip_data *chip = drv_data->cur_chip;
218
219 /* Clear status and disable clock */
Bryan Wubb90eb02007-12-04 23:45:18 -0800220 write_STAT(drv_data, BIT_STAT_CLR);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700221 bfin_spi_disable(drv_data);
Bryan Wu88b40362007-05-21 18:32:16 +0800222 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700223
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700224 /* Load the registers */
Bryan Wubb90eb02007-12-04 23:45:18 -0800225 write_CTRL(drv_data, chip->ctl_reg);
Bryan Wu092e1fd2007-12-04 23:45:23 -0800226 write_BAUD(drv_data, chip->baud);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800227
228 bfin_spi_enable(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700229 bfin_spi_cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700230}
231
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700232/* used to kick off transfer in rx mode and read unwanted RX data */
233static inline void bfin_spi_dummy_read(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700234{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700235 (void) read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700236}
237
Mike Frysinger138f97c2009-04-06 19:00:50 -0700238static void bfin_spi_null_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700239{
240 u8 n_bytes = drv_data->n_bytes;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700241 u16 tx_val = drv_data->cur_chip->idle_tx_val;
242
243 /* clear RXS (we check for RXS inside the loop) */
244 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700245
246 while (drv_data->tx < drv_data->tx_end) {
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700247 write_TDBR(drv_data, tx_val);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700248 drv_data->tx += n_bytes;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700249 /* wait until transfer finished.
250 checking SPIF or TXS may not guarantee transfer completion */
251 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
252 cpu_relax();
253 /* discard RX data and clear RXS */
254 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700255 }
256}
257
Mike Frysinger138f97c2009-04-06 19:00:50 -0700258static void bfin_spi_null_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700259{
260 u8 n_bytes = drv_data->n_bytes;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700261 u16 tx_val = drv_data->cur_chip->idle_tx_val;
262
263 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700264 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700265
266 while (drv_data->rx < drv_data->rx_end) {
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700267 write_TDBR(drv_data, tx_val);
268 drv_data->rx += n_bytes;
Bryan Wubb90eb02007-12-04 23:45:18 -0800269 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800270 cpu_relax();
Mike Frysinger138f97c2009-04-06 19:00:50 -0700271 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700272 }
273}
274
Mike Frysinger138f97c2009-04-06 19:00:50 -0700275static void bfin_spi_u8_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700276{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700277 /* clear RXS (we check for RXS inside the loop) */
278 bfin_spi_dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800279
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700280 while (drv_data->tx < drv_data->tx_end) {
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700281 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
282 /* wait until transfer finished.
283 checking SPIF or TXS may not guarantee transfer completion */
284 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800285 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700286 /* discard RX data and clear RXS */
287 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700288 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700289}
290
Mike Frysinger138f97c2009-04-06 19:00:50 -0700291static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700292{
293 struct chip_data *chip = drv_data->cur_chip;
294
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700295 /* clear RXS (we check for RXS inside the loop) */
296 bfin_spi_dummy_read(drv_data);
297
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700298 while (drv_data->tx < drv_data->tx_end) {
Mike Frysinger138f97c2009-04-06 19:00:50 -0700299 bfin_spi_cs_active(drv_data, chip);
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700300 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
301 /* make sure transfer finished before deactiving CS */
302 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800303 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700304 bfin_spi_dummy_read(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700305 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700306 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700307}
308
Mike Frysinger138f97c2009-04-06 19:00:50 -0700309static void bfin_spi_u8_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700310{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700311 u16 tx_val = drv_data->cur_chip->idle_tx_val;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700312
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700313 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700314 bfin_spi_dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800315
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700316 while (drv_data->rx < drv_data->rx_end) {
317 write_TDBR(drv_data, tx_val);
Bryan Wubb90eb02007-12-04 23:45:18 -0800318 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800319 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700320 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700321 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700322}
323
Mike Frysinger138f97c2009-04-06 19:00:50 -0700324static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700325{
326 struct chip_data *chip = drv_data->cur_chip;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700327 u16 tx_val = chip->idle_tx_val;
328
329 /* discard old RX data and clear RXS */
330 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700331
Bryan Wue26aa012008-02-06 01:38:18 -0800332 while (drv_data->rx < drv_data->rx_end) {
Mike Frysinger138f97c2009-04-06 19:00:50 -0700333 bfin_spi_cs_active(drv_data, chip);
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700334 write_TDBR(drv_data, tx_val);
Bryan Wubb90eb02007-12-04 23:45:18 -0800335 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800336 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700337 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700338 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700339 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700340}
341
Mike Frysinger138f97c2009-04-06 19:00:50 -0700342static void bfin_spi_u8_duplex(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700343{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700344 /* discard old RX data and clear RXS */
345 bfin_spi_dummy_read(drv_data);
346
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700347 while (drv_data->rx < drv_data->rx_end) {
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700348 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
Bryan Wubb90eb02007-12-04 23:45:18 -0800349 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800350 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700351 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700352 }
353}
354
Mike Frysinger138f97c2009-04-06 19:00:50 -0700355static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700356{
357 struct chip_data *chip = drv_data->cur_chip;
358
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700359 /* discard old RX data and clear RXS */
360 bfin_spi_dummy_read(drv_data);
361
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700362 while (drv_data->rx < drv_data->rx_end) {
Mike Frysinger138f97c2009-04-06 19:00:50 -0700363 bfin_spi_cs_active(drv_data, chip);
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700364 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
Bryan Wubb90eb02007-12-04 23:45:18 -0800365 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800366 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700367 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700368 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700369 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700370}
371
Mike Frysinger138f97c2009-04-06 19:00:50 -0700372static void bfin_spi_u16_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700373{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700374 /* clear RXS (we check for RXS inside the loop) */
375 bfin_spi_dummy_read(drv_data);
Bryan Wu88b40362007-05-21 18:32:16 +0800376
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700377 while (drv_data->tx < drv_data->tx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800378 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700379 drv_data->tx += 2;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700380 /* wait until transfer finished.
381 checking SPIF or TXS may not guarantee transfer completion */
382 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
383 cpu_relax();
384 /* discard RX data and clear RXS */
385 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700386 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700387}
388
Mike Frysinger138f97c2009-04-06 19:00:50 -0700389static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700390{
391 struct chip_data *chip = drv_data->cur_chip;
392
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700393 /* clear RXS (we check for RXS inside the loop) */
394 bfin_spi_dummy_read(drv_data);
395
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700396 while (drv_data->tx < drv_data->tx_end) {
Mike Frysinger138f97c2009-04-06 19:00:50 -0700397 bfin_spi_cs_active(drv_data, chip);
Bryan Wubb90eb02007-12-04 23:45:18 -0800398 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700399 drv_data->tx += 2;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700400 /* make sure transfer finished before deactiving CS */
401 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
402 cpu_relax();
403 bfin_spi_dummy_read(drv_data);
404 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700405 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700406}
407
Mike Frysinger138f97c2009-04-06 19:00:50 -0700408static void bfin_spi_u16_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700409{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700410 u16 tx_val = drv_data->cur_chip->idle_tx_val;
Sonic Zhangcc487e72007-12-04 23:45:17 -0800411
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700412 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700413 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700414
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700415 while (drv_data->rx < drv_data->rx_end) {
416 write_TDBR(drv_data, tx_val);
Bryan Wubb90eb02007-12-04 23:45:18 -0800417 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800418 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800419 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700420 drv_data->rx += 2;
421 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700422}
423
Mike Frysinger138f97c2009-04-06 19:00:50 -0700424static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700425{
426 struct chip_data *chip = drv_data->cur_chip;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700427 u16 tx_val = chip->idle_tx_val;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700428
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700429 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700430 bfin_spi_dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800431
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700432 while (drv_data->rx < drv_data->rx_end) {
433 bfin_spi_cs_active(drv_data, chip);
434 write_TDBR(drv_data, tx_val);
Bryan Wubb90eb02007-12-04 23:45:18 -0800435 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800436 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800437 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700438 drv_data->rx += 2;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700439 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700440 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700441}
442
Mike Frysinger138f97c2009-04-06 19:00:50 -0700443static void bfin_spi_u16_duplex(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700444{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700445 /* discard old RX data and clear RXS */
446 bfin_spi_dummy_read(drv_data);
447
448 while (drv_data->rx < drv_data->rx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800449 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700450 drv_data->tx += 2;
Bryan Wubb90eb02007-12-04 23:45:18 -0800451 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800452 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800453 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700454 drv_data->rx += 2;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700455 }
456}
457
Mike Frysinger138f97c2009-04-06 19:00:50 -0700458static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700459{
460 struct chip_data *chip = drv_data->cur_chip;
461
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700462 /* discard old RX data and clear RXS */
463 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700464
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700465 while (drv_data->rx < drv_data->rx_end) {
466 bfin_spi_cs_active(drv_data, chip);
Bryan Wubb90eb02007-12-04 23:45:18 -0800467 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700468 drv_data->tx += 2;
Bryan Wubb90eb02007-12-04 23:45:18 -0800469 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800470 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800471 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700472 drv_data->rx += 2;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700473 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700474 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700475}
476
477/* test if ther is more transfer to be done */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700478static void *bfin_spi_next_transfer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700479{
480 struct spi_message *msg = drv_data->cur_msg;
481 struct spi_transfer *trans = drv_data->cur_transfer;
482
483 /* Move to next transfer */
484 if (trans->transfer_list.next != &msg->transfers) {
485 drv_data->cur_transfer =
486 list_entry(trans->transfer_list.next,
487 struct spi_transfer, transfer_list);
488 return RUNNING_STATE;
489 } else
490 return DONE_STATE;
491}
492
493/*
494 * caller already set message->status;
495 * dma and pio irqs are blocked give finished message back
496 */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700497static void bfin_spi_giveback(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700498{
Bryan Wufad91c82007-12-04 23:45:14 -0800499 struct chip_data *chip = drv_data->cur_chip;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700500 struct spi_transfer *last_transfer;
501 unsigned long flags;
502 struct spi_message *msg;
503
504 spin_lock_irqsave(&drv_data->lock, flags);
505 msg = drv_data->cur_msg;
506 drv_data->cur_msg = NULL;
507 drv_data->cur_transfer = NULL;
508 drv_data->cur_chip = NULL;
509 queue_work(drv_data->workqueue, &drv_data->pump_messages);
510 spin_unlock_irqrestore(&drv_data->lock, flags);
511
512 last_transfer = list_entry(msg->transfers.prev,
513 struct spi_transfer, transfer_list);
514
515 msg->state = NULL;
516
Bryan Wufad91c82007-12-04 23:45:14 -0800517 if (!drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700518 bfin_spi_cs_deactive(drv_data, chip);
Bryan Wufad91c82007-12-04 23:45:14 -0800519
Yi Lib9b2a762009-04-06 19:00:49 -0700520 /* Not stop spi in autobuffer mode */
521 if (drv_data->tx_dma != 0xFFFF)
522 bfin_spi_disable(drv_data);
523
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700524 if (msg->complete)
525 msg->complete(msg->context);
526}
527
Mike Frysinger138f97c2009-04-06 19:00:50 -0700528static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700529{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800530 struct driver_data *drv_data = dev_id;
Bryan Wufad91c82007-12-04 23:45:14 -0800531 struct chip_data *chip = drv_data->cur_chip;
Bryan Wubb90eb02007-12-04 23:45:18 -0800532 struct spi_message *msg = drv_data->cur_msg;
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700533 unsigned long timeout;
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700534 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
Mike Frysinger04b95d22009-04-06 19:00:35 -0700535 u16 spistat = read_STAT(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700536
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700537 dev_dbg(&drv_data->pdev->dev,
538 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
539 dmastat, spistat);
540
Bryan Wubb90eb02007-12-04 23:45:18 -0800541 clear_dma_irqstat(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700542
Bryan Wud6fe89b2007-06-11 17:34:17 +0800543 /* Wait for DMA to complete */
Bryan Wubb90eb02007-12-04 23:45:18 -0800544 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
Bryan Wud8c05002007-12-04 23:45:21 -0800545 cpu_relax();
Bryan Wud6fe89b2007-06-11 17:34:17 +0800546
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700547 /*
Bryan Wud6fe89b2007-06-11 17:34:17 +0800548 * wait for the last transaction shifted out. HRM states:
549 * at this point there may still be data in the SPI DMA FIFO waiting
550 * to be transmitted ... software needs to poll TXS in the SPI_STAT
551 * register until it goes low for 2 successive reads
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700552 */
553 if (drv_data->tx != NULL) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800554 while ((read_STAT(drv_data) & TXS) ||
555 (read_STAT(drv_data) & TXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800556 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700557 }
558
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700559 dev_dbg(&drv_data->pdev->dev,
560 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
561 dmastat, read_STAT(drv_data));
562
563 timeout = jiffies + HZ;
Bryan Wubb90eb02007-12-04 23:45:18 -0800564 while (!(read_STAT(drv_data) & SPIF))
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700565 if (!time_before(jiffies, timeout)) {
566 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
567 break;
568 } else
569 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700570
Mike Frysinger40a29452009-04-06 19:00:38 -0700571 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
Mike Frysinger04b95d22009-04-06 19:00:35 -0700572 msg->state = ERROR_STATE;
573 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
574 } else {
575 msg->actual_length += drv_data->len_in_bytes;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700576
Mike Frysinger04b95d22009-04-06 19:00:35 -0700577 if (drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700578 bfin_spi_cs_deactive(drv_data, chip);
Bryan Wufad91c82007-12-04 23:45:14 -0800579
Mike Frysinger04b95d22009-04-06 19:00:35 -0700580 /* Move to next transfer */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700581 msg->state = bfin_spi_next_transfer(drv_data);
Mike Frysinger04b95d22009-04-06 19:00:35 -0700582 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700583
584 /* Schedule transfer tasklet */
585 tasklet_schedule(&drv_data->pump_transfers);
586
587 /* free the irq handler before next transfer */
Bryan Wu88b40362007-05-21 18:32:16 +0800588 dev_dbg(&drv_data->pdev->dev,
589 "disable dma channel irq%d\n",
Bryan Wubb90eb02007-12-04 23:45:18 -0800590 drv_data->dma_channel);
591 dma_disable_irq(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700592
593 return IRQ_HANDLED;
594}
595
Mike Frysinger138f97c2009-04-06 19:00:50 -0700596static void bfin_spi_pump_transfers(unsigned long data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700597{
598 struct driver_data *drv_data = (struct driver_data *)data;
599 struct spi_message *message = NULL;
600 struct spi_transfer *transfer = NULL;
601 struct spi_transfer *previous = NULL;
602 struct chip_data *chip = NULL;
Bryan Wu88b40362007-05-21 18:32:16 +0800603 u8 width;
604 u16 cr, dma_width, dma_config;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700605 u32 tranf_success = 1;
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700606 u8 full_duplex = 0;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700607
608 /* Get current state information */
609 message = drv_data->cur_msg;
610 transfer = drv_data->cur_transfer;
611 chip = drv_data->cur_chip;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800612
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700613 /*
614 * if msg is error or done, report it back using complete() callback
615 */
616
617 /* Handle for abort */
618 if (message->state == ERROR_STATE) {
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700619 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700620 message->status = -EIO;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700621 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700622 return;
623 }
624
625 /* Handle end of message */
626 if (message->state == DONE_STATE) {
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700627 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700628 message->status = 0;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700629 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700630 return;
631 }
632
633 /* Delay if requested at end of transfer */
634 if (message->state == RUNNING_STATE) {
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700635 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700636 previous = list_entry(transfer->transfer_list.prev,
637 struct spi_transfer, transfer_list);
638 if (previous->delay_usecs)
639 udelay(previous->delay_usecs);
640 }
641
642 /* Setup the transfer state based on the type of transfer */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700643 if (bfin_spi_flush(drv_data) == 0) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700644 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
645 message->status = -EIO;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700646 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700647 return;
648 }
649
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700650 if (transfer->len == 0) {
651 /* Move to next transfer of this msg */
652 message->state = bfin_spi_next_transfer(drv_data);
653 /* Schedule next transfer tasklet */
654 tasklet_schedule(&drv_data->pump_transfers);
655 }
656
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700657 if (transfer->tx_buf != NULL) {
658 drv_data->tx = (void *)transfer->tx_buf;
659 drv_data->tx_end = drv_data->tx + transfer->len;
Bryan Wu88b40362007-05-21 18:32:16 +0800660 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
661 transfer->tx_buf, drv_data->tx_end);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700662 } else {
663 drv_data->tx = NULL;
664 }
665
666 if (transfer->rx_buf != NULL) {
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700667 full_duplex = transfer->tx_buf != NULL;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700668 drv_data->rx = transfer->rx_buf;
669 drv_data->rx_end = drv_data->rx + transfer->len;
Bryan Wu88b40362007-05-21 18:32:16 +0800670 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
671 transfer->rx_buf, drv_data->rx_end);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700672 } else {
673 drv_data->rx = NULL;
674 }
675
676 drv_data->rx_dma = transfer->rx_dma;
677 drv_data->tx_dma = transfer->tx_dma;
678 drv_data->len_in_bytes = transfer->len;
Bryan Wufad91c82007-12-04 23:45:14 -0800679 drv_data->cs_change = transfer->cs_change;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700680
Bryan Wu092e1fd2007-12-04 23:45:23 -0800681 /* Bits per word setup */
682 switch (transfer->bits_per_word) {
683 case 8:
684 drv_data->n_bytes = 1;
685 width = CFG_SPI_WORDSIZE8;
686 drv_data->read = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700687 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800688 drv_data->write = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700689 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800690 drv_data->duplex = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700691 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800692 break;
693
694 case 16:
695 drv_data->n_bytes = 2;
696 width = CFG_SPI_WORDSIZE16;
697 drv_data->read = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700698 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800699 drv_data->write = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700700 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800701 drv_data->duplex = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700702 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800703 break;
704
705 default:
706 /* No change, the same as default setting */
707 drv_data->n_bytes = chip->n_bytes;
708 width = chip->width;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700709 drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer;
710 drv_data->read = drv_data->rx ? chip->read : bfin_spi_null_reader;
711 drv_data->duplex = chip->duplex ? chip->duplex : bfin_spi_null_writer;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800712 break;
713 }
714 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
715 cr |= (width << 8);
716 write_CTRL(drv_data, cr);
717
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700718 if (width == CFG_SPI_WORDSIZE16) {
719 drv_data->len = (transfer->len) >> 1;
720 } else {
721 drv_data->len = transfer->len;
722 }
Mike Frysinger4fb98ef2008-04-08 17:41:57 -0700723 dev_dbg(&drv_data->pdev->dev,
724 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
Mike Frysinger138f97c2009-04-06 19:00:50 -0700725 drv_data->write, chip->write, bfin_spi_null_writer);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700726
727 /* speed and width has been set on per message */
728 message->state = RUNNING_STATE;
729 dma_config = 0;
730
Bryan Wu092e1fd2007-12-04 23:45:23 -0800731 /* Speed setup (surely valid because already checked) */
732 if (transfer->speed_hz)
733 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
734 else
735 write_BAUD(drv_data, chip->baud);
736
Bryan Wubb90eb02007-12-04 23:45:18 -0800737 write_STAT(drv_data, BIT_STAT_CLR);
738 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
Yi Lib9b2a762009-04-06 19:00:49 -0700739 if (drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700740 bfin_spi_cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700741
Bryan Wu88b40362007-05-21 18:32:16 +0800742 dev_dbg(&drv_data->pdev->dev,
743 "now pumping a transfer: width is %d, len is %d\n",
744 width, transfer->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700745
746 /*
Vitja Makarov8cf58582009-04-06 19:00:31 -0700747 * Try to map dma buffer and do a dma transfer. If successful use,
748 * different way to r/w according to the enable_dma settings and if
749 * we are not doing a full duplex transfer (since the hardware does
750 * not support full duplex DMA transfers).
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700751 */
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700752 if (!full_duplex && drv_data->cur_chip->enable_dma
753 && drv_data->len > 6) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700754
Mike Frysinger11d6f592009-04-06 19:00:41 -0700755 unsigned long dma_start_addr, flags;
Mike Frysinger7aec3562009-04-06 19:00:36 -0700756
Bryan Wubb90eb02007-12-04 23:45:18 -0800757 disable_dma(drv_data->dma_channel);
758 clear_dma_irqstat(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700759
760 /* config dma channel */
Bryan Wu88b40362007-05-21 18:32:16 +0800761 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
Mike Frysinger7aec3562009-04-06 19:00:36 -0700762 set_dma_x_count(drv_data->dma_channel, drv_data->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700763 if (width == CFG_SPI_WORDSIZE16) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800764 set_dma_x_modify(drv_data->dma_channel, 2);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700765 dma_width = WDSIZE_16;
766 } else {
Bryan Wubb90eb02007-12-04 23:45:18 -0800767 set_dma_x_modify(drv_data->dma_channel, 1);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700768 dma_width = WDSIZE_8;
769 }
770
Sonic Zhang3f479a62007-12-04 23:45:18 -0800771 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800772 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800773 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800774
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700775 /* dirty hack for autobuffer DMA mode */
776 if (drv_data->tx_dma == 0xFFFF) {
Bryan Wu88b40362007-05-21 18:32:16 +0800777 dev_dbg(&drv_data->pdev->dev,
778 "doing autobuffer DMA out.\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700779
780 /* no irq in autobuffer mode */
781 dma_config =
782 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
Bryan Wubb90eb02007-12-04 23:45:18 -0800783 set_dma_config(drv_data->dma_channel, dma_config);
784 set_dma_start_addr(drv_data->dma_channel,
Bryan Wua32c6912007-12-04 23:45:15 -0800785 (unsigned long)drv_data->tx);
Bryan Wubb90eb02007-12-04 23:45:18 -0800786 enable_dma(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700787
Sonic Zhang07612e52007-12-04 23:45:21 -0800788 /* start SPI transfer */
Mike Frysinger11d6f592009-04-06 19:00:41 -0700789 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
Sonic Zhang07612e52007-12-04 23:45:21 -0800790
791 /* just return here, there can only be one transfer
792 * in this mode
793 */
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700794 message->status = 0;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700795 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700796 return;
797 }
798
799 /* In dma mode, rx or tx must be NULL in one transfer */
Mike Frysinger7aec3562009-04-06 19:00:36 -0700800 dma_config = (RESTART | dma_width | DI_EN);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700801 if (drv_data->rx != NULL) {
802 /* set transfer mode, and enable SPI */
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700803 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
804 drv_data->rx, drv_data->len_in_bytes);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700805
Vitja Makarov8cf58582009-04-06 19:00:31 -0700806 /* invalidate caches, if needed */
Jie Zhang67834fa2009-06-10 06:26:26 +0000807 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
Vitja Makarov8cf58582009-04-06 19:00:31 -0700808 invalidate_dcache_range((unsigned long) drv_data->rx,
809 (unsigned long) (drv_data->rx +
Mike Frysingerace32862009-04-06 19:00:34 -0700810 drv_data->len_in_bytes));
Vitja Makarov8cf58582009-04-06 19:00:31 -0700811
Mike Frysinger7aec3562009-04-06 19:00:36 -0700812 dma_config |= WNR;
813 dma_start_addr = (unsigned long)drv_data->rx;
Mike Frysingerb31e27a2009-04-06 19:00:39 -0700814 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
Sonic Zhang07612e52007-12-04 23:45:21 -0800815
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700816 } else if (drv_data->tx != NULL) {
Bryan Wu88b40362007-05-21 18:32:16 +0800817 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700818
Vitja Makarov8cf58582009-04-06 19:00:31 -0700819 /* flush caches, if needed */
Jie Zhang67834fa2009-06-10 06:26:26 +0000820 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
Vitja Makarov8cf58582009-04-06 19:00:31 -0700821 flush_dcache_range((unsigned long) drv_data->tx,
822 (unsigned long) (drv_data->tx +
Mike Frysingerace32862009-04-06 19:00:34 -0700823 drv_data->len_in_bytes));
Vitja Makarov8cf58582009-04-06 19:00:31 -0700824
Mike Frysinger7aec3562009-04-06 19:00:36 -0700825 dma_start_addr = (unsigned long)drv_data->tx;
Mike Frysingerb31e27a2009-04-06 19:00:39 -0700826 cr |= BIT_CTL_TIMOD_DMA_TX;
Sonic Zhang07612e52007-12-04 23:45:21 -0800827
Mike Frysinger7aec3562009-04-06 19:00:36 -0700828 } else
829 BUG();
830
Mike Frysinger11d6f592009-04-06 19:00:41 -0700831 /* oh man, here there be monsters ... and i dont mean the
832 * fluffy cute ones from pixar, i mean the kind that'll eat
833 * your data, kick your dog, and love it all. do *not* try
834 * and change these lines unless you (1) heavily test DMA
835 * with SPI flashes on a loaded system (e.g. ping floods),
836 * (2) know just how broken the DMA engine interaction with
837 * the SPI peripheral is, and (3) have someone else to blame
838 * when you screw it all up anyways.
839 */
Mike Frysinger7aec3562009-04-06 19:00:36 -0700840 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
Mike Frysinger11d6f592009-04-06 19:00:41 -0700841 set_dma_config(drv_data->dma_channel, dma_config);
842 local_irq_save(flags);
Mike Frysingera963ea82009-04-06 19:00:43 -0700843 SSYNC();
Mike Frysinger11d6f592009-04-06 19:00:41 -0700844 write_CTRL(drv_data, cr);
Mike Frysingera963ea82009-04-06 19:00:43 -0700845 enable_dma(drv_data->dma_channel);
Mike Frysinger11d6f592009-04-06 19:00:41 -0700846 dma_enable_irq(drv_data->dma_channel);
847 local_irq_restore(flags);
Mike Frysinger7aec3562009-04-06 19:00:36 -0700848
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700849 } else {
850 /* IO mode write then read */
Bryan Wu88b40362007-05-21 18:32:16 +0800851 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700852
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700853 /* we always use SPI_WRITE mode. SPI_READ mode
854 seems to have problems with setting up the
855 output value in TDBR prior to the transfer. */
856 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
857
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700858 if (full_duplex) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700859 /* full duplex mode */
860 BUG_ON((drv_data->tx_end - drv_data->tx) !=
861 (drv_data->rx_end - drv_data->rx));
Bryan Wu88b40362007-05-21 18:32:16 +0800862 dev_dbg(&drv_data->pdev->dev,
863 "IO duplex: cr is 0x%x\n", cr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700864
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700865 drv_data->duplex(drv_data);
866
867 if (drv_data->tx != drv_data->tx_end)
868 tranf_success = 0;
869 } else if (drv_data->tx != NULL) {
870 /* write only half duplex */
Bryan Wu131b17d2007-12-04 23:45:12 -0800871 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800872 "IO write: cr is 0x%x\n", cr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700873
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700874 drv_data->write(drv_data);
875
876 if (drv_data->tx != drv_data->tx_end)
877 tranf_success = 0;
878 } else if (drv_data->rx != NULL) {
879 /* read only half duplex */
Bryan Wu131b17d2007-12-04 23:45:12 -0800880 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800881 "IO read: cr is 0x%x\n", cr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700882
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700883 drv_data->read(drv_data);
884 if (drv_data->rx != drv_data->rx_end)
885 tranf_success = 0;
886 }
887
888 if (!tranf_success) {
Bryan Wu131b17d2007-12-04 23:45:12 -0800889 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800890 "IO write error!\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700891 message->state = ERROR_STATE;
892 } else {
893 /* Update total byte transfered */
Mike Frysingerace32862009-04-06 19:00:34 -0700894 message->actual_length += drv_data->len_in_bytes;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700895 /* Move to next transfer of this msg */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700896 message->state = bfin_spi_next_transfer(drv_data);
Yi Lib9b2a762009-04-06 19:00:49 -0700897 if (drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700898 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700899 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700900 /* Schedule next transfer tasklet */
901 tasklet_schedule(&drv_data->pump_transfers);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700902 }
903}
904
905/* pop a msg from queue and kick off real transfer */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700906static void bfin_spi_pump_messages(struct work_struct *work)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700907{
Bryan Wu131b17d2007-12-04 23:45:12 -0800908 struct driver_data *drv_data;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700909 unsigned long flags;
910
Bryan Wu131b17d2007-12-04 23:45:12 -0800911 drv_data = container_of(work, struct driver_data, pump_messages);
912
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700913 /* Lock queue and check for queue work */
914 spin_lock_irqsave(&drv_data->lock, flags);
915 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
916 /* pumper kicked off but no work to do */
917 drv_data->busy = 0;
918 spin_unlock_irqrestore(&drv_data->lock, flags);
919 return;
920 }
921
922 /* Make sure we are not already running a message */
923 if (drv_data->cur_msg) {
924 spin_unlock_irqrestore(&drv_data->lock, flags);
925 return;
926 }
927
928 /* Extract head of queue */
929 drv_data->cur_msg = list_entry(drv_data->queue.next,
930 struct spi_message, queue);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800931
932 /* Setup the SSP using the per chip configuration */
933 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700934 bfin_spi_restore_state(drv_data);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800935
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700936 list_del_init(&drv_data->cur_msg->queue);
937
938 /* Initial message state */
939 drv_data->cur_msg->state = START_STATE;
940 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
941 struct spi_transfer, transfer_list);
942
Bryan Wu5fec5b52007-12-04 23:45:13 -0800943 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
944 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
945 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
946 drv_data->cur_chip->ctl_reg);
Bryan Wu131b17d2007-12-04 23:45:12 -0800947
948 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800949 "the first transfer len is %d\n",
950 drv_data->cur_transfer->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700951
952 /* Mark as busy and launch transfers */
953 tasklet_schedule(&drv_data->pump_transfers);
954
955 drv_data->busy = 1;
956 spin_unlock_irqrestore(&drv_data->lock, flags);
957}
958
959/*
960 * got a msg to transfer, queue it in drv_data->queue.
961 * And kick off message pumper
962 */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700963static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700964{
965 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
966 unsigned long flags;
967
968 spin_lock_irqsave(&drv_data->lock, flags);
969
970 if (drv_data->run == QUEUE_STOPPED) {
971 spin_unlock_irqrestore(&drv_data->lock, flags);
972 return -ESHUTDOWN;
973 }
974
975 msg->actual_length = 0;
976 msg->status = -EINPROGRESS;
977 msg->state = START_STATE;
978
Bryan Wu88b40362007-05-21 18:32:16 +0800979 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700980 list_add_tail(&msg->queue, &drv_data->queue);
981
982 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
983 queue_work(drv_data->workqueue, &drv_data->pump_messages);
984
985 spin_unlock_irqrestore(&drv_data->lock, flags);
986
987 return 0;
988}
989
Sonic Zhang12e17c42007-12-04 23:45:16 -0800990#define MAX_SPI_SSEL 7
991
Mike Frysinger4160bde2009-04-06 19:00:40 -0700992static u16 ssel[][MAX_SPI_SSEL] = {
Sonic Zhang12e17c42007-12-04 23:45:16 -0800993 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
994 P_SPI0_SSEL4, P_SPI0_SSEL5,
995 P_SPI0_SSEL6, P_SPI0_SSEL7},
996
997 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
998 P_SPI1_SSEL4, P_SPI1_SSEL5,
999 P_SPI1_SSEL6, P_SPI1_SSEL7},
1000
1001 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1002 P_SPI2_SSEL4, P_SPI2_SSEL5,
1003 P_SPI2_SSEL6, P_SPI2_SSEL7},
1004};
1005
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001006/* first setup for new devices */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001007static int bfin_spi_setup(struct spi_device *spi)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001008{
1009 struct bfin5xx_spi_chip *chip_info = NULL;
1010 struct chip_data *chip;
1011 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
Michael Hennerich42c78b22009-04-06 19:00:51 -07001012 int ret;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001013
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001014 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1015 return -EINVAL;
1016
1017 /* Only alloc (or use chip_info) on first setup */
1018 chip = spi_get_ctldata(spi);
1019 if (chip == NULL) {
1020 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1021 if (!chip)
1022 return -ENOMEM;
1023
1024 chip->enable_dma = 0;
1025 chip_info = spi->controller_data;
1026 }
1027
1028 /* chip_info isn't always needed */
1029 if (chip_info) {
Mike Frysinger2ed35512007-12-04 23:45:14 -08001030 /* Make sure people stop trying to set fields via ctl_reg
1031 * when they should actually be using common SPI framework.
1032 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1033 * Not sure if a user actually needs/uses any of these,
1034 * but let's assume (for now) they do.
1035 */
1036 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1037 dev_err(&spi->dev, "do not set bits in ctl_reg "
1038 "that the SPI framework manages\n");
1039 return -EINVAL;
1040 }
1041
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001042 chip->enable_dma = chip_info->enable_dma != 0
1043 && drv_data->master_info->enable_dma;
1044 chip->ctl_reg = chip_info->ctl_reg;
1045 chip->bits_per_word = chip_info->bits_per_word;
1046 chip->cs_change_per_word = chip_info->cs_change_per_word;
1047 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
Michael Hennerich42c78b22009-04-06 19:00:51 -07001048 chip->cs_gpio = chip_info->cs_gpio;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -07001049 chip->idle_tx_val = chip_info->idle_tx_val;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001050 }
1051
1052 /* translate common spi framework into our register */
1053 if (spi->mode & SPI_CPOL)
1054 chip->ctl_reg |= CPOL;
1055 if (spi->mode & SPI_CPHA)
1056 chip->ctl_reg |= CPHA;
1057 if (spi->mode & SPI_LSB_FIRST)
1058 chip->ctl_reg |= LSBF;
1059 /* we dont support running in slave mode (yet?) */
1060 chip->ctl_reg |= MSTR;
1061
1062 /*
1063 * if any one SPI chip is registered and wants DMA, request the
1064 * DMA channel for it
1065 */
Bryan Wubb90eb02007-12-04 23:45:18 -08001066 if (chip->enable_dma && !drv_data->dma_requested) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001067 /* register dma irq handler */
Mike Frysinger59bfcc62009-04-06 19:00:37 -07001068 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
Bryan Wu88b40362007-05-21 18:32:16 +08001069 dev_dbg(&spi->dev,
1070 "Unable to request BlackFin SPI DMA channel\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001071 return -ENODEV;
1072 }
Bryan Wubb90eb02007-12-04 23:45:18 -08001073 if (set_dma_callback(drv_data->dma_channel,
Mike Frysinger138f97c2009-04-06 19:00:50 -07001074 bfin_spi_dma_irq_handler, drv_data) < 0) {
Bryan Wu88b40362007-05-21 18:32:16 +08001075 dev_dbg(&spi->dev, "Unable to set dma callback\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001076 return -EPERM;
1077 }
Bryan Wubb90eb02007-12-04 23:45:18 -08001078 dma_disable_irq(drv_data->dma_channel);
1079 drv_data->dma_requested = 1;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001080 }
1081
1082 /*
1083 * Notice: for blackfin, the speed_hz is the value of register
1084 * SPI_BAUD, not the real baudrate
1085 */
1086 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
Yi Li2cf36832009-04-06 19:00:44 -07001087 chip->flag = 1 << (spi->chip_select);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001088 chip->chip_select_num = spi->chip_select;
1089
Michael Hennerich42c78b22009-04-06 19:00:51 -07001090 if (chip->chip_select_num == 0) {
1091 ret = gpio_request(chip->cs_gpio, spi->modalias);
1092 if (ret) {
1093 if (drv_data->dma_requested)
1094 free_dma(drv_data->dma_channel);
1095 return ret;
1096 }
1097 gpio_direction_output(chip->cs_gpio, 1);
1098 }
1099
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001100 switch (chip->bits_per_word) {
1101 case 8:
1102 chip->n_bytes = 1;
1103 chip->width = CFG_SPI_WORDSIZE8;
1104 chip->read = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001105 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001106 chip->write = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001107 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001108 chip->duplex = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001109 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001110 break;
1111
1112 case 16:
1113 chip->n_bytes = 2;
1114 chip->width = CFG_SPI_WORDSIZE16;
1115 chip->read = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001116 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001117 chip->write = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001118 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001119 chip->duplex = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001120 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001121 break;
1122
1123 default:
1124 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1125 chip->bits_per_word);
Mike Frysinger138f97c2009-04-06 19:00:50 -07001126 if (chip_info)
1127 kfree(chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001128 return -ENODEV;
1129 }
1130
Joe Perches898eb712007-10-18 03:06:30 -07001131 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001132 spi->modalias, chip->width, chip->enable_dma);
Bryan Wu88b40362007-05-21 18:32:16 +08001133 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001134 chip->ctl_reg, chip->flag);
1135
1136 spi_set_ctldata(spi, chip);
1137
Sonic Zhang12e17c42007-12-04 23:45:16 -08001138 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1139 if ((chip->chip_select_num > 0)
1140 && (chip->chip_select_num <= spi->master->num_chipselect))
1141 peripheral_request(ssel[spi->master->bus_num]
Bryan Wuaab0d832008-02-06 01:38:17 -08001142 [chip->chip_select_num-1], spi->modalias);
Sonic Zhang12e17c42007-12-04 23:45:16 -08001143
Mike Frysinger138f97c2009-04-06 19:00:50 -07001144 bfin_spi_cs_deactive(drv_data, chip);
Sonic Zhang07612e52007-12-04 23:45:21 -08001145
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001146 return 0;
1147}
1148
1149/*
1150 * callback for spi framework.
1151 * clean driver specific data
1152 */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001153static void bfin_spi_cleanup(struct spi_device *spi)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001154{
Mike Frysinger27bb9e72007-06-11 15:31:30 +08001155 struct chip_data *chip = spi_get_ctldata(spi);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001156
Mike Frysingere7d02e32009-04-06 19:00:51 -07001157 if (!chip)
1158 return;
1159
Sonic Zhang12e17c42007-12-04 23:45:16 -08001160 if ((chip->chip_select_num > 0)
1161 && (chip->chip_select_num <= spi->master->num_chipselect))
1162 peripheral_free(ssel[spi->master->bus_num]
1163 [chip->chip_select_num-1]);
1164
Michael Hennerich42c78b22009-04-06 19:00:51 -07001165 if (chip->chip_select_num == 0)
1166 gpio_free(chip->cs_gpio);
1167
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001168 kfree(chip);
1169}
1170
Mike Frysinger138f97c2009-04-06 19:00:50 -07001171static inline int bfin_spi_init_queue(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001172{
1173 INIT_LIST_HEAD(&drv_data->queue);
1174 spin_lock_init(&drv_data->lock);
1175
1176 drv_data->run = QUEUE_STOPPED;
1177 drv_data->busy = 0;
1178
1179 /* init transfer tasklet */
1180 tasklet_init(&drv_data->pump_transfers,
Mike Frysinger138f97c2009-04-06 19:00:50 -07001181 bfin_spi_pump_transfers, (unsigned long)drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001182
1183 /* init messages workqueue */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001184 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
Kay Sievers6c7377a2009-03-24 16:38:21 -07001185 drv_data->workqueue = create_singlethread_workqueue(
1186 dev_name(drv_data->master->dev.parent));
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001187 if (drv_data->workqueue == NULL)
1188 return -EBUSY;
1189
1190 return 0;
1191}
1192
Mike Frysinger138f97c2009-04-06 19:00:50 -07001193static inline int bfin_spi_start_queue(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001194{
1195 unsigned long flags;
1196
1197 spin_lock_irqsave(&drv_data->lock, flags);
1198
1199 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1200 spin_unlock_irqrestore(&drv_data->lock, flags);
1201 return -EBUSY;
1202 }
1203
1204 drv_data->run = QUEUE_RUNNING;
1205 drv_data->cur_msg = NULL;
1206 drv_data->cur_transfer = NULL;
1207 drv_data->cur_chip = NULL;
1208 spin_unlock_irqrestore(&drv_data->lock, flags);
1209
1210 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1211
1212 return 0;
1213}
1214
Mike Frysinger138f97c2009-04-06 19:00:50 -07001215static inline int bfin_spi_stop_queue(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001216{
1217 unsigned long flags;
1218 unsigned limit = 500;
1219 int status = 0;
1220
1221 spin_lock_irqsave(&drv_data->lock, flags);
1222
1223 /*
1224 * This is a bit lame, but is optimized for the common execution path.
1225 * A wait_queue on the drv_data->busy could be used, but then the common
1226 * execution path (pump_messages) would be required to call wake_up or
1227 * friends on every SPI message. Do this instead
1228 */
1229 drv_data->run = QUEUE_STOPPED;
1230 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1231 spin_unlock_irqrestore(&drv_data->lock, flags);
1232 msleep(10);
1233 spin_lock_irqsave(&drv_data->lock, flags);
1234 }
1235
1236 if (!list_empty(&drv_data->queue) || drv_data->busy)
1237 status = -EBUSY;
1238
1239 spin_unlock_irqrestore(&drv_data->lock, flags);
1240
1241 return status;
1242}
1243
Mike Frysinger138f97c2009-04-06 19:00:50 -07001244static inline int bfin_spi_destroy_queue(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001245{
1246 int status;
1247
Mike Frysinger138f97c2009-04-06 19:00:50 -07001248 status = bfin_spi_stop_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001249 if (status != 0)
1250 return status;
1251
1252 destroy_workqueue(drv_data->workqueue);
1253
1254 return 0;
1255}
1256
Mike Frysinger138f97c2009-04-06 19:00:50 -07001257static int __init bfin_spi_probe(struct platform_device *pdev)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001258{
1259 struct device *dev = &pdev->dev;
1260 struct bfin5xx_spi_master *platform_info;
1261 struct spi_master *master;
1262 struct driver_data *drv_data = 0;
Bryan Wua32c6912007-12-04 23:45:15 -08001263 struct resource *res;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001264 int status = 0;
1265
1266 platform_info = dev->platform_data;
1267
1268 /* Allocate master with space for drv_data */
1269 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1270 if (!master) {
1271 dev_err(&pdev->dev, "can not alloc spi_master\n");
1272 return -ENOMEM;
1273 }
Bryan Wu131b17d2007-12-04 23:45:12 -08001274
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001275 drv_data = spi_master_get_devdata(master);
1276 drv_data->master = master;
1277 drv_data->master_info = platform_info;
1278 drv_data->pdev = pdev;
Bryan Wu003d9222007-12-04 23:45:22 -08001279 drv_data->pin_req = platform_info->pin_req;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001280
David Brownelle7db06b2009-06-17 16:26:04 -07001281 /* the spi->mode bits supported by this driver: */
1282 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1283
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001284 master->bus_num = pdev->id;
1285 master->num_chipselect = platform_info->num_chipselect;
Mike Frysinger138f97c2009-04-06 19:00:50 -07001286 master->cleanup = bfin_spi_cleanup;
1287 master->setup = bfin_spi_setup;
1288 master->transfer = bfin_spi_transfer;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001289
Bryan Wua32c6912007-12-04 23:45:15 -08001290 /* Find and map our resources */
1291 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1292 if (res == NULL) {
1293 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1294 status = -ENOENT;
1295 goto out_error_get_res;
1296 }
1297
hartleys74947b82009-12-14 22:33:43 +00001298 drv_data->regs_base = ioremap(res->start, resource_size(res));
Bryan Wuf4521262007-12-04 23:45:22 -08001299 if (drv_data->regs_base == NULL) {
Bryan Wua32c6912007-12-04 23:45:15 -08001300 dev_err(dev, "Cannot map IO\n");
1301 status = -ENXIO;
1302 goto out_error_ioremap;
1303 }
1304
Bryan Wubb90eb02007-12-04 23:45:18 -08001305 drv_data->dma_channel = platform_get_irq(pdev, 0);
1306 if (drv_data->dma_channel < 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001307 dev_err(dev, "No DMA channel specified\n");
1308 status = -ENOENT;
1309 goto out_error_no_dma_ch;
1310 }
1311
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001312 /* Initial and start queue */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001313 status = bfin_spi_init_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001314 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001315 dev_err(dev, "problem initializing queue\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001316 goto out_error_queue_alloc;
1317 }
Bryan Wua32c6912007-12-04 23:45:15 -08001318
Mike Frysinger138f97c2009-04-06 19:00:50 -07001319 status = bfin_spi_start_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001320 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001321 dev_err(dev, "problem starting queue\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001322 goto out_error_queue_alloc;
1323 }
1324
Vitja Makarovf9e522c2008-04-08 17:41:57 -07001325 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1326 if (status != 0) {
1327 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1328 goto out_error_queue_alloc;
1329 }
1330
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001331 /* Register with the SPI framework */
1332 platform_set_drvdata(pdev, drv_data);
1333 status = spi_register_master(master);
1334 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001335 dev_err(dev, "problem registering spi master\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001336 goto out_error_queue_alloc;
1337 }
Bryan Wua32c6912007-12-04 23:45:15 -08001338
Bryan Wuf4521262007-12-04 23:45:22 -08001339 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
Bryan Wubb90eb02007-12-04 23:45:18 -08001340 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1341 drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001342 return status;
1343
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001344out_error_queue_alloc:
Mike Frysinger138f97c2009-04-06 19:00:50 -07001345 bfin_spi_destroy_queue(drv_data);
Bryan Wua32c6912007-12-04 23:45:15 -08001346out_error_no_dma_ch:
Bryan Wubb90eb02007-12-04 23:45:18 -08001347 iounmap((void *) drv_data->regs_base);
Bryan Wua32c6912007-12-04 23:45:15 -08001348out_error_ioremap:
1349out_error_get_res:
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001350 spi_master_put(master);
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001351
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001352 return status;
1353}
1354
1355/* stop hardware and remove the driver */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001356static int __devexit bfin_spi_remove(struct platform_device *pdev)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001357{
1358 struct driver_data *drv_data = platform_get_drvdata(pdev);
1359 int status = 0;
1360
1361 if (!drv_data)
1362 return 0;
1363
1364 /* Remove the queue */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001365 status = bfin_spi_destroy_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001366 if (status != 0)
1367 return status;
1368
1369 /* Disable the SSP at the peripheral and SOC level */
1370 bfin_spi_disable(drv_data);
1371
1372 /* Release DMA */
1373 if (drv_data->master_info->enable_dma) {
Bryan Wubb90eb02007-12-04 23:45:18 -08001374 if (dma_channel_active(drv_data->dma_channel))
1375 free_dma(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001376 }
1377
1378 /* Disconnect from the SPI framework */
1379 spi_unregister_master(drv_data->master);
1380
Bryan Wu003d9222007-12-04 23:45:22 -08001381 peripheral_free_list(drv_data->pin_req);
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001382
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001383 /* Prevent double remove */
1384 platform_set_drvdata(pdev, NULL);
1385
1386 return 0;
1387}
1388
1389#ifdef CONFIG_PM
Mike Frysinger138f97c2009-04-06 19:00:50 -07001390static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001391{
1392 struct driver_data *drv_data = platform_get_drvdata(pdev);
1393 int status = 0;
1394
Mike Frysinger138f97c2009-04-06 19:00:50 -07001395 status = bfin_spi_stop_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001396 if (status != 0)
1397 return status;
1398
1399 /* stop hardware */
1400 bfin_spi_disable(drv_data);
1401
1402 return 0;
1403}
1404
Mike Frysinger138f97c2009-04-06 19:00:50 -07001405static int bfin_spi_resume(struct platform_device *pdev)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001406{
1407 struct driver_data *drv_data = platform_get_drvdata(pdev);
1408 int status = 0;
1409
1410 /* Enable the SPI interface */
1411 bfin_spi_enable(drv_data);
1412
1413 /* Start the queue running */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001414 status = bfin_spi_start_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001415 if (status != 0) {
1416 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1417 return status;
1418 }
1419
1420 return 0;
1421}
1422#else
Mike Frysinger138f97c2009-04-06 19:00:50 -07001423#define bfin_spi_suspend NULL
1424#define bfin_spi_resume NULL
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001425#endif /* CONFIG_PM */
1426
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001427MODULE_ALIAS("platform:bfin-spi");
Mike Frysinger138f97c2009-04-06 19:00:50 -07001428static struct platform_driver bfin_spi_driver = {
David Brownellfc3ba952007-08-30 23:56:24 -07001429 .driver = {
Bryan Wua32c6912007-12-04 23:45:15 -08001430 .name = DRV_NAME,
Bryan Wu88b40362007-05-21 18:32:16 +08001431 .owner = THIS_MODULE,
1432 },
Mike Frysinger138f97c2009-04-06 19:00:50 -07001433 .suspend = bfin_spi_suspend,
1434 .resume = bfin_spi_resume,
1435 .remove = __devexit_p(bfin_spi_remove),
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001436};
1437
Mike Frysinger138f97c2009-04-06 19:00:50 -07001438static int __init bfin_spi_init(void)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001439{
Mike Frysinger138f97c2009-04-06 19:00:50 -07001440 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001441}
Mike Frysinger138f97c2009-04-06 19:00:50 -07001442module_init(bfin_spi_init);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001443
Mike Frysinger138f97c2009-04-06 19:00:50 -07001444static void __exit bfin_spi_exit(void)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001445{
Mike Frysinger138f97c2009-04-06 19:00:50 -07001446 platform_driver_unregister(&bfin_spi_driver);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001447}
Mike Frysinger138f97c2009-04-06 19:00:50 -07001448module_exit(bfin_spi_exit);