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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04002 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
Alan Coxd96212e2005-12-08 19:19:50 +000040 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
Alan2c5ff672006-12-04 16:33:20 +000043 * driver the list of errata that are relevant is below, going back to
Alan Coxd96212e2005-12-08 19:19:50 +000044 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
Jeff Garzik6248e642005-10-30 06:42:18 -050091#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070092#include <scsi/scsi_host.h>
93#include <linux/libata.h>
Tejun Heob8b275e2007-07-10 15:55:43 +090094#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070095
96#define DRV_NAME "ata_piix"
Jeff Garzik2a3103c2007-08-31 04:54:06 -040097#define DRV_VERSION "2.12"
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
Greg Felix7b6dbd62005-07-28 15:54:15 -0400103 PIIX_SCC = 0x0A, /* sub-class code register */
Tejun Heoc7290722008-01-18 18:36:30 +0900104 PIIX_SIDPR_BAR = 5,
105 PIIX_SIDPR_LEN = 16,
106 PIIX_SIDPR_IDX = 0,
107 PIIX_SIDPR_DATA = 4,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108
Tejun Heoff0fc142005-12-18 17:17:07 +0900109 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
Tejun Heoc7290722008-01-18 18:36:30 +0900111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112
Tejun Heo800b3992006-12-03 21:34:13 +0900113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
Tejun Heob3362f82006-11-10 18:08:10 +0900115
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116 PIIX_80C_PRI = (1 << 5) | (1 << 4),
117 PIIX_80C_SEC = (1 << 7) | (1 << 6),
118
Tejun Heod33f58b2006-03-01 01:25:39 +0900119 /* constants for mapping table */
120 P0 = 0, /* port 0 */
121 P1 = 1, /* port 1 */
122 P2 = 2, /* port 2 */
123 P3 = 3, /* port 3 */
124 IDE = -1, /* IDE */
125 NA = -2, /* not avaliable */
126 RV = -3, /* reserved */
127
Greg Felix7b6dbd62005-07-28 15:54:15 -0400128 PIIX_AHCI_DEVICE = 6,
Tejun Heob8b275e2007-07-10 15:55:43 +0900129
130 /* host->flags bits */
131 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132};
133
Tejun Heo9cde9ed12007-11-24 21:16:07 +0900134enum piix_controller_ids {
135 /* controller IDs */
136 piix_pata_mwdma, /* PIIX3 MWDMA only */
137 piix_pata_33, /* PIIX4 at 33Mhz */
138 ich_pata_33, /* ICH up to UDMA 33 only */
139 ich_pata_66, /* ICH up to 66 Mhz */
140 ich_pata_100, /* ICH up to UDMA 100 */
141 ich5_sata,
142 ich6_sata,
143 ich6_sata_ahci,
144 ich6m_sata_ahci,
145 ich8_sata_ahci,
146 ich8_2port_sata,
147 ich8m_apple_sata_ahci, /* locks up on second port enable */
148 tolapai_sata_ahci,
149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
150};
151
Tejun Heod33f58b2006-03-01 01:25:39 +0900152struct piix_map_db {
153 const u32 mask;
Jeff Garzik73291a12006-07-11 13:11:17 -0400154 const u16 port_enable;
Tejun Heod33f58b2006-03-01 01:25:39 +0900155 const int map[][4];
156};
157
Tejun Heod96715c2006-06-29 01:58:28 +0900158struct piix_host_priv {
159 const int *map;
Tejun Heoc7290722008-01-18 18:36:30 +0900160 void __iomem *sidpr;
Tejun Heod96715c2006-06-29 01:58:28 +0900161};
162
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400163static int piix_init_one(struct pci_dev *pdev,
164 const struct pci_device_id *ent);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400165static void piix_pata_error_handler(struct ata_port *ap);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400166static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
167static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
168static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
Alan Coxeb4a2c72007-04-11 00:04:20 +0100169static int ich_pata_cable_detect(struct ata_port *ap);
Tejun Heo25f98132008-01-07 19:38:53 +0900170static u8 piix_vmw_bmdma_status(struct ata_port *ap);
Tejun Heoc7290722008-01-18 18:36:30 +0900171static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val);
172static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val);
173static void piix_sidpr_error_handler(struct ata_port *ap);
Tejun Heob8b275e2007-07-10 15:55:43 +0900174#ifdef CONFIG_PM
175static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
176static int piix_pci_device_resume(struct pci_dev *pdev);
177#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700178
179static unsigned int in_module_init = 1;
180
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500181static const struct pci_device_id piix_pci_tbl[] = {
Aland2cdfc02007-01-10 17:13:38 +0000182 /* Intel PIIX3 for the 430HX etc */
183 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
Tejun Heo25f98132008-01-07 19:38:53 +0900184 /* VMware ICH4 */
185 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400186 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
187 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
188 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400189 /* Intel PIIX4 */
190 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel PIIX4 */
192 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel PIIX */
194 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 /* Intel ICH (i810, i815, i840) UDMA 66*/
196 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
197 /* Intel ICH0 : UDMA 33*/
198 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
199 /* Intel ICH2M */
200 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
202 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH3M */
204 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH3 (E7500/1) UDMA 100 */
206 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
208 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* Intel ICH5 */
Christian Lamparter2eb829e2007-08-10 13:59:51 -0700211 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400212 /* C-ICH (i810E2) */
213 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik85cd7252006-08-31 00:03:49 -0400214 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400215 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ICH6 (and 6) (i915) UDMA 100 */
217 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 /* ICH7/7-R (i945, i975) UDMA 100*/
Christian Lamparter2eb829e2007-08-10 13:59:51 -0700219 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400220 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Christian Lamparterc1e6f282007-07-03 10:19:20 -0400221 /* ICH8 Mobile PATA Controller */
222 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223
224 /* NOTE: The following PCI ids must be kept in sync with the
225 * list in drivers/pci/quirks.c.
226 */
227
Tejun Heo1d076e52006-03-01 01:25:39 +0900228 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900230 /* 82801EB (ICH5) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900232 /* 6300ESB (ICH5 variant with broken PCS present bits) */
Tejun Heo5e56a372006-11-10 18:08:10 +0900233 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900234 /* 6300ESB pretending RAID */
Tejun Heo5e56a372006-11-10 18:08:10 +0900235 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900236 /* 82801FB/FW (ICH6/ICH6W) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
Tejun Heo1d076e52006-03-01 01:25:39 +0900238 /* 82801FR/FRW (ICH6R/ICH6RW) */
Jeff Garzik1c24a412005-11-14 18:20:23 -0500239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
Tejun Heo1d076e52006-03-01 01:25:39 +0900240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
241 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
242 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
Jeff Garzik1c24a412005-11-14 18:20:23 -0500243 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
Tejun Heo1d076e52006-03-01 01:25:39 +0900244 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
Tejun Heoc6446a42006-10-09 13:23:58 +0900245 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
Jason Gastonf98b6572006-12-07 08:57:32 -0800246 /* Enterprise Southbridge 2 (631xESB/632xESB) */
Jeff Garzik1c24a412005-11-14 18:20:23 -0500247 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
Jason Gastonf98b6572006-12-07 08:57:32 -0800248 /* SATA Controller 1 IDE (ICH8) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400249 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
Jason Gastonf98b6572006-12-07 08:57:32 -0800250 /* SATA Controller 2 IDE (ICH8) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900251 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800252 /* Mobile SATA Controller IDE (ICH8M) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400253 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900254 /* Mobile SATA Controller IDE (ICH8M), Apple */
255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
Jason Gastonf98b6572006-12-07 08:57:32 -0800256 /* SATA Controller IDE (ICH9) */
257 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
258 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900259 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800260 /* SATA Controller IDE (ICH9) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900261 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800262 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900263 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800264 /* SATA Controller IDE (ICH9M) */
Tejun Heo00242ec2007-11-19 11:24:25 +0900265 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Jason Gastonf98b6572006-12-07 08:57:32 -0800266 /* SATA Controller IDE (ICH9M) */
267 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700268 /* SATA Controller IDE (Tolapai) */
269 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
Jason Gastonbf7f22b2008-01-28 17:36:45 -0800270 /* SATA Controller IDE (ICH10) */
271 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
272 /* SATA Controller IDE (ICH10) */
273 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (ICH10) */
275 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
276 /* SATA Controller IDE (ICH10) */
277 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278
279 { } /* terminate list */
280};
281
282static struct pci_driver piix_pci_driver = {
283 .name = DRV_NAME,
284 .id_table = piix_pci_tbl,
285 .probe = piix_init_one,
286 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900287#ifdef CONFIG_PM
Tejun Heob8b275e2007-07-10 15:55:43 +0900288 .suspend = piix_pci_device_suspend,
289 .resume = piix_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900290#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291};
292
Jeff Garzik193515d2005-11-07 00:59:37 -0500293static struct scsi_host_template piix_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 .module = THIS_MODULE,
295 .name = DRV_NAME,
296 .ioctl = ata_scsi_ioctl,
297 .queuecommand = ata_scsi_queuecmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 .can_queue = ATA_DEF_QUEUE,
299 .this_id = ATA_SHT_THIS_ID,
300 .sg_tablesize = LIBATA_MAX_PRD,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
302 .emulated = ATA_SHT_EMULATED,
303 .use_clustering = ATA_SHT_USE_CLUSTERING,
304 .proc_name = DRV_NAME,
305 .dma_boundary = ATA_DMA_BOUNDARY,
306 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900307 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309};
310
Jeff Garzik057ace52005-10-22 14:27:05 -0400311static const struct ata_port_operations piix_pata_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 .set_piomode = piix_set_piomode,
313 .set_dmamode = piix_set_dmamode,
Albert Lee89bad582006-05-26 13:49:18 +0800314 .mode_filter = ata_pci_default_filter,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315
316 .tf_load = ata_tf_load,
317 .tf_read = ata_tf_read,
318 .check_status = ata_check_status,
319 .exec_command = ata_exec_command,
320 .dev_select = ata_std_dev_select,
321
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322 .bmdma_setup = ata_bmdma_setup,
323 .bmdma_start = ata_bmdma_start,
324 .bmdma_stop = ata_bmdma_stop,
325 .bmdma_status = ata_bmdma_status,
326 .qc_prep = ata_qc_prep,
327 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900328 .data_xfer = ata_data_xfer,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329
Tejun Heo3f037db2006-05-15 20:58:25 +0900330 .freeze = ata_bmdma_freeze,
331 .thaw = ata_bmdma_thaw,
Tejun Heoccc46722006-05-31 18:28:14 +0900332 .error_handler = piix_pata_error_handler,
Tejun Heo3f037db2006-05-15 20:58:25 +0900333 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Alan Coxeb4a2c72007-04-11 00:04:20 +0100334 .cable_detect = ata_cable_40wire,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900337 .irq_on = ata_irq_on,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
339 .port_start = ata_port_start,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340};
341
Jeff Garzik669a5db2006-08-29 18:12:40 -0400342static const struct ata_port_operations ich_pata_ops = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400343 .set_piomode = piix_set_piomode,
344 .set_dmamode = ich_set_dmamode,
345 .mode_filter = ata_pci_default_filter,
346
347 .tf_load = ata_tf_load,
348 .tf_read = ata_tf_read,
349 .check_status = ata_check_status,
350 .exec_command = ata_exec_command,
351 .dev_select = ata_std_dev_select,
352
353 .bmdma_setup = ata_bmdma_setup,
354 .bmdma_start = ata_bmdma_start,
355 .bmdma_stop = ata_bmdma_stop,
356 .bmdma_status = ata_bmdma_status,
357 .qc_prep = ata_qc_prep,
358 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900359 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400360
361 .freeze = ata_bmdma_freeze,
362 .thaw = ata_bmdma_thaw,
Alan Coxeb4a2c72007-04-11 00:04:20 +0100363 .error_handler = piix_pata_error_handler,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400364 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Alan Coxeb4a2c72007-04-11 00:04:20 +0100365 .cable_detect = ich_pata_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400366
Jeff Garzik669a5db2006-08-29 18:12:40 -0400367 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900368 .irq_on = ata_irq_on,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400369
370 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400371};
372
Jeff Garzik057ace52005-10-22 14:27:05 -0400373static const struct ata_port_operations piix_sata_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 .tf_load = ata_tf_load,
375 .tf_read = ata_tf_read,
376 .check_status = ata_check_status,
377 .exec_command = ata_exec_command,
378 .dev_select = ata_std_dev_select,
379
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 .bmdma_setup = ata_bmdma_setup,
381 .bmdma_start = ata_bmdma_start,
382 .bmdma_stop = ata_bmdma_stop,
383 .bmdma_status = ata_bmdma_status,
384 .qc_prep = ata_qc_prep,
385 .qc_issue = ata_qc_issue_prot,
Tejun Heo0d5ff562007-02-01 15:06:36 +0900386 .data_xfer = ata_data_xfer,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387
Tejun Heo3f037db2006-05-15 20:58:25 +0900388 .freeze = ata_bmdma_freeze,
389 .thaw = ata_bmdma_thaw,
Alan Cox2f91d812007-05-21 15:15:51 +0100390 .error_handler = ata_bmdma_error_handler,
Tejun Heo3f037db2006-05-15 20:58:25 +0900391 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900394 .irq_on = ata_irq_on,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395
396 .port_start = ata_port_start,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397};
398
Tejun Heo25f98132008-01-07 19:38:53 +0900399static const struct ata_port_operations piix_vmw_ops = {
400 .set_piomode = piix_set_piomode,
401 .set_dmamode = piix_set_dmamode,
402 .mode_filter = ata_pci_default_filter,
403
404 .tf_load = ata_tf_load,
405 .tf_read = ata_tf_read,
406 .check_status = ata_check_status,
407 .exec_command = ata_exec_command,
408 .dev_select = ata_std_dev_select,
409
410 .bmdma_setup = ata_bmdma_setup,
411 .bmdma_start = ata_bmdma_start,
412 .bmdma_stop = ata_bmdma_stop,
413 .bmdma_status = piix_vmw_bmdma_status,
414 .qc_prep = ata_qc_prep,
415 .qc_issue = ata_qc_issue_prot,
416 .data_xfer = ata_data_xfer,
417
418 .freeze = ata_bmdma_freeze,
419 .thaw = ata_bmdma_thaw,
420 .error_handler = piix_pata_error_handler,
421 .post_internal_cmd = ata_bmdma_post_internal_cmd,
422 .cable_detect = ata_cable_40wire,
423
424 .irq_handler = ata_interrupt,
425 .irq_clear = ata_bmdma_irq_clear,
426 .irq_on = ata_irq_on,
427
428 .port_start = ata_port_start,
429};
430
Tejun Heoc7290722008-01-18 18:36:30 +0900431static const struct ata_port_operations piix_sidpr_sata_ops = {
432 .tf_load = ata_tf_load,
433 .tf_read = ata_tf_read,
434 .check_status = ata_check_status,
435 .exec_command = ata_exec_command,
436 .dev_select = ata_std_dev_select,
437
438 .bmdma_setup = ata_bmdma_setup,
439 .bmdma_start = ata_bmdma_start,
440 .bmdma_stop = ata_bmdma_stop,
441 .bmdma_status = ata_bmdma_status,
442 .qc_prep = ata_qc_prep,
443 .qc_issue = ata_qc_issue_prot,
444 .data_xfer = ata_data_xfer,
445
446 .scr_read = piix_sidpr_scr_read,
447 .scr_write = piix_sidpr_scr_write,
448
449 .freeze = ata_bmdma_freeze,
450 .thaw = ata_bmdma_thaw,
451 .error_handler = piix_sidpr_error_handler,
452 .post_internal_cmd = ata_bmdma_post_internal_cmd,
453
454 .irq_clear = ata_bmdma_irq_clear,
455 .irq_on = ata_irq_on,
456
457 .port_start = ata_port_start,
458};
459
Tejun Heod96715c2006-06-29 01:58:28 +0900460static const struct piix_map_db ich5_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900461 .mask = 0x7,
Jeff Garzikea35d292006-07-11 11:48:50 -0400462 .port_enable = 0x3,
Tejun Heod33f58b2006-03-01 01:25:39 +0900463 .map = {
464 /* PM PS SM SS MAP */
465 { P0, NA, P1, NA }, /* 000b */
466 { P1, NA, P0, NA }, /* 001b */
467 { RV, RV, RV, RV },
468 { RV, RV, RV, RV },
469 { P0, P1, IDE, IDE }, /* 100b */
470 { P1, P0, IDE, IDE }, /* 101b */
471 { IDE, IDE, P0, P1 }, /* 110b */
472 { IDE, IDE, P1, P0 }, /* 111b */
473 },
474};
475
Tejun Heod96715c2006-06-29 01:58:28 +0900476static const struct piix_map_db ich6_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900477 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400478 .port_enable = 0xf,
Tejun Heod33f58b2006-03-01 01:25:39 +0900479 .map = {
480 /* PM PS SM SS MAP */
Tejun Heo79ea24e2006-03-31 20:01:50 +0900481 { P0, P2, P1, P3 }, /* 00b */
Tejun Heod33f58b2006-03-01 01:25:39 +0900482 { IDE, IDE, P1, P3 }, /* 01b */
483 { P0, P2, IDE, IDE }, /* 10b */
484 { RV, RV, RV, RV },
485 },
486};
487
Tejun Heod96715c2006-06-29 01:58:28 +0900488static const struct piix_map_db ich6m_map_db = {
Tejun Heod33f58b2006-03-01 01:25:39 +0900489 .mask = 0x3,
Jeff Garzikea35d292006-07-11 11:48:50 -0400490 .port_enable = 0x5,
Tejun Heo67083742006-09-11 06:29:03 +0900491
492 /* Map 01b isn't specified in the doc but some notebooks use
Tejun Heoc6446a42006-10-09 13:23:58 +0900493 * it anyway. MAP 01b have been spotted on both ICH6M and
494 * ICH7M.
Tejun Heo67083742006-09-11 06:29:03 +0900495 */
496 .map = {
497 /* PM PS SM SS MAP */
Tejun Heoe04b3b92007-07-10 17:58:21 +0900498 { P0, P2, NA, NA }, /* 00b */
Tejun Heo67083742006-09-11 06:29:03 +0900499 { IDE, IDE, P1, P3 }, /* 01b */
500 { P0, P2, IDE, IDE }, /* 10b */
501 { RV, RV, RV, RV },
502 },
503};
504
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400505static const struct piix_map_db ich8_map_db = {
506 .mask = 0x3,
Tejun Heoa0ce9ac2007-11-19 12:06:37 +0900507 .port_enable = 0xf,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400508 .map = {
509 /* PM PS SM SS MAP */
Kristen Carlson Accardi158f30c82006-10-19 13:27:39 -0700510 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400511 { RV, RV, RV, RV },
Tejun Heoac2b0432007-08-07 02:43:27 +0900512 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400513 { RV, RV, RV, RV },
514 },
515};
516
Tejun Heo00242ec2007-11-19 11:24:25 +0900517static const struct piix_map_db ich8_2port_map_db = {
Jason Gastone2d352a2007-09-07 17:21:03 -0700518 .mask = 0x3,
519 .port_enable = 0x3,
520 .map = {
521 /* PM PS SM SS MAP */
522 { P0, NA, P1, NA }, /* 00b */
523 { RV, RV, RV, RV }, /* 01b */
524 { RV, RV, RV, RV }, /* 10b */
525 { RV, RV, RV, RV },
526 },
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700527};
528
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900529static const struct piix_map_db ich8m_apple_map_db = {
530 .mask = 0x3,
531 .port_enable = 0x1,
532 .map = {
533 /* PM PS SM SS MAP */
534 { P0, NA, NA, NA }, /* 00b */
535 { RV, RV, RV, RV },
536 { P0, P2, IDE, IDE }, /* 10b */
537 { RV, RV, RV, RV },
538 },
539};
540
Tejun Heo00242ec2007-11-19 11:24:25 +0900541static const struct piix_map_db tolapai_map_db = {
Jason Gaston8f73a682007-10-11 16:05:15 -0700542 .mask = 0x3,
543 .port_enable = 0x3,
544 .map = {
545 /* PM PS SM SS MAP */
546 { P0, NA, P1, NA }, /* 00b */
547 { RV, RV, RV, RV }, /* 01b */
548 { RV, RV, RV, RV }, /* 10b */
549 { RV, RV, RV, RV },
550 },
551};
552
Tejun Heod96715c2006-06-29 01:58:28 +0900553static const struct piix_map_db *piix_map_db_table[] = {
554 [ich5_sata] = &ich5_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900555 [ich6_sata] = &ich6_map_db,
556 [ich6_sata_ahci] = &ich6_map_db,
557 [ich6m_sata_ahci] = &ich6m_map_db,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400558 [ich8_sata_ahci] = &ich8_map_db,
Tejun Heo00242ec2007-11-19 11:24:25 +0900559 [ich8_2port_sata] = &ich8_2port_map_db,
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900560 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700561 [tolapai_sata_ahci] = &tolapai_map_db,
Tejun Heod96715c2006-06-29 01:58:28 +0900562};
563
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564static struct ata_port_info piix_port_info[] = {
Tejun Heo00242ec2007-11-19 11:24:25 +0900565 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
566 {
Tejun Heo00242ec2007-11-19 11:24:25 +0900567 .flags = PIIX_PATA_FLAGS,
568 .pio_mask = 0x1f, /* pio0-4 */
569 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
570 .port_ops = &piix_pata_ops,
571 },
572
Jeff Garzikec300d92007-09-01 07:17:36 -0400573 [piix_pata_33] = /* PIIX4 at 33MHz */
Tejun Heo1d076e52006-03-01 01:25:39 +0900574 {
Tejun Heob3362f82006-11-10 18:08:10 +0900575 .flags = PIIX_PATA_FLAGS,
Tejun Heo1d076e52006-03-01 01:25:39 +0900576 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400577 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
Tejun Heo1d076e52006-03-01 01:25:39 +0900578 .udma_mask = ATA_UDMA_MASK_40C,
579 .port_ops = &piix_pata_ops,
580 },
581
Jeff Garzikec300d92007-09-01 07:17:36 -0400582 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583 {
Tejun Heob3362f82006-11-10 18:08:10 +0900584 .flags = PIIX_PATA_FLAGS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400585 .pio_mask = 0x1f, /* pio 0-4 */
586 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
587 .udma_mask = ATA_UDMA2, /* UDMA33 */
588 .port_ops = &ich_pata_ops,
589 },
Jeff Garzikec300d92007-09-01 07:17:36 -0400590
591 [ich_pata_66] = /* ICH controllers up to 66MHz */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400592 {
Tejun Heob3362f82006-11-10 18:08:10 +0900593 .flags = PIIX_PATA_FLAGS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400594 .pio_mask = 0x1f, /* pio 0-4 */
595 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
596 .udma_mask = ATA_UDMA4,
597 .port_ops = &ich_pata_ops,
598 },
Jeff Garzik85cd7252006-08-31 00:03:49 -0400599
Jeff Garzikec300d92007-09-01 07:17:36 -0400600 [ich_pata_100] =
Jeff Garzik669a5db2006-08-29 18:12:40 -0400601 {
Tejun Heob3362f82006-11-10 18:08:10 +0900602 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603 .pio_mask = 0x1f, /* pio0-4 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 .mwdma_mask = 0x06, /* mwdma1-2 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400605 .udma_mask = ATA_UDMA5, /* udma0-5 */
606 .port_ops = &ich_pata_ops,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607 },
608
Jeff Garzikec300d92007-09-01 07:17:36 -0400609 [ich5_sata] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610 {
Tejun Heo228c1592006-11-10 18:08:10 +0900611 .flags = PIIX_SATA_FLAGS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612 .pio_mask = 0x1f, /* pio0-4 */
613 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400614 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615 .port_ops = &piix_sata_ops,
616 },
617
Jeff Garzikec300d92007-09-01 07:17:36 -0400618 [ich6_sata] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619 {
Tejun Heo723159c2008-01-04 18:42:20 +0900620 .flags = PIIX_SATA_FLAGS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700621 .pio_mask = 0x1f, /* pio0-4 */
622 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400623 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624 .port_ops = &piix_sata_ops,
625 },
626
Jeff Garzikec300d92007-09-01 07:17:36 -0400627 [ich6_sata_ahci] =
Jason Gastonc368ca42005-04-16 15:24:44 -0700628 {
Tejun Heo723159c2008-01-04 18:42:20 +0900629 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
Jason Gastonc368ca42005-04-16 15:24:44 -0700630 .pio_mask = 0x1f, /* pio0-4 */
631 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400632 .udma_mask = ATA_UDMA6,
Jason Gastonc368ca42005-04-16 15:24:44 -0700633 .port_ops = &piix_sata_ops,
634 },
Tejun Heo1d076e52006-03-01 01:25:39 +0900635
Jeff Garzikec300d92007-09-01 07:17:36 -0400636 [ich6m_sata_ahci] =
Tejun Heo1d076e52006-03-01 01:25:39 +0900637 {
Tejun Heo723159c2008-01-04 18:42:20 +0900638 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
Tejun Heo1d076e52006-03-01 01:25:39 +0900639 .pio_mask = 0x1f, /* pio0-4 */
640 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400641 .udma_mask = ATA_UDMA6,
Tejun Heo1d076e52006-03-01 01:25:39 +0900642 .port_ops = &piix_sata_ops,
643 },
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400644
Jeff Garzikec300d92007-09-01 07:17:36 -0400645 [ich8_sata_ahci] =
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400646 {
Tejun Heoc7290722008-01-18 18:36:30 +0900647 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
648 PIIX_FLAG_SIDPR,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400649 .pio_mask = 0x1f, /* pio0-4 */
650 .mwdma_mask = 0x07, /* mwdma0-2 */
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400651 .udma_mask = ATA_UDMA6,
Jeff Garzik08f12ed2006-07-11 11:57:44 -0400652 .port_ops = &piix_sata_ops,
653 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400654
Tejun Heo00242ec2007-11-19 11:24:25 +0900655 [ich8_2port_sata] =
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700656 {
Tejun Heoc7290722008-01-18 18:36:30 +0900657 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
658 PIIX_FLAG_SIDPR,
Jason Gastonc5cf0ff2007-08-30 21:36:56 -0700659 .pio_mask = 0x1f, /* pio0-4 */
660 .mwdma_mask = 0x07, /* mwdma0-2 */
661 .udma_mask = ATA_UDMA6,
662 .port_ops = &piix_sata_ops,
663 },
Jason Gaston8f73a682007-10-11 16:05:15 -0700664
Tejun Heo00242ec2007-11-19 11:24:25 +0900665 [tolapai_sata_ahci] =
Jason Gaston8f73a682007-10-11 16:05:15 -0700666 {
Tejun Heo723159c2008-01-04 18:42:20 +0900667 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
Jason Gaston8f73a682007-10-11 16:05:15 -0700668 .pio_mask = 0x1f, /* pio0-4 */
669 .mwdma_mask = 0x07, /* mwdma0-2 */
670 .udma_mask = ATA_UDMA6,
671 .port_ops = &piix_sata_ops,
672 },
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900673
674 [ich8m_apple_sata_ahci] =
675 {
Tejun Heoc7290722008-01-18 18:36:30 +0900676 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
677 PIIX_FLAG_SIDPR,
Thomas Rohwer8d8ef2f2007-11-19 11:54:24 +0900678 .pio_mask = 0x1f, /* pio0-4 */
679 .mwdma_mask = 0x07, /* mwdma0-2 */
680 .udma_mask = ATA_UDMA6,
681 .port_ops = &piix_sata_ops,
682 },
683
Tejun Heo25f98132008-01-07 19:38:53 +0900684 [piix_pata_vmw] =
685 {
686 .sht = &piix_sht,
687 .flags = PIIX_PATA_FLAGS,
688 .pio_mask = 0x1f, /* pio0-4 */
689 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
690 .udma_mask = ATA_UDMA_MASK_40C,
691 .port_ops = &piix_vmw_ops,
692 },
693
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694};
695
696static struct pci_bits piix_enable_bits[] = {
697 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
698 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
699};
700
701MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
702MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
703MODULE_LICENSE("GPL");
704MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
705MODULE_VERSION(DRV_VERSION);
706
Alan Coxfc085152006-10-10 14:28:11 -0700707struct ich_laptop {
708 u16 device;
709 u16 subvendor;
710 u16 subdevice;
711};
712
713/*
714 * List of laptops that use short cables rather than 80 wire
715 */
716
717static const struct ich_laptop ich_laptop[] = {
718 /* devid, subvendor, subdev */
719 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
Alan Cox2655e2c2007-11-05 22:51:09 +0000720 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
J Jbabfb682007-01-09 02:26:30 +0900721 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
Robin H\. Johnson12340102007-03-28 18:02:07 -0700722 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
Jeff Garzik54174db2007-09-29 04:01:43 -0400723 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
Tejun Heob33620f2007-05-22 11:34:22 +0200724 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
Alan Coxfc085152006-10-10 14:28:11 -0700725 /* end marker */
726 { 0, }
727};
728
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729/**
Alan Coxeb4a2c72007-04-11 00:04:20 +0100730 * ich_pata_cable_detect - Probe host controller cable detect info
Linus Torvalds1da177e2005-04-16 15:20:36 -0700731 * @ap: Port for which cable detect info is desired
732 *
733 * Read 80c cable indicator from ATA PCI device's PCI config
734 * register. This register is normally set by firmware (BIOS).
735 *
736 * LOCKING:
737 * None (inherited from caller).
738 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400739
Alan Coxeb4a2c72007-04-11 00:04:20 +0100740static int ich_pata_cable_detect(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700741{
Jeff Garzikcca39742006-08-24 03:19:22 -0400742 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan Coxfc085152006-10-10 14:28:11 -0700743 const struct ich_laptop *lap = &ich_laptop[0];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744 u8 tmp, mask;
745
Alan Coxfc085152006-10-10 14:28:11 -0700746 /* Check for specials - Acer Aspire 5602WLMi */
747 while (lap->device) {
748 if (lap->device == pdev->device &&
749 lap->subvendor == pdev->subsystem_vendor &&
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400750 lap->subdevice == pdev->subsystem_device)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100751 return ATA_CBL_PATA40_SHORT;
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400752
Alan Coxfc085152006-10-10 14:28:11 -0700753 lap++;
754 }
755
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756 /* check BIOS cable detect results */
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900757 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
759 if ((tmp & mask) == 0)
Alan Coxeb4a2c72007-04-11 00:04:20 +0100760 return ATA_CBL_PATA40;
761 return ATA_CBL_PATA80;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762}
763
764/**
Tejun Heoccc46722006-05-31 18:28:14 +0900765 * piix_pata_prereset - prereset for PATA host controller
Tejun Heocc0680a2007-08-06 18:36:23 +0900766 * @link: Target link
Tejun Heod4b2bab2007-02-02 16:50:52 +0900767 * @deadline: deadline jiffies for the operation
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 * LOCKING:
770 * None (inherited from caller).
771 */
Tejun Heocc0680a2007-08-06 18:36:23 +0900772static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773{
Tejun Heocc0680a2007-08-06 18:36:23 +0900774 struct ata_port *ap = link->ap;
Jeff Garzikcca39742006-08-24 03:19:22 -0400775 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776
Alan Coxc9619222006-09-26 17:53:38 +0100777 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
778 return -ENOENT;
Tejun Heocc0680a2007-08-06 18:36:23 +0900779 return ata_std_prereset(link, deadline);
Tejun Heoccc46722006-05-31 18:28:14 +0900780}
781
782static void piix_pata_error_handler(struct ata_port *ap)
783{
784 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
785 ata_std_postreset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700786}
787
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788/**
789 * piix_set_piomode - Initialize host controller PATA PIO timings
790 * @ap: Port whose timings we are configuring
791 * @adev: um
Linus Torvalds1da177e2005-04-16 15:20:36 -0700792 *
793 * Set PIO mode for device, in host controller PCI config space.
794 *
795 * LOCKING:
796 * None (inherited from caller).
797 */
798
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400799static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800{
801 unsigned int pio = adev->pio_mode - XFER_PIO_0;
Jeff Garzikcca39742006-08-24 03:19:22 -0400802 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803 unsigned int is_slave = (adev->devno != 0);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900804 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805 unsigned int slave_port = 0x44;
806 u16 master_data;
807 u8 slave_data;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400808 u8 udma_enable;
809 int control = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400810
Jeff Garzik669a5db2006-08-29 18:12:40 -0400811 /*
812 * See Intel Document 298600-004 for the timing programing rules
813 * for ICH controllers.
814 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815
816 static const /* ISP RTC */
817 u8 timings[][2] = { { 0, 0 },
818 { 0, 0 },
819 { 1, 0 },
820 { 2, 1 },
821 { 2, 3 }, };
822
Jeff Garzik669a5db2006-08-29 18:12:40 -0400823 if (pio >= 2)
824 control |= 1; /* TIME1 enable */
825 if (ata_pio_need_iordy(adev))
826 control |= 2; /* IE enable */
827
Jeff Garzik85cd7252006-08-31 00:03:49 -0400828 /* Intel specifies that the PPE functionality is for disk only */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400829 if (adev->class == ATA_DEV_ATA)
830 control |= 4; /* PPE enable */
831
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200832 /* PIO configuration clears DTE unconditionally. It will be
833 * programmed in set_dmamode which is guaranteed to be called
834 * after set_piomode if any DMA mode is available.
835 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836 pci_read_config_word(dev, master_port, &master_data);
837 if (is_slave) {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200838 /* clear TIME1|IE1|PPE1|DTE1 */
839 master_data &= 0xff0f;
Joe Perches1967b7f2008-02-03 17:08:11 +0200840 /* Enable SITRE (separate slave timing register) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841 master_data |= 0x4000;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400842 /* enable PPE1, IE1 and TIME1 as needed */
843 master_data |= (control << 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844 pci_read_config_byte(dev, slave_port, &slave_data);
Tejun Heo2a88d1a2006-08-10 16:59:16 +0900845 slave_data &= (ap->port_no ? 0x0f : 0xf0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400846 /* Load the timing nibble for this slave */
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200847 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
848 << (ap->port_no ? 4 : 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849 } else {
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200850 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
851 master_data &= 0xccf0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400852 /* Enable PPE, IE and TIME as appropriate */
853 master_data |= control;
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200854 /* load ISP and RCT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700855 master_data |=
856 (timings[pio][0] << 12) |
857 (timings[pio][1] << 8);
858 }
859 pci_write_config_word(dev, master_port, master_data);
860 if (is_slave)
861 pci_write_config_byte(dev, slave_port, slave_data);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400862
863 /* Ensure the UDMA bit is off - it will be turned back on if
864 UDMA is selected */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400865
Jeff Garzik669a5db2006-08-29 18:12:40 -0400866 if (ap->udma_mask) {
867 pci_read_config_byte(dev, 0x48, &udma_enable);
868 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
869 pci_write_config_byte(dev, 0x48, udma_enable);
870 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871}
872
873/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400874 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875 * @ap: Port whose timings we are configuring
Jeff Garzik669a5db2006-08-29 18:12:40 -0400876 * @adev: Drive in question
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877 * @udma: udma mode, 0 - 6
Hennec32a8fd2006-09-25 22:00:46 +0200878 * @isich: set if the chip is an ICH device
Linus Torvalds1da177e2005-04-16 15:20:36 -0700879 *
880 * Set UDMA mode for device, in host controller PCI config space.
881 *
882 * LOCKING:
883 * None (inherited from caller).
884 */
885
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400886static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700887{
Jeff Garzikcca39742006-08-24 03:19:22 -0400888 struct pci_dev *dev = to_pci_dev(ap->host->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400889 u8 master_port = ap->port_no ? 0x42 : 0x40;
890 u16 master_data;
891 u8 speed = adev->dma_mode;
892 int devid = adev->devno + 2 * ap->port_no;
Andrew Mortondedf61db2007-01-10 17:20:34 -0800893 u8 udma_enable = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400894
Jeff Garzik669a5db2006-08-29 18:12:40 -0400895 static const /* ISP RTC */
896 u8 timings[][2] = { { 0, 0 },
897 { 0, 0 },
898 { 1, 0 },
899 { 2, 1 },
900 { 2, 3 }, };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901
Jeff Garzik669a5db2006-08-29 18:12:40 -0400902 pci_read_config_word(dev, master_port, &master_data);
Aland2cdfc02007-01-10 17:13:38 +0000903 if (ap->udma_mask)
904 pci_read_config_byte(dev, 0x48, &udma_enable);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905
906 if (speed >= XFER_UDMA_0) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400907 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
908 u16 udma_timing;
909 u16 ideconf;
910 int u_clock, u_speed;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400911
Jeff Garzik669a5db2006-08-29 18:12:40 -0400912 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400913 * UDMA is handled by a combination of clock switching and
Jeff Garzik85cd7252006-08-31 00:03:49 -0400914 * selection of dividers
915 *
Jeff Garzik669a5db2006-08-29 18:12:40 -0400916 * Handy rule: Odd modes are UDMATIMx 01, even are 02
Jeff Garzik85cd7252006-08-31 00:03:49 -0400917 * except UDMA0 which is 00
Jeff Garzik669a5db2006-08-29 18:12:40 -0400918 */
919 u_speed = min(2 - (udma & 1), udma);
920 if (udma == 5)
921 u_clock = 0x1000; /* 100Mhz */
922 else if (udma > 2)
923 u_clock = 1; /* 66Mhz */
924 else
925 u_clock = 0; /* 33Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400926
Jeff Garzik669a5db2006-08-29 18:12:40 -0400927 udma_enable |= (1 << devid);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400928
Jeff Garzik669a5db2006-08-29 18:12:40 -0400929 /* Load the CT/RP selection */
930 pci_read_config_word(dev, 0x4A, &udma_timing);
931 udma_timing &= ~(3 << (4 * devid));
932 udma_timing |= u_speed << (4 * devid);
933 pci_write_config_word(dev, 0x4A, udma_timing);
934
Jeff Garzik85cd7252006-08-31 00:03:49 -0400935 if (isich) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400936 /* Select a 33/66/100Mhz clock */
937 pci_read_config_word(dev, 0x54, &ideconf);
938 ideconf &= ~(0x1001 << devid);
939 ideconf |= u_clock << devid;
940 /* For ICH or later we should set bit 10 for better
941 performance (WR_PingPong_En) */
942 pci_write_config_word(dev, 0x54, ideconf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944 } else {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400945 /*
946 * MWDMA is driven by the PIO timings. We must also enable
947 * IORDY unconditionally along with TIME1. PPE has already
948 * been set when the PIO timing was set.
949 */
950 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
951 unsigned int control;
952 u8 slave_data;
953 const unsigned int needed_pio[3] = {
954 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
955 };
956 int pio = needed_pio[mwdma] - XFER_PIO_0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400957
Jeff Garzik669a5db2006-08-29 18:12:40 -0400958 control = 3; /* IORDY|TIME1 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400959
Jeff Garzik669a5db2006-08-29 18:12:40 -0400960 /* If the drive MWDMA is faster than it can do PIO then
961 we must force PIO into PIO0 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400962
Jeff Garzik669a5db2006-08-29 18:12:40 -0400963 if (adev->pio_mode < needed_pio[mwdma])
964 /* Enable DMA timing only */
965 control |= 8; /* PIO cycles in PIO0 */
966
967 if (adev->devno) { /* Slave */
968 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
969 master_data |= control << 4;
970 pci_read_config_byte(dev, 0x44, &slave_data);
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200971 slave_data &= (ap->port_no ? 0x0f : 0xf0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400972 /* Load the matching timing */
973 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
974 pci_write_config_byte(dev, 0x44, slave_data);
975 } else { /* Master */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400976 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
Jeff Garzik669a5db2006-08-29 18:12:40 -0400977 and master timing bits */
978 master_data |= control;
979 master_data |=
980 (timings[pio][0] << 12) |
981 (timings[pio][1] << 8);
982 }
Tejun Heoa5bf5f52007-05-25 19:16:58 +0200983
984 if (ap->udma_mask) {
985 udma_enable &= ~(1 << devid);
986 pci_write_config_word(dev, master_port, master_data);
987 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400989 /* Don't scribble on 0x48 if the controller does not support UDMA */
990 if (ap->udma_mask)
991 pci_write_config_byte(dev, 0x48, udma_enable);
992}
993
994/**
995 * piix_set_dmamode - Initialize host controller PATA DMA timings
996 * @ap: Port whose timings we are configuring
997 * @adev: um
998 *
999 * Set MW/UDMA mode for device, in host controller PCI config space.
1000 *
1001 * LOCKING:
1002 * None (inherited from caller).
1003 */
1004
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001005static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -04001006{
1007 do_pata_set_dmamode(ap, adev, 0);
1008}
1009
1010/**
1011 * ich_set_dmamode - Initialize host controller PATA DMA timings
1012 * @ap: Port whose timings we are configuring
1013 * @adev: um
1014 *
1015 * Set MW/UDMA mode for device, in host controller PCI config space.
1016 *
1017 * LOCKING:
1018 * None (inherited from caller).
1019 */
1020
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001021static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
Jeff Garzik669a5db2006-08-29 18:12:40 -04001022{
1023 do_pata_set_dmamode(ap, adev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024}
1025
Tejun Heoc7290722008-01-18 18:36:30 +09001026/*
1027 * Serial ATA Index/Data Pair Superset Registers access
1028 *
1029 * Beginning from ICH8, there's a sane way to access SCRs using index
1030 * and data register pair located at BAR5. This creates an
1031 * interesting problem of mapping two SCRs to one port.
1032 *
1033 * Although they have separate SCRs, the master and slave aren't
1034 * independent enough to be treated as separate links - e.g. softreset
1035 * resets both. Also, there's no protocol defined for hard resetting
1036 * singled device sharing the virtual port (no defined way to acquire
1037 * device signature). This is worked around by merging the SCR values
1038 * into one sensible value and requesting follow-up SRST after
1039 * hardreset.
1040 *
1041 * SCR merging is perfomed in nibbles which is the unit contents in
1042 * SCRs are organized. If two values are equal, the value is used.
1043 * When they differ, merge table which lists precedence of possible
1044 * values is consulted and the first match or the last entry when
1045 * nothing matches is used. When there's no merge table for the
1046 * specific nibble, value from the first port is used.
1047 */
1048static const int piix_sidx_map[] = {
1049 [SCR_STATUS] = 0,
1050 [SCR_ERROR] = 2,
1051 [SCR_CONTROL] = 1,
1052};
1053
1054static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg)
1055{
1056 struct ata_port *ap = dev->link->ap;
1057 struct piix_host_priv *hpriv = ap->host->private_data;
1058
1059 iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg],
1060 hpriv->sidpr + PIIX_SIDPR_IDX);
1061}
1062
1063static int piix_sidpr_read(struct ata_device *dev, unsigned int reg)
1064{
1065 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
1066
1067 piix_sidpr_sel(dev, reg);
1068 return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
1069}
1070
1071static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val)
1072{
1073 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
1074
1075 piix_sidpr_sel(dev, reg);
1076 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1077}
1078
Adrian Bunk4a537a552008-01-29 00:10:19 +02001079static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
Tejun Heoc7290722008-01-18 18:36:30 +09001080{
1081 u32 val = 0;
1082 int i, mi;
1083
1084 for (i = 0, mi = 0; i < 32 / 4; i++) {
1085 u8 c0 = (val0 >> (i * 4)) & 0xf;
1086 u8 c1 = (val1 >> (i * 4)) & 0xf;
1087 u8 merged = c0;
1088 const int *cur;
1089
1090 /* if no merge preference, assume the first value */
1091 cur = merge_tbl[mi];
1092 if (!cur)
1093 goto done;
1094 mi++;
1095
1096 /* if two values equal, use it */
1097 if (c0 == c1)
1098 goto done;
1099
1100 /* choose the first match or the last from the merge table */
1101 while (*cur != -1) {
1102 if (c0 == *cur || c1 == *cur)
1103 break;
1104 cur++;
1105 }
1106 if (*cur == -1)
1107 cur--;
1108 merged = *cur;
1109 done:
1110 val |= merged << (i * 4);
1111 }
1112
1113 return val;
1114}
1115
1116static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val)
1117{
1118 const int * const sstatus_merge_tbl[] = {
1119 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
1120 /* SPD */ (const int []){ 2, 1, 0, -1 },
1121 /* IPM */ (const int []){ 6, 2, 1, 0, -1 },
1122 NULL,
1123 };
1124 const int * const scontrol_merge_tbl[] = {
1125 /* DET */ (const int []){ 1, 0, 4, 0, -1 },
1126 /* SPD */ (const int []){ 0, 2, 1, 0, -1 },
1127 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
1128 NULL,
1129 };
1130 u32 v0, v1;
1131
1132 if (reg >= ARRAY_SIZE(piix_sidx_map))
1133 return -EINVAL;
1134
1135 if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) {
1136 *val = piix_sidpr_read(&ap->link.device[0], reg);
1137 return 0;
1138 }
1139
1140 v0 = piix_sidpr_read(&ap->link.device[0], reg);
1141 v1 = piix_sidpr_read(&ap->link.device[1], reg);
1142
1143 switch (reg) {
1144 case SCR_STATUS:
1145 *val = piix_merge_scr(v0, v1, sstatus_merge_tbl);
1146 break;
1147 case SCR_ERROR:
1148 *val = v0 | v1;
1149 break;
1150 case SCR_CONTROL:
1151 *val = piix_merge_scr(v0, v1, scontrol_merge_tbl);
1152 break;
1153 }
1154
1155 return 0;
1156}
1157
1158static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val)
1159{
1160 if (reg >= ARRAY_SIZE(piix_sidx_map))
1161 return -EINVAL;
1162
1163 piix_sidpr_write(&ap->link.device[0], reg, val);
1164
1165 if (ap->flags & ATA_FLAG_SLAVE_POSS)
1166 piix_sidpr_write(&ap->link.device[1], reg, val);
1167
1168 return 0;
1169}
1170
1171static int piix_sidpr_hardreset(struct ata_link *link, unsigned int *class,
1172 unsigned long deadline)
1173{
1174 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1175 int rc;
1176
1177 /* do hardreset */
1178 rc = sata_link_hardreset(link, timing, deadline);
1179 if (rc) {
1180 ata_link_printk(link, KERN_ERR,
1181 "COMRESET failed (errno=%d)\n", rc);
1182 return rc;
1183 }
1184
1185 /* TODO: phy layer with polling, timeouts, etc. */
1186 if (ata_link_offline(link)) {
1187 *class = ATA_DEV_NONE;
1188 return 0;
1189 }
1190
1191 return -EAGAIN;
1192}
1193
1194static void piix_sidpr_error_handler(struct ata_port *ap)
1195{
1196 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1197 piix_sidpr_hardreset, ata_std_postreset);
1198}
1199
Tejun Heob8b275e2007-07-10 15:55:43 +09001200#ifdef CONFIG_PM
Tejun Heo8c3832e2007-07-27 14:53:28 +09001201static int piix_broken_suspend(void)
1202{
Jeff Garzik18552562007-10-03 15:15:40 -04001203 static const struct dmi_system_id sysids[] = {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001204 {
Tejun Heo4c74d4e2007-09-30 01:11:20 -07001205 .ident = "TECRA M3",
1206 .matches = {
1207 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1208 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1209 },
1210 },
1211 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001212 .ident = "TECRA M3",
1213 .matches = {
1214 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1215 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1216 },
1217 },
1218 {
Peter Schwenked1aa6902007-12-05 10:39:49 +09001219 .ident = "TECRA M4",
1220 .matches = {
1221 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1222 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1223 },
1224 },
1225 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001226 .ident = "TECRA M5",
1227 .matches = {
1228 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1229 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1230 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001231 },
Tejun Heo8c3832e2007-07-27 14:53:28 +09001232 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +10001233 .ident = "TECRA M6",
1234 .matches = {
1235 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1236 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1237 },
1238 },
1239 {
Tejun Heo5c08ea02007-08-14 19:56:04 +09001240 .ident = "TECRA M7",
1241 .matches = {
1242 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1243 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1244 },
1245 },
1246 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001247 .ident = "TECRA A8",
1248 .matches = {
1249 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1250 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1251 },
1252 },
1253 {
Peter Schwenkeffe188d2008-01-17 23:08:55 +10001254 .ident = "Satellite R20",
1255 .matches = {
1256 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1257 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1258 },
1259 },
1260 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001261 .ident = "Satellite R25",
1262 .matches = {
1263 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1264 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1265 },
1266 },
1267 {
Tejun Heo3cc0b9d2007-08-25 08:31:02 +09001268 .ident = "Satellite U200",
1269 .matches = {
1270 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1271 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1272 },
1273 },
1274 {
Peter Schwenke04d86d62007-11-30 15:28:29 +09001275 .ident = "Satellite U200",
1276 .matches = {
1277 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1278 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1279 },
1280 },
1281 {
Yann Chachkoff62320e22007-11-07 12:02:27 +09001282 .ident = "Satellite Pro U200",
1283 .matches = {
1284 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1285 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1286 },
1287 },
1288 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001289 .ident = "Satellite U205",
1290 .matches = {
1291 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1292 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1293 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001294 },
Tejun Heo8c3832e2007-07-27 14:53:28 +09001295 {
Tejun Heode753e52007-11-12 17:56:24 +09001296 .ident = "SATELLITE U205",
1297 .matches = {
1298 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1299 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1300 },
1301 },
1302 {
Tejun Heo8c3832e2007-07-27 14:53:28 +09001303 .ident = "Portege M500",
1304 .matches = {
1305 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1306 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1307 },
Tejun Heob8b275e2007-07-10 15:55:43 +09001308 },
Jeff Garzik7d051542007-09-01 06:48:52 -04001309
1310 { } /* terminate list */
Tejun Heo8c3832e2007-07-27 14:53:28 +09001311 };
Tejun Heo7abe79c2007-07-27 14:55:07 +09001312 static const char *oemstrs[] = {
1313 "Tecra M3,",
1314 };
1315 int i;
Tejun Heo8c3832e2007-07-27 14:53:28 +09001316
1317 if (dmi_check_system(sysids))
1318 return 1;
1319
Tejun Heo7abe79c2007-07-27 14:55:07 +09001320 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1321 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1322 return 1;
1323
Tejun Heo8c3832e2007-07-27 14:53:28 +09001324 return 0;
1325}
Tejun Heob8b275e2007-07-10 15:55:43 +09001326
1327static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1328{
1329 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1330 unsigned long flags;
1331 int rc = 0;
1332
1333 rc = ata_host_suspend(host, mesg);
1334 if (rc)
1335 return rc;
1336
1337 /* Some braindamaged ACPI suspend implementations expect the
1338 * controller to be awake on entry; otherwise, it burns cpu
1339 * cycles and power trying to do something to the sleeping
1340 * beauty.
1341 */
Tejun Heo8c3832e2007-07-27 14:53:28 +09001342 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
Tejun Heob8b275e2007-07-10 15:55:43 +09001343 pci_save_state(pdev);
1344
1345 /* mark its power state as "unknown", since we don't
1346 * know if e.g. the BIOS will change its device state
1347 * when we suspend.
1348 */
1349 if (pdev->current_state == PCI_D0)
1350 pdev->current_state = PCI_UNKNOWN;
1351
1352 /* tell resume that it's waking up from broken suspend */
1353 spin_lock_irqsave(&host->lock, flags);
1354 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1355 spin_unlock_irqrestore(&host->lock, flags);
1356 } else
1357 ata_pci_device_do_suspend(pdev, mesg);
1358
1359 return 0;
1360}
1361
1362static int piix_pci_device_resume(struct pci_dev *pdev)
1363{
1364 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1365 unsigned long flags;
1366 int rc;
1367
1368 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1369 spin_lock_irqsave(&host->lock, flags);
1370 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1371 spin_unlock_irqrestore(&host->lock, flags);
1372
1373 pci_set_power_state(pdev, PCI_D0);
1374 pci_restore_state(pdev);
1375
1376 /* PCI device wasn't disabled during suspend. Use
Tejun Heo0b62e132007-07-27 14:43:35 +09001377 * pci_reenable_device() to avoid affecting the enable
1378 * count.
Tejun Heob8b275e2007-07-10 15:55:43 +09001379 */
Tejun Heo0b62e132007-07-27 14:43:35 +09001380 rc = pci_reenable_device(pdev);
Tejun Heob8b275e2007-07-10 15:55:43 +09001381 if (rc)
1382 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1383 "device after resume (%d)\n", rc);
1384 } else
1385 rc = ata_pci_device_do_resume(pdev);
1386
1387 if (rc == 0)
1388 ata_host_resume(host);
1389
1390 return rc;
1391}
1392#endif
1393
Tejun Heo25f98132008-01-07 19:38:53 +09001394static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1395{
1396 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1397}
1398
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399#define AHCI_PCI_BAR 5
1400#define AHCI_GLOBAL_CTL 0x04
1401#define AHCI_ENABLE (1 << 31)
1402static int piix_disable_ahci(struct pci_dev *pdev)
1403{
Jeff Garzikea6ba102005-08-30 05:18:18 -04001404 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001405 u32 tmp;
1406 int rc = 0;
1407
1408 /* BUG: pci_enable_device has not yet been called. This
1409 * works because this device is usually set up by BIOS.
1410 */
1411
Jeff Garzik374b1872005-08-30 05:42:52 -04001412 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1413 !pci_resource_len(pdev, AHCI_PCI_BAR))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001414 return 0;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001415
Jeff Garzik374b1872005-08-30 05:42:52 -04001416 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417 if (!mmio)
1418 return -ENOMEM;
Greg Felix7b6dbd62005-07-28 15:54:15 -04001419
Alan Coxc47a6312007-11-19 14:28:28 +00001420 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421 if (tmp & AHCI_ENABLE) {
1422 tmp &= ~AHCI_ENABLE;
Alan Coxc47a6312007-11-19 14:28:28 +00001423 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424
Alan Coxc47a6312007-11-19 14:28:28 +00001425 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001426 if (tmp & AHCI_ENABLE)
1427 rc = -EIO;
1428 }
Greg Felix7b6dbd62005-07-28 15:54:15 -04001429
Jeff Garzik374b1872005-08-30 05:42:52 -04001430 pci_iounmap(pdev, mmio);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431 return rc;
1432}
1433
1434/**
Alan Coxc621b142005-12-08 19:22:28 +00001435 * piix_check_450nx_errata - Check for problem 450NX setup
Randy Dunlapc893a3a2006-01-28 13:15:32 -05001436 * @ata_dev: the PCI device to check
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001437 *
Alan Coxc621b142005-12-08 19:22:28 +00001438 * Check for the present of 450NX errata #19 and errata #25. If
1439 * they are found return an error code so we can turn off DMA
1440 */
1441
1442static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1443{
1444 struct pci_dev *pdev = NULL;
1445 u16 cfg;
Alan Coxc621b142005-12-08 19:22:28 +00001446 int no_piix_dma = 0;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001447
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001448 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
Alan Coxc621b142005-12-08 19:22:28 +00001449 /* Look for 450NX PXB. Check for problem configurations
1450 A PCI quirk checks bit 6 already */
Alan Coxc621b142005-12-08 19:22:28 +00001451 pci_read_config_word(pdev, 0x41, &cfg);
1452 /* Only on the original revision: IDE DMA can hang */
Auke Kok44c10132007-06-08 15:46:36 -07001453 if (pdev->revision == 0x00)
Alan Coxc621b142005-12-08 19:22:28 +00001454 no_piix_dma = 1;
1455 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
Auke Kok44c10132007-06-08 15:46:36 -07001456 else if (cfg & (1<<14) && pdev->revision < 5)
Alan Coxc621b142005-12-08 19:22:28 +00001457 no_piix_dma = 2;
1458 }
Alan Cox31a34fe2006-05-22 22:58:14 +01001459 if (no_piix_dma)
Alan Coxc621b142005-12-08 19:22:28 +00001460 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
Alan Cox31a34fe2006-05-22 22:58:14 +01001461 if (no_piix_dma == 2)
Alan Coxc621b142005-12-08 19:22:28 +00001462 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1463 return no_piix_dma;
Jeff Garzik2e9edbf2006-03-24 09:56:57 -05001464}
Alan Coxc621b142005-12-08 19:22:28 +00001465
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001466static void __devinit piix_init_pcs(struct ata_host *host,
Jeff Garzikea35d292006-07-11 11:48:50 -04001467 const struct piix_map_db *map_db)
1468{
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001469 struct pci_dev *pdev = to_pci_dev(host->dev);
Jeff Garzikea35d292006-07-11 11:48:50 -04001470 u16 pcs, new_pcs;
1471
1472 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1473
1474 new_pcs = pcs | map_db->port_enable;
1475
1476 if (new_pcs != pcs) {
1477 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1478 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1479 msleep(150);
1480 }
1481}
1482
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001483static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1484 struct ata_port_info *pinfo,
1485 const struct piix_map_db *map_db)
Tejun Heod33f58b2006-03-01 01:25:39 +09001486{
Al Virob4482a42007-10-14 19:35:40 +01001487 const int *map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001488 int i, invalid_map = 0;
1489 u8 map_value;
1490
1491 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1492
1493 map = map_db->map[map_value & map_db->mask];
1494
1495 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1496 for (i = 0; i < 4; i++) {
1497 switch (map[i]) {
1498 case RV:
1499 invalid_map = 1;
1500 printk(" XX");
1501 break;
1502
1503 case NA:
1504 printk(" --");
1505 break;
1506
1507 case IDE:
1508 WARN_ON((i & 1) || map[i + 1] != IDE);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001509 pinfo[i / 2] = piix_port_info[ich_pata_100];
Tejun Heod33f58b2006-03-01 01:25:39 +09001510 i++;
1511 printk(" IDE IDE");
1512 break;
1513
1514 default:
1515 printk(" P%d", map[i]);
1516 if (i & 1)
Jeff Garzikcca39742006-08-24 03:19:22 -04001517 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
Tejun Heod33f58b2006-03-01 01:25:39 +09001518 break;
1519 }
1520 }
1521 printk(" ]\n");
1522
1523 if (invalid_map)
1524 dev_printk(KERN_ERR, &pdev->dev,
1525 "invalid MAP value %u\n", map_value);
1526
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001527 return map;
Tejun Heod33f58b2006-03-01 01:25:39 +09001528}
1529
Tejun Heoc7290722008-01-18 18:36:30 +09001530static void __devinit piix_init_sidpr(struct ata_host *host)
1531{
1532 struct pci_dev *pdev = to_pci_dev(host->dev);
1533 struct piix_host_priv *hpriv = host->private_data;
1534 int i;
1535
1536 /* check for availability */
1537 for (i = 0; i < 4; i++)
1538 if (hpriv->map[i] == IDE)
1539 return;
1540
1541 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1542 return;
1543
1544 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1545 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1546 return;
1547
1548 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1549 return;
1550
1551 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1552 host->ports[0]->ops = &piix_sidpr_sata_ops;
1553 host->ports[1]->ops = &piix_sidpr_sata_ops;
1554}
1555
Tejun Heo43a98f02007-08-23 10:15:18 +09001556static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1557{
Jeff Garzik18552562007-10-03 15:15:40 -04001558 static const struct dmi_system_id sysids[] = {
Tejun Heo43a98f02007-08-23 10:15:18 +09001559 {
1560 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1561 * isn't used to boot the system which
1562 * disables the channel.
1563 */
1564 .ident = "M570U",
1565 .matches = {
1566 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1567 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1568 },
1569 },
Jeff Garzik7d051542007-09-01 06:48:52 -04001570
1571 { } /* terminate list */
Tejun Heo43a98f02007-08-23 10:15:18 +09001572 };
1573 u32 iocfg;
1574
1575 if (!dmi_check_system(sysids))
1576 return;
1577
1578 /* The datasheet says that bit 18 is NOOP but certain systems
1579 * seem to use it to disable a channel. Clear the bit on the
1580 * affected systems.
1581 */
1582 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1583 if (iocfg & (1 << 18)) {
1584 dev_printk(KERN_INFO, &pdev->dev,
1585 "applying IOCFG bit18 quirk\n");
1586 iocfg &= ~(1 << 18);
1587 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1588 }
1589}
1590
Alan Coxc621b142005-12-08 19:22:28 +00001591/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001592 * piix_init_one - Register PIIX ATA PCI device with kernel services
1593 * @pdev: PCI device to register
1594 * @ent: Entry in piix_pci_tbl matching with @pdev
1595 *
1596 * Called from kernel PCI layer. We probe for combined mode (sigh),
1597 * and then hand over control to libata, for it to do the rest.
1598 *
1599 * LOCKING:
1600 * Inherited from PCI layer (may sleep).
1601 *
1602 * RETURNS:
1603 * Zero on success, or -ERRNO value.
1604 */
1605
Adrian Bunkbc5468f2008-01-30 22:02:02 +02001606static int __devinit piix_init_one(struct pci_dev *pdev,
1607 const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608{
1609 static int printed_version;
Tejun Heo24dc5f32007-01-20 16:00:28 +09001610 struct device *dev = &pdev->dev;
Tejun Heod33f58b2006-03-01 01:25:39 +09001611 struct ata_port_info port_info[2];
Tejun Heo1626aeb2007-05-04 12:43:58 +02001612 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
Jeff Garzikcca39742006-08-24 03:19:22 -04001613 unsigned long port_flags;
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001614 struct ata_host *host;
1615 struct piix_host_priv *hpriv;
1616 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001617
1618 if (!printed_version++)
Jeff Garzik6248e642005-10-30 06:42:18 -05001619 dev_printk(KERN_DEBUG, &pdev->dev,
1620 "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621
1622 /* no hotplugging support (FIXME) */
1623 if (!in_module_init)
1624 return -ENODEV;
1625
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001626 port_info[0] = piix_port_info[ent->driver_data];
1627 port_info[1] = piix_port_info[ent->driver_data];
1628
1629 port_flags = port_info[0].flags;
1630
1631 /* enable device and prepare host */
1632 rc = pcim_enable_device(pdev);
1633 if (rc)
1634 return rc;
1635
1636 /* SATA map init can change port_info, do it before prepping host */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001637 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
Tejun Heod96715c2006-06-29 01:58:28 +09001638 if (!hpriv)
1639 return -ENOMEM;
1640
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001641 if (port_flags & ATA_FLAG_SATA)
1642 hpriv->map = piix_init_sata_map(pdev, port_info,
1643 piix_map_db_table[ent->driver_data]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001644
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001645 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
1646 if (rc)
1647 return rc;
1648 host->private_data = hpriv;
Tejun Heoff0fc142005-12-18 17:17:07 +09001649
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001650 /* initialize controller */
Jeff Garzikcca39742006-08-24 03:19:22 -04001651 if (port_flags & PIIX_FLAG_AHCI) {
Jeff Garzik8a60a072005-07-31 13:13:24 -04001652 u8 tmp;
1653 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1654 if (tmp == PIIX_AHCI_DEVICE) {
1655 int rc = piix_disable_ahci(pdev);
1656 if (rc)
1657 return rc;
1658 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001659 }
1660
Tejun Heoc7290722008-01-18 18:36:30 +09001661 if (port_flags & ATA_FLAG_SATA) {
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001662 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
Tejun Heoc7290722008-01-18 18:36:30 +09001663 piix_init_sidpr(host);
1664 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001665
Tejun Heo43a98f02007-08-23 10:15:18 +09001666 /* apply IOCFG bit18 quirk */
1667 piix_iocfg_bit18_quirk(pdev);
1668
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669 /* On ICH5, some BIOSen disable the interrupt using the
1670 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1671 * On ICH6, this bit has the same effect, but only when
1672 * MSI is disabled (and it is disabled, as we don't use
1673 * message-signalled interrupts currently).
1674 */
Jeff Garzikcca39742006-08-24 03:19:22 -04001675 if (port_flags & PIIX_FLAG_CHECKINTR)
Brett M Russa04ce0f2005-08-15 15:23:41 -04001676 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001677
Alan Coxc621b142005-12-08 19:22:28 +00001678 if (piix_check_450nx_errata(pdev)) {
1679 /* This writes into the master table but it does not
1680 really matter for this errata as we will apply it to
1681 all the PIIX devices on the board */
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001682 host->ports[0]->mwdma_mask = 0;
1683 host->ports[0]->udma_mask = 0;
1684 host->ports[1]->mwdma_mask = 0;
1685 host->ports[1]->udma_mask = 0;
Alan Coxc621b142005-12-08 19:22:28 +00001686 }
Tejun Heo8b09f0d2008-01-18 18:36:29 +09001687
1688 pci_set_master(pdev);
1689 return ata_pci_activate_sff_host(host, ata_interrupt, &piix_sht);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001690}
1691
Linus Torvalds1da177e2005-04-16 15:20:36 -07001692static int __init piix_init(void)
1693{
1694 int rc;
1695
Pavel Roskinb7887192006-08-10 18:13:18 +09001696 DPRINTK("pci_register_driver\n");
1697 rc = pci_register_driver(&piix_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001698 if (rc)
1699 return rc;
1700
1701 in_module_init = 0;
1702
1703 DPRINTK("done\n");
1704 return 0;
1705}
1706
Linus Torvalds1da177e2005-04-16 15:20:36 -07001707static void __exit piix_exit(void)
1708{
1709 pci_unregister_driver(&piix_pci_driver);
1710}
1711
1712module_init(piix_init);
1713module_exit(piix_exit);