Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2011 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Jesse Barnes <jbarnes@virtuousgeek.org> |
| 25 | * |
| 26 | * New plane/sprite handling. |
| 27 | * |
| 28 | * The older chips had a separate interface for programming plane related |
| 29 | * registers; newer ones are much simpler and we can use the new DRM plane |
| 30 | * support. |
| 31 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/drmP.h> |
| 33 | #include <drm/drm_crtc.h> |
| 34 | #include <drm/drm_fourcc.h> |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 35 | #include <drm/drm_rect.h> |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 36 | #include <drm/drm_atomic.h> |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 37 | #include <drm/drm_plane_helper.h> |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 38 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 39 | #include <drm/i915_drm.h> |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 40 | #include "i915_drv.h" |
| 41 | |
Ville Syrjälä | 6ca2aeb | 2014-10-20 19:47:53 +0300 | [diff] [blame] | 42 | static bool |
| 43 | format_is_yuv(uint32_t format) |
| 44 | { |
| 45 | switch (format) { |
| 46 | case DRM_FORMAT_YUYV: |
| 47 | case DRM_FORMAT_UYVY: |
| 48 | case DRM_FORMAT_VYUY: |
| 49 | case DRM_FORMAT_YVYU: |
| 50 | return true; |
| 51 | default: |
| 52 | return false; |
| 53 | } |
| 54 | } |
| 55 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 56 | static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs) |
| 57 | { |
| 58 | /* paranoia */ |
| 59 | if (!mode->crtc_htotal) |
| 60 | return 1; |
| 61 | |
| 62 | return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal); |
| 63 | } |
| 64 | |
Ander Conselvan de Oliveira | 26ff276 | 2014-10-28 15:10:12 +0200 | [diff] [blame] | 65 | /** |
| 66 | * intel_pipe_update_start() - start update of a set of display registers |
| 67 | * @crtc: the crtc of which the registers are going to be updated |
| 68 | * @start_vbl_count: vblank counter return pointer used for error checking |
| 69 | * |
| 70 | * Mark the start of an update to pipe registers that should be updated |
| 71 | * atomically regarding vblank. If the next vblank will happens within |
| 72 | * the next 100 us, this function waits until the vblank passes. |
| 73 | * |
| 74 | * After a successful call to this function, interrupts will be disabled |
| 75 | * until a subsequent call to intel_pipe_update_end(). That is done to |
| 76 | * avoid random delays. The value written to @start_vbl_count should be |
| 77 | * supplied to intel_pipe_update_end() for error checking. |
| 78 | * |
| 79 | * Return: true if the call was successful |
| 80 | */ |
Ander Conselvan de Oliveira | 9362c7c | 2014-10-28 15:10:14 +0200 | [diff] [blame] | 81 | bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 82 | { |
| 83 | struct drm_device *dev = crtc->base.dev; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 84 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 85 | enum pipe pipe = crtc->pipe; |
| 86 | long timeout = msecs_to_jiffies_timeout(1); |
| 87 | int scanline, min, max, vblank_start; |
Ville Syrjälä | 210871b | 2014-05-22 19:00:50 +0300 | [diff] [blame] | 88 | wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 89 | DEFINE_WAIT(wait); |
| 90 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 91 | vblank_start = mode->crtc_vblank_start; |
| 92 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 93 | vblank_start = DIV_ROUND_UP(vblank_start, 2); |
| 94 | |
| 95 | /* FIXME needs to be calibrated sensibly */ |
| 96 | min = vblank_start - usecs_to_scanlines(mode, 100); |
| 97 | max = vblank_start - 1; |
| 98 | |
| 99 | if (min <= 0 || max <= 0) |
| 100 | return false; |
| 101 | |
Daniel Vetter | 1e3feef | 2015-02-13 21:03:45 +0100 | [diff] [blame] | 102 | if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 103 | return false; |
| 104 | |
| 105 | local_irq_disable(); |
| 106 | |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 107 | trace_i915_pipe_update_start(crtc, min, max); |
| 108 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 109 | for (;;) { |
| 110 | /* |
| 111 | * prepare_to_wait() has a memory barrier, which guarantees |
| 112 | * other CPUs can see the task state update by the time we |
| 113 | * read the scanline. |
| 114 | */ |
Ville Syrjälä | 210871b | 2014-05-22 19:00:50 +0300 | [diff] [blame] | 115 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 116 | |
| 117 | scanline = intel_get_crtc_scanline(crtc); |
| 118 | if (scanline < min || scanline > max) |
| 119 | break; |
| 120 | |
| 121 | if (timeout <= 0) { |
| 122 | DRM_ERROR("Potential atomic update failure on pipe %c\n", |
| 123 | pipe_name(crtc->pipe)); |
| 124 | break; |
| 125 | } |
| 126 | |
| 127 | local_irq_enable(); |
| 128 | |
| 129 | timeout = schedule_timeout(timeout); |
| 130 | |
| 131 | local_irq_disable(); |
| 132 | } |
| 133 | |
Ville Syrjälä | 210871b | 2014-05-22 19:00:50 +0300 | [diff] [blame] | 134 | finish_wait(wq, &wait); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 135 | |
Daniel Vetter | 1e3feef | 2015-02-13 21:03:45 +0100 | [diff] [blame] | 136 | drm_crtc_vblank_put(&crtc->base); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 137 | |
| 138 | *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
| 139 | |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 140 | trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count); |
| 141 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 142 | return true; |
| 143 | } |
| 144 | |
Ander Conselvan de Oliveira | 26ff276 | 2014-10-28 15:10:12 +0200 | [diff] [blame] | 145 | /** |
| 146 | * intel_pipe_update_end() - end update of a set of display registers |
| 147 | * @crtc: the crtc of which the registers were updated |
| 148 | * @start_vbl_count: start vblank counter (used for error checking) |
| 149 | * |
| 150 | * Mark the end of an update started with intel_pipe_update_start(). This |
| 151 | * re-enables interrupts and verifies the update was actually completed |
| 152 | * before a vblank using the value of @start_vbl_count. |
| 153 | */ |
Ander Conselvan de Oliveira | 9362c7c | 2014-10-28 15:10:14 +0200 | [diff] [blame] | 154 | void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 155 | { |
| 156 | struct drm_device *dev = crtc->base.dev; |
| 157 | enum pipe pipe = crtc->pipe; |
| 158 | u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
| 159 | |
Ville Syrjälä | 25ef284 | 2014-04-29 13:35:48 +0300 | [diff] [blame] | 160 | trace_i915_pipe_update_end(crtc, end_vbl_count); |
| 161 | |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 162 | local_irq_enable(); |
| 163 | |
| 164 | if (start_vbl_count != end_vbl_count) |
| 165 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n", |
| 166 | pipe_name(pipe), start_vbl_count, end_vbl_count); |
| 167 | } |
| 168 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 169 | static void |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 170 | skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, |
| 171 | struct drm_framebuffer *fb, |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 172 | int crtc_x, int crtc_y, |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 173 | unsigned int crtc_w, unsigned int crtc_h, |
| 174 | uint32_t x, uint32_t y, |
| 175 | uint32_t src_w, uint32_t src_h) |
| 176 | { |
| 177 | struct drm_device *dev = drm_plane->dev; |
| 178 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 179 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 180 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 181 | const int pipe = intel_plane->pipe; |
| 182 | const int plane = intel_plane->plane + 1; |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 183 | u32 plane_ctl, stride_div, stride; |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 184 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 185 | const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey; |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 186 | unsigned long surf_addr; |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 187 | u32 tile_height, plane_offset, plane_size; |
| 188 | unsigned int rotation; |
| 189 | int x_offset, y_offset; |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 190 | struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config; |
| 191 | int scaler_id; |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 192 | |
Ville Syrjälä | 48fe469 | 2015-03-19 17:57:13 +0200 | [diff] [blame] | 193 | plane_ctl = PLANE_CTL_ENABLE | |
| 194 | PLANE_CTL_PIPE_CSC_ENABLE; |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 195 | |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 196 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
| 197 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 198 | |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 199 | rotation = drm_plane->state->rotation; |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 200 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 201 | |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 202 | intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, |
| 203 | pixel_size, true, |
| 204 | src_w != crtc_w || src_h != crtc_h); |
| 205 | |
Damien Lespiau | b321803 | 2015-02-27 11:15:18 +0000 | [diff] [blame] | 206 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
| 207 | fb->pixel_format); |
| 208 | |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 209 | scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id; |
| 210 | |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 211 | /* Sizes are 0 based */ |
| 212 | src_w--; |
| 213 | src_h--; |
| 214 | crtc_w--; |
| 215 | crtc_h--; |
| 216 | |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 217 | if (key->flags) { |
| 218 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); |
| 219 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); |
| 220 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); |
| 221 | } |
| 222 | |
| 223 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
| 224 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; |
| 225 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
| 226 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; |
| 227 | |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 228 | surf_addr = intel_plane_obj_offset(intel_plane, obj); |
| 229 | |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 230 | if (intel_rotation_90_or_270(rotation)) { |
| 231 | /* stride: Surface height in tiles */ |
| 232 | tile_height = intel_tile_height(dev, fb->bits_per_pixel, |
| 233 | fb->modifier[0]); |
| 234 | stride = DIV_ROUND_UP(fb->height, tile_height); |
| 235 | plane_size = (src_w << 16) | src_h; |
| 236 | x_offset = stride * tile_height - y - (src_h + 1); |
| 237 | y_offset = x; |
| 238 | } else { |
| 239 | stride = fb->pitches[0] / stride_div; |
| 240 | plane_size = (src_h << 16) | src_w; |
| 241 | x_offset = x; |
| 242 | y_offset = y; |
| 243 | } |
| 244 | plane_offset = y_offset << 16 | x_offset; |
| 245 | |
| 246 | I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); |
| 247 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 248 | I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 249 | |
| 250 | /* program plane scaler */ |
| 251 | if (scaler_id >= 0) { |
| 252 | uint32_t ps_ctrl = 0; |
| 253 | |
| 254 | DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, |
| 255 | PS_PLANE_SEL(plane)); |
| 256 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | |
| 257 | crtc_state->scaler_state.scalers[scaler_id].mode; |
| 258 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
| 259 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
| 260 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); |
| 261 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), |
| 262 | ((crtc_w + 1) << 16)|(crtc_h + 1)); |
| 263 | |
| 264 | I915_WRITE(PLANE_POS(pipe, plane), 0); |
| 265 | } else { |
| 266 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); |
| 267 | } |
| 268 | |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 269 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); |
Tvrtko Ursulin | 121920f | 2015-03-23 11:10:37 +0000 | [diff] [blame] | 270 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 271 | POSTING_READ(PLANE_SURF(pipe, plane)); |
| 272 | } |
| 273 | |
| 274 | static void |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 275 | skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force) |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 276 | { |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 277 | struct drm_device *dev = dplane->dev; |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 278 | struct drm_i915_private *dev_priv = dev->dev_private; |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 279 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 280 | const int pipe = intel_plane->pipe; |
| 281 | const int plane = intel_plane->plane + 1; |
| 282 | |
Ville Syrjälä | 48fe469 | 2015-03-19 17:57:13 +0200 | [diff] [blame] | 283 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 284 | |
| 285 | /* Activate double buffered register update */ |
Ville Syrjälä | 2ddc1da | 2015-03-19 17:57:14 +0200 | [diff] [blame] | 286 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
| 287 | POSTING_READ(PLANE_SURF(pipe, plane)); |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 288 | |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 289 | intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 290 | } |
| 291 | |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 292 | static void |
Ville Syrjälä | 6ca2aeb | 2014-10-20 19:47:53 +0300 | [diff] [blame] | 293 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) |
| 294 | { |
| 295 | struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; |
| 296 | int plane = intel_plane->plane; |
| 297 | |
| 298 | /* Seems RGB data bypasses the CSC always */ |
| 299 | if (!format_is_yuv(format)) |
| 300 | return; |
| 301 | |
| 302 | /* |
| 303 | * BT.601 limited range YCbCr -> full range RGB |
| 304 | * |
| 305 | * |r| | 6537 4769 0| |cr | |
| 306 | * |g| = |-3330 4769 -1605| x |y-64| |
| 307 | * |b| | 0 4769 8263| |cb | |
| 308 | * |
| 309 | * Cb and Cr apparently come in as signed already, so no |
| 310 | * need for any offset. For Y we need to remove the offset. |
| 311 | */ |
| 312 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); |
| 313 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
| 314 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); |
| 315 | |
| 316 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); |
| 317 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); |
| 318 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); |
| 319 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); |
| 320 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); |
| 321 | |
| 322 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); |
| 323 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
| 324 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); |
| 325 | |
| 326 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
| 327 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
| 328 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); |
| 329 | } |
| 330 | |
| 331 | static void |
Ville Syrjälä | b39d53f | 2013-08-06 22:24:09 +0300 | [diff] [blame] | 332 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
| 333 | struct drm_framebuffer *fb, |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 334 | int crtc_x, int crtc_y, |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 335 | unsigned int crtc_w, unsigned int crtc_h, |
| 336 | uint32_t x, uint32_t y, |
| 337 | uint32_t src_w, uint32_t src_h) |
| 338 | { |
| 339 | struct drm_device *dev = dplane->dev; |
| 340 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 341 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 342 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 343 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 344 | int pipe = intel_plane->pipe; |
| 345 | int plane = intel_plane->plane; |
| 346 | u32 sprctl; |
| 347 | unsigned long sprsurf_offset, linear_offset; |
| 348 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 349 | const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey; |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 350 | |
Ville Syrjälä | 48fe469 | 2015-03-19 17:57:13 +0200 | [diff] [blame] | 351 | sprctl = SP_ENABLE; |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 352 | |
| 353 | switch (fb->pixel_format) { |
| 354 | case DRM_FORMAT_YUYV: |
| 355 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; |
| 356 | break; |
| 357 | case DRM_FORMAT_YVYU: |
| 358 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; |
| 359 | break; |
| 360 | case DRM_FORMAT_UYVY: |
| 361 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; |
| 362 | break; |
| 363 | case DRM_FORMAT_VYUY: |
| 364 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; |
| 365 | break; |
| 366 | case DRM_FORMAT_RGB565: |
| 367 | sprctl |= SP_FORMAT_BGR565; |
| 368 | break; |
| 369 | case DRM_FORMAT_XRGB8888: |
| 370 | sprctl |= SP_FORMAT_BGRX8888; |
| 371 | break; |
| 372 | case DRM_FORMAT_ARGB8888: |
| 373 | sprctl |= SP_FORMAT_BGRA8888; |
| 374 | break; |
| 375 | case DRM_FORMAT_XBGR2101010: |
| 376 | sprctl |= SP_FORMAT_RGBX1010102; |
| 377 | break; |
| 378 | case DRM_FORMAT_ABGR2101010: |
| 379 | sprctl |= SP_FORMAT_RGBA1010102; |
| 380 | break; |
| 381 | case DRM_FORMAT_XBGR8888: |
| 382 | sprctl |= SP_FORMAT_RGBX8888; |
| 383 | break; |
| 384 | case DRM_FORMAT_ABGR8888: |
| 385 | sprctl |= SP_FORMAT_RGBA8888; |
| 386 | break; |
| 387 | default: |
| 388 | /* |
| 389 | * If we get here one of the upper layers failed to filter |
| 390 | * out the unsupported plane formats |
| 391 | */ |
| 392 | BUG(); |
| 393 | break; |
| 394 | } |
| 395 | |
Ville Syrjälä | 4ea67bc | 2013-11-18 18:32:38 -0800 | [diff] [blame] | 396 | /* |
| 397 | * Enable gamma to match primary/cursor plane behaviour. |
| 398 | * FIXME should be user controllable via propertiesa. |
| 399 | */ |
| 400 | sprctl |= SP_GAMMA_ENABLE; |
| 401 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 402 | if (obj->tiling_mode != I915_TILING_NONE) |
| 403 | sprctl |= SP_TILED; |
| 404 | |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 405 | intel_update_sprite_watermarks(dplane, crtc, src_w, src_h, |
| 406 | pixel_size, true, |
Ville Syrjälä | 67ca28f | 2013-07-05 11:57:14 +0300 | [diff] [blame] | 407 | src_w != crtc_w || src_h != crtc_h); |
| 408 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 409 | /* Sizes are 0 based */ |
| 410 | src_w--; |
| 411 | src_h--; |
| 412 | crtc_w--; |
| 413 | crtc_h--; |
| 414 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 415 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
| 416 | sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, |
| 417 | obj->tiling_mode, |
| 418 | pixel_size, |
| 419 | fb->pitches[0]); |
| 420 | linear_offset -= sprsurf_offset; |
| 421 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 422 | if (dplane->state->rotation == BIT(DRM_ROTATE_180)) { |
Ville Syrjälä | 76eebda | 2014-08-05 11:26:52 +0530 | [diff] [blame] | 423 | sprctl |= SP_ROTATE_180; |
| 424 | |
| 425 | x += src_w; |
| 426 | y += src_h; |
| 427 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
| 428 | } |
| 429 | |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 430 | if (key->flags) { |
| 431 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); |
| 432 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); |
| 433 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); |
| 434 | } |
| 435 | |
| 436 | if (key->flags & I915_SET_COLORKEY_SOURCE) |
| 437 | sprctl |= SP_SOURCE_KEY; |
| 438 | |
Ville Syrjälä | 6ca2aeb | 2014-10-20 19:47:53 +0300 | [diff] [blame] | 439 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
| 440 | chv_update_csc(intel_plane, fb->pixel_format); |
| 441 | |
Ville Syrjälä | ca6ad02 | 2014-01-17 20:09:03 +0200 | [diff] [blame] | 442 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
| 443 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); |
| 444 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 445 | if (obj->tiling_mode != I915_TILING_NONE) |
| 446 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); |
| 447 | else |
| 448 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); |
| 449 | |
Ville Syrjälä | c14b048 | 2014-10-16 20:52:34 +0300 | [diff] [blame] | 450 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
| 451 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 452 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
| 453 | I915_WRITE(SPCNTR(pipe, plane), sprctl); |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 454 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
| 455 | sprsurf_offset); |
Ville Syrjälä | 5b633d6 | 2014-04-29 13:35:47 +0300 | [diff] [blame] | 456 | |
| 457 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | static void |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 461 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force) |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 462 | { |
| 463 | struct drm_device *dev = dplane->dev; |
| 464 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 465 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 466 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 467 | int pipe = intel_plane->pipe; |
| 468 | int plane = intel_plane->plane; |
| 469 | |
Ville Syrjälä | 48fe469 | 2015-03-19 17:57:13 +0200 | [diff] [blame] | 470 | I915_WRITE(SPCNTR(pipe, plane), 0); |
| 471 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 472 | /* Activate double buffered register update */ |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 473 | I915_WRITE(SPSURF(pipe, plane), 0); |
Ville Syrjälä | 5b633d6 | 2014-04-29 13:35:47 +0300 | [diff] [blame] | 474 | |
| 475 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
Ville Syrjälä | a95fd8c | 2013-08-06 22:24:12 +0300 | [diff] [blame] | 476 | |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 477 | intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 478 | } |
| 479 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 480 | |
| 481 | static void |
Ville Syrjälä | b39d53f | 2013-08-06 22:24:09 +0300 | [diff] [blame] | 482 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
| 483 | struct drm_framebuffer *fb, |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 484 | int crtc_x, int crtc_y, |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 485 | unsigned int crtc_w, unsigned int crtc_h, |
| 486 | uint32_t x, uint32_t y, |
| 487 | uint32_t src_w, uint32_t src_h) |
| 488 | { |
| 489 | struct drm_device *dev = plane->dev; |
| 490 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 491 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 492 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 493 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 494 | enum pipe pipe = intel_plane->pipe; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 495 | u32 sprctl, sprscale = 0; |
Damien Lespiau | 5a35e99 | 2012-10-26 18:20:12 +0100 | [diff] [blame] | 496 | unsigned long sprsurf_offset, linear_offset; |
Ville Syrjälä | 2bd3c3c | 2012-10-31 17:50:20 +0200 | [diff] [blame] | 497 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 498 | const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 499 | |
Ville Syrjälä | 48fe469 | 2015-03-19 17:57:13 +0200 | [diff] [blame] | 500 | sprctl = SPRITE_ENABLE; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 501 | |
| 502 | switch (fb->pixel_format) { |
| 503 | case DRM_FORMAT_XBGR8888: |
Vijay Purushothaman | 5ee3691 | 2012-08-23 12:08:57 +0530 | [diff] [blame] | 504 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 505 | break; |
| 506 | case DRM_FORMAT_XRGB8888: |
Vijay Purushothaman | 5ee3691 | 2012-08-23 12:08:57 +0530 | [diff] [blame] | 507 | sprctl |= SPRITE_FORMAT_RGBX888; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 508 | break; |
| 509 | case DRM_FORMAT_YUYV: |
| 510 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 511 | break; |
| 512 | case DRM_FORMAT_YVYU: |
| 513 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 514 | break; |
| 515 | case DRM_FORMAT_UYVY: |
| 516 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 517 | break; |
| 518 | case DRM_FORMAT_VYUY: |
| 519 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 520 | break; |
| 521 | default: |
Ville Syrjälä | 28d491d | 2012-10-31 17:50:21 +0200 | [diff] [blame] | 522 | BUG(); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 523 | } |
| 524 | |
Ville Syrjälä | 4ea67bc | 2013-11-18 18:32:38 -0800 | [diff] [blame] | 525 | /* |
| 526 | * Enable gamma to match primary/cursor plane behaviour. |
| 527 | * FIXME should be user controllable via propertiesa. |
| 528 | */ |
| 529 | sprctl |= SPRITE_GAMMA_ENABLE; |
| 530 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 531 | if (obj->tiling_mode != I915_TILING_NONE) |
| 532 | sprctl |= SPRITE_TILED; |
| 533 | |
Ville Syrjälä | b42c600 | 2013-11-03 13:47:27 +0200 | [diff] [blame] | 534 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Paulo Zanoni | 1f5d76d | 2013-08-23 19:51:28 -0300 | [diff] [blame] | 535 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
| 536 | else |
| 537 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; |
| 538 | |
Ville Syrjälä | 6bbfa1c | 2013-11-02 21:07:39 -0700 | [diff] [blame] | 539 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | 86d3efc | 2013-01-18 19:11:38 +0200 | [diff] [blame] | 540 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
| 541 | |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 542 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size, |
| 543 | true, |
Ville Syrjälä | 67ca28f | 2013-07-05 11:57:14 +0300 | [diff] [blame] | 544 | src_w != crtc_w || src_h != crtc_h); |
| 545 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 546 | /* Sizes are 0 based */ |
| 547 | src_w--; |
| 548 | src_h--; |
| 549 | crtc_w--; |
| 550 | crtc_h--; |
| 551 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 552 | if (crtc_w != src_w || crtc_h != src_h) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 553 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 554 | |
Chris Wilson | ca320ac | 2012-12-19 12:14:22 +0000 | [diff] [blame] | 555 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
Damien Lespiau | 5a35e99 | 2012-10-26 18:20:12 +0100 | [diff] [blame] | 556 | sprsurf_offset = |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 557 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
| 558 | pixel_size, fb->pitches[0]); |
Damien Lespiau | 5a35e99 | 2012-10-26 18:20:12 +0100 | [diff] [blame] | 559 | linear_offset -= sprsurf_offset; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 560 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 561 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
Ville Syrjälä | 76eebda | 2014-08-05 11:26:52 +0530 | [diff] [blame] | 562 | sprctl |= SPRITE_ROTATE_180; |
| 563 | |
| 564 | /* HSW and BDW does this automagically in hardware */ |
| 565 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
| 566 | x += src_w; |
| 567 | y += src_h; |
| 568 | linear_offset += src_h * fb->pitches[0] + |
| 569 | src_w * pixel_size; |
| 570 | } |
| 571 | } |
| 572 | |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 573 | if (key->flags) { |
| 574 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); |
| 575 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); |
| 576 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); |
| 577 | } |
| 578 | |
| 579 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
| 580 | sprctl |= SPRITE_DEST_KEY; |
| 581 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
| 582 | sprctl |= SPRITE_SOURCE_KEY; |
| 583 | |
Ville Syrjälä | ca6ad02 | 2014-01-17 20:09:03 +0200 | [diff] [blame] | 584 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
| 585 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); |
| 586 | |
Damien Lespiau | 5a35e99 | 2012-10-26 18:20:12 +0100 | [diff] [blame] | 587 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
| 588 | * register */ |
Paulo Zanoni | b3dc685 | 2013-11-02 21:07:33 -0700 | [diff] [blame] | 589 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Damien Lespiau | 5a35e99 | 2012-10-26 18:20:12 +0100 | [diff] [blame] | 590 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
| 591 | else if (obj->tiling_mode != I915_TILING_NONE) |
| 592 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
| 593 | else |
| 594 | I915_WRITE(SPRLINOFF(pipe), linear_offset); |
Damien Lespiau | c54173a | 2012-10-26 18:20:11 +0100 | [diff] [blame] | 595 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 596 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
Damien Lespiau | 2d354c3 | 2012-10-22 18:19:27 +0100 | [diff] [blame] | 597 | if (intel_plane->can_scale) |
| 598 | I915_WRITE(SPRSCALE(pipe), sprscale); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 599 | I915_WRITE(SPRCTL(pipe), sprctl); |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 600 | I915_WRITE(SPRSURF(pipe), |
| 601 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); |
Ville Syrjälä | 5b633d6 | 2014-04-29 13:35:47 +0300 | [diff] [blame] | 602 | |
| 603 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 604 | } |
| 605 | |
| 606 | static void |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 607 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 608 | { |
| 609 | struct drm_device *dev = plane->dev; |
| 610 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 611 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 612 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 613 | int pipe = intel_plane->pipe; |
| 614 | |
| 615 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
| 616 | /* Can't leave the scaler enabled... */ |
Damien Lespiau | 2d354c3 | 2012-10-22 18:19:27 +0100 | [diff] [blame] | 617 | if (intel_plane->can_scale) |
| 618 | I915_WRITE(SPRSCALE(pipe), 0); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 619 | /* Activate double buffered register update */ |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 620 | I915_WRITE(SPRSURF(pipe), 0); |
Ville Syrjälä | 5b633d6 | 2014-04-29 13:35:47 +0300 | [diff] [blame] | 621 | |
| 622 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 623 | } |
| 624 | |
| 625 | static void |
Ville Syrjälä | b39d53f | 2013-08-06 22:24:09 +0300 | [diff] [blame] | 626 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
| 627 | struct drm_framebuffer *fb, |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 628 | int crtc_x, int crtc_y, |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 629 | unsigned int crtc_w, unsigned int crtc_h, |
| 630 | uint32_t x, uint32_t y, |
| 631 | uint32_t src_w, uint32_t src_h) |
| 632 | { |
| 633 | struct drm_device *dev = plane->dev; |
| 634 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 635 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 636 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 637 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Ville Syrjälä | 2bd3c3c | 2012-10-31 17:50:20 +0200 | [diff] [blame] | 638 | int pipe = intel_plane->pipe; |
Damien Lespiau | 5a35e99 | 2012-10-26 18:20:12 +0100 | [diff] [blame] | 639 | unsigned long dvssurf_offset, linear_offset; |
Chris Wilson | 8aaa81a | 2012-04-14 22:14:26 +0100 | [diff] [blame] | 640 | u32 dvscntr, dvsscale; |
Ville Syrjälä | 2bd3c3c | 2012-10-31 17:50:20 +0200 | [diff] [blame] | 641 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 642 | const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 643 | |
Ville Syrjälä | 48fe469 | 2015-03-19 17:57:13 +0200 | [diff] [blame] | 644 | dvscntr = DVS_ENABLE; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 645 | |
| 646 | switch (fb->pixel_format) { |
| 647 | case DRM_FORMAT_XBGR8888: |
Jesse Barnes | ab2f9df | 2012-02-27 12:40:10 -0800 | [diff] [blame] | 648 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 649 | break; |
| 650 | case DRM_FORMAT_XRGB8888: |
Jesse Barnes | ab2f9df | 2012-02-27 12:40:10 -0800 | [diff] [blame] | 651 | dvscntr |= DVS_FORMAT_RGBX888; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 652 | break; |
| 653 | case DRM_FORMAT_YUYV: |
| 654 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 655 | break; |
| 656 | case DRM_FORMAT_YVYU: |
| 657 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 658 | break; |
| 659 | case DRM_FORMAT_UYVY: |
| 660 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 661 | break; |
| 662 | case DRM_FORMAT_VYUY: |
| 663 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 664 | break; |
| 665 | default: |
Ville Syrjälä | 28d491d | 2012-10-31 17:50:21 +0200 | [diff] [blame] | 666 | BUG(); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 667 | } |
| 668 | |
Ville Syrjälä | 4ea67bc | 2013-11-18 18:32:38 -0800 | [diff] [blame] | 669 | /* |
| 670 | * Enable gamma to match primary/cursor plane behaviour. |
| 671 | * FIXME should be user controllable via propertiesa. |
| 672 | */ |
| 673 | dvscntr |= DVS_GAMMA_ENABLE; |
| 674 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 675 | if (obj->tiling_mode != I915_TILING_NONE) |
| 676 | dvscntr |= DVS_TILED; |
| 677 | |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 678 | if (IS_GEN6(dev)) |
| 679 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 680 | |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 681 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, |
| 682 | pixel_size, true, |
Ville Syrjälä | 67ca28f | 2013-07-05 11:57:14 +0300 | [diff] [blame] | 683 | src_w != crtc_w || src_h != crtc_h); |
| 684 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 685 | /* Sizes are 0 based */ |
| 686 | src_w--; |
| 687 | src_h--; |
| 688 | crtc_w--; |
| 689 | crtc_h--; |
| 690 | |
Chris Wilson | 8aaa81a | 2012-04-14 22:14:26 +0100 | [diff] [blame] | 691 | dvsscale = 0; |
Ville Syrjälä | 8368f01 | 2013-12-05 15:51:31 +0200 | [diff] [blame] | 692 | if (crtc_w != src_w || crtc_h != src_h) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 693 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
| 694 | |
Chris Wilson | ca320ac | 2012-12-19 12:14:22 +0000 | [diff] [blame] | 695 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
Damien Lespiau | 5a35e99 | 2012-10-26 18:20:12 +0100 | [diff] [blame] | 696 | dvssurf_offset = |
Chris Wilson | bc75286 | 2013-02-21 20:04:31 +0000 | [diff] [blame] | 697 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
| 698 | pixel_size, fb->pitches[0]); |
Damien Lespiau | 5a35e99 | 2012-10-26 18:20:12 +0100 | [diff] [blame] | 699 | linear_offset -= dvssurf_offset; |
| 700 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 701 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
Ville Syrjälä | 76eebda | 2014-08-05 11:26:52 +0530 | [diff] [blame] | 702 | dvscntr |= DVS_ROTATE_180; |
| 703 | |
| 704 | x += src_w; |
| 705 | y += src_h; |
| 706 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; |
| 707 | } |
| 708 | |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 709 | if (key->flags) { |
| 710 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); |
| 711 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); |
| 712 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); |
| 713 | } |
| 714 | |
| 715 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
| 716 | dvscntr |= DVS_DEST_KEY; |
| 717 | else if (key->flags & I915_SET_COLORKEY_SOURCE) |
| 718 | dvscntr |= DVS_SOURCE_KEY; |
| 719 | |
Ville Syrjälä | ca6ad02 | 2014-01-17 20:09:03 +0200 | [diff] [blame] | 720 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
| 721 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); |
| 722 | |
Damien Lespiau | 5a35e99 | 2012-10-26 18:20:12 +0100 | [diff] [blame] | 723 | if (obj->tiling_mode != I915_TILING_NONE) |
| 724 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
| 725 | else |
| 726 | I915_WRITE(DVSLINOFF(pipe), linear_offset); |
| 727 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 728 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
| 729 | I915_WRITE(DVSSCALE(pipe), dvsscale); |
| 730 | I915_WRITE(DVSCNTR(pipe), dvscntr); |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 731 | I915_WRITE(DVSSURF(pipe), |
| 732 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); |
Ville Syrjälä | 5b633d6 | 2014-04-29 13:35:47 +0300 | [diff] [blame] | 733 | |
| 734 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 735 | } |
| 736 | |
| 737 | static void |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 738 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 739 | { |
| 740 | struct drm_device *dev = plane->dev; |
| 741 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 742 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Ville Syrjälä | 8d7849d | 2014-04-29 13:35:46 +0300 | [diff] [blame] | 743 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 744 | int pipe = intel_plane->pipe; |
| 745 | |
Ville Syrjälä | 48fe469 | 2015-03-19 17:57:13 +0200 | [diff] [blame] | 746 | I915_WRITE(DVSCNTR(pipe), 0); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 747 | /* Disable the scaler */ |
| 748 | I915_WRITE(DVSSCALE(pipe), 0); |
Ville Syrjälä | 48fe469 | 2015-03-19 17:57:13 +0200 | [diff] [blame] | 749 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 750 | /* Flush double buffered register updates */ |
Daniel Vetter | 85ba7b7 | 2014-01-24 10:31:44 +0100 | [diff] [blame] | 751 | I915_WRITE(DVSSURF(pipe), 0); |
Ville Syrjälä | 5b633d6 | 2014-04-29 13:35:47 +0300 | [diff] [blame] | 752 | |
| 753 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 754 | } |
| 755 | |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 756 | static int |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 757 | intel_check_sprite_plane(struct drm_plane *plane, |
| 758 | struct intel_plane_state *state) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 759 | { |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 760 | struct drm_device *dev = plane->dev; |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 761 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 762 | struct intel_crtc_state *crtc_state; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 763 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 764 | struct drm_framebuffer *fb = state->base.fb; |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 765 | int crtc_x, crtc_y; |
| 766 | unsigned int crtc_w, crtc_h; |
| 767 | uint32_t src_x, src_y, src_w, src_h; |
| 768 | struct drm_rect *src = &state->src; |
| 769 | struct drm_rect *dst = &state->dst; |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 770 | const struct drm_rect *clip = &state->clip; |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 771 | int hscale, vscale; |
| 772 | int max_scale, min_scale; |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 773 | int pixel_size; |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 774 | int ret; |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 775 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 776 | intel_crtc = intel_crtc ? intel_crtc : to_intel_crtc(plane->crtc); |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 777 | crtc_state = state->base.state ? |
| 778 | intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 779 | |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 780 | if (!fb) { |
| 781 | state->visible = false; |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 782 | goto finish; |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 783 | } |
Jesse Barnes | 5e1bac2 | 2013-03-26 09:25:43 -0700 | [diff] [blame] | 784 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 785 | /* Don't modify another pipe's plane */ |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 786 | if (intel_plane->pipe != intel_crtc->pipe) { |
| 787 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 788 | return -EINVAL; |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 789 | } |
| 790 | |
| 791 | /* FIXME check all gen limits */ |
| 792 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { |
| 793 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); |
| 794 | return -EINVAL; |
| 795 | } |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 796 | |
Ville Syrjälä | 3c3686c | 2013-04-24 18:52:39 +0300 | [diff] [blame] | 797 | /* |
| 798 | * FIXME the following code does a bunch of fuzzy adjustments to the |
| 799 | * coordinates and sizes. We probably need some way to decide whether |
| 800 | * more strict checking should be done instead. |
| 801 | */ |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 802 | max_scale = intel_plane->max_downscale << 16; |
| 803 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); |
| 804 | |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 805 | if (INTEL_INFO(dev)->gen >= 9) { |
| 806 | min_scale = 1; |
| 807 | max_scale = skl_max_scale(intel_crtc, crtc_state); |
| 808 | } |
| 809 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 810 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 811 | state->base.rotation); |
Ville Syrjälä | 76eebda | 2014-08-05 11:26:52 +0530 | [diff] [blame] | 812 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 813 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
Ville Syrjälä | 3c3686c | 2013-04-24 18:52:39 +0300 | [diff] [blame] | 814 | BUG_ON(hscale < 0); |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 815 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 816 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
Ville Syrjälä | 3c3686c | 2013-04-24 18:52:39 +0300 | [diff] [blame] | 817 | BUG_ON(vscale < 0); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 818 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 819 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 820 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 821 | crtc_x = dst->x1; |
| 822 | crtc_y = dst->y1; |
| 823 | crtc_w = drm_rect_width(dst); |
| 824 | crtc_h = drm_rect_height(dst); |
Damien Lespiau | 2d354c3 | 2012-10-22 18:19:27 +0100 | [diff] [blame] | 825 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 826 | if (state->visible) { |
Ville Syrjälä | 3c3686c | 2013-04-24 18:52:39 +0300 | [diff] [blame] | 827 | /* check again in case clipping clamped the results */ |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 828 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
Ville Syrjälä | 3c3686c | 2013-04-24 18:52:39 +0300 | [diff] [blame] | 829 | if (hscale < 0) { |
| 830 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 831 | drm_rect_debug_print(src, true); |
| 832 | drm_rect_debug_print(dst, false); |
Ville Syrjälä | 3c3686c | 2013-04-24 18:52:39 +0300 | [diff] [blame] | 833 | |
| 834 | return hscale; |
| 835 | } |
| 836 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 837 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
Ville Syrjälä | 3c3686c | 2013-04-24 18:52:39 +0300 | [diff] [blame] | 838 | if (vscale < 0) { |
| 839 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 840 | drm_rect_debug_print(src, true); |
| 841 | drm_rect_debug_print(dst, false); |
Ville Syrjälä | 3c3686c | 2013-04-24 18:52:39 +0300 | [diff] [blame] | 842 | |
| 843 | return vscale; |
| 844 | } |
| 845 | |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 846 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 847 | drm_rect_adjust_size(src, |
| 848 | drm_rect_width(dst) * hscale - drm_rect_width(src), |
| 849 | drm_rect_height(dst) * vscale - drm_rect_height(src)); |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 850 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 851 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 852 | state->base.rotation); |
Ville Syrjälä | 76eebda | 2014-08-05 11:26:52 +0530 | [diff] [blame] | 853 | |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 854 | /* sanity check to make sure the src viewport wasn't enlarged */ |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 855 | WARN_ON(src->x1 < (int) state->base.src_x || |
| 856 | src->y1 < (int) state->base.src_y || |
| 857 | src->x2 > (int) state->base.src_x + state->base.src_w || |
| 858 | src->y2 > (int) state->base.src_y + state->base.src_h); |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 859 | |
| 860 | /* |
| 861 | * Hardware doesn't handle subpixel coordinates. |
| 862 | * Adjust to (macro)pixel boundary, but be careful not to |
| 863 | * increase the source viewport size, because that could |
| 864 | * push the downscaling factor out of bounds. |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 865 | */ |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 866 | src_x = src->x1 >> 16; |
| 867 | src_w = drm_rect_width(src) >> 16; |
| 868 | src_y = src->y1 >> 16; |
| 869 | src_h = drm_rect_height(src) >> 16; |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 870 | |
| 871 | if (format_is_yuv(fb->pixel_format)) { |
| 872 | src_x &= ~1; |
| 873 | src_w &= ~1; |
| 874 | |
| 875 | /* |
| 876 | * Must keep src and dst the |
| 877 | * same if we can't scale. |
| 878 | */ |
| 879 | if (!intel_plane->can_scale) |
| 880 | crtc_w &= ~1; |
| 881 | |
| 882 | if (crtc_w == 0) |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 883 | state->visible = false; |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 884 | } |
| 885 | } |
| 886 | |
| 887 | /* Check size restrictions when scaling */ |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 888 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 889 | unsigned int width_bytes; |
| 890 | |
| 891 | WARN_ON(!intel_plane->can_scale); |
| 892 | |
| 893 | /* FIXME interlacing min height is 6 */ |
| 894 | |
| 895 | if (crtc_w < 3 || crtc_h < 3) |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 896 | state->visible = false; |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 897 | |
| 898 | if (src_w < 3 || src_h < 3) |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 899 | state->visible = false; |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 900 | |
Matt Roper | cf4c7c1 | 2014-12-04 10:27:42 -0800 | [diff] [blame] | 901 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 902 | width_bytes = ((src_x * pixel_size) & 63) + |
| 903 | src_w * pixel_size; |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 904 | |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 905 | if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || |
| 906 | width_bytes > 4096 || fb->pitches[0] > 4096)) { |
Ville Syrjälä | 1731693 | 2013-04-24 18:52:38 +0300 | [diff] [blame] | 907 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
| 908 | return -EINVAL; |
| 909 | } |
| 910 | } |
| 911 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 912 | if (state->visible) { |
Chandra Konduru | 0a5ae1b | 2015-04-09 16:41:54 -0700 | [diff] [blame] | 913 | src->x1 = src_x << 16; |
| 914 | src->x2 = (src_x + src_w) << 16; |
| 915 | src->y1 = src_y << 16; |
| 916 | src->y2 = (src_y + src_h) << 16; |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 917 | } |
| 918 | |
| 919 | dst->x1 = crtc_x; |
| 920 | dst->x2 = crtc_x + crtc_w; |
| 921 | dst->y1 = crtc_y; |
| 922 | dst->y2 = crtc_y + crtc_h; |
| 923 | |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 924 | finish: |
| 925 | /* |
| 926 | * If the sprite is completely covering the primary plane, |
| 927 | * we can disable the primary and save power. |
| 928 | */ |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 929 | if (intel_crtc->active) { |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 930 | intel_crtc->atomic.fb_bits |= |
| 931 | INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe); |
| 932 | |
Tvrtko Ursulin | 1fc0a8f | 2015-03-23 11:10:38 +0000 | [diff] [blame] | 933 | if (intel_wm_need_update(plane, &state->base)) |
Tvrtko Ursulin | 0fda656 | 2015-02-27 15:12:35 +0000 | [diff] [blame] | 934 | intel_crtc->atomic.update_wm = true; |
Matt Roper | 08fd59f | 2015-03-18 15:04:47 -0700 | [diff] [blame] | 935 | |
| 936 | if (!state->visible) { |
| 937 | /* |
| 938 | * Avoid underruns when disabling the sprite. |
| 939 | * FIXME remove once watermark updates are done properly. |
| 940 | */ |
| 941 | intel_crtc->atomic.wait_vblank = true; |
| 942 | intel_crtc->atomic.update_sprite_watermarks |= |
| 943 | (1 << drm_plane_index(plane)); |
| 944 | } |
Matt Roper | 32b7eee | 2014-12-24 07:59:06 -0800 | [diff] [blame] | 945 | } |
| 946 | |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 947 | if (INTEL_INFO(dev)->gen >= 9) { |
| 948 | ret = skl_update_scaler_users(intel_crtc, crtc_state, intel_plane, |
| 949 | state, 0); |
| 950 | if (ret) |
| 951 | return ret; |
| 952 | } |
| 953 | |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 954 | return 0; |
| 955 | } |
| 956 | |
Gustavo Padovan | 34aa50a | 2014-10-24 14:51:32 +0100 | [diff] [blame] | 957 | static void |
| 958 | intel_commit_sprite_plane(struct drm_plane *plane, |
| 959 | struct intel_plane_state *state) |
| 960 | { |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 961 | struct drm_crtc *crtc = state->base.crtc; |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 962 | struct intel_crtc *intel_crtc; |
Gustavo Padovan | 34aa50a | 2014-10-24 14:51:32 +0100 | [diff] [blame] | 963 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Matt Roper | 2b875c2 | 2014-12-01 15:40:13 -0800 | [diff] [blame] | 964 | struct drm_framebuffer *fb = state->base.fb; |
Gustavo Padovan | 34aa50a | 2014-10-24 14:51:32 +0100 | [diff] [blame] | 965 | int crtc_x, crtc_y; |
| 966 | unsigned int crtc_w, crtc_h; |
| 967 | uint32_t src_x, src_y, src_w, src_h; |
Gustavo Padovan | 34aa50a | 2014-10-24 14:51:32 +0100 | [diff] [blame] | 968 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 969 | crtc = crtc ? crtc : plane->crtc; |
| 970 | intel_crtc = to_intel_crtc(crtc); |
| 971 | |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 972 | plane->fb = fb; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 973 | |
Ville Syrjälä | 03c5b25 | 2013-10-01 18:02:11 +0300 | [diff] [blame] | 974 | if (intel_crtc->active) { |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 975 | if (state->visible) { |
| 976 | crtc_x = state->dst.x1; |
Gustavo Padovan | e259f17 | 2014-09-11 17:42:15 -0300 | [diff] [blame] | 977 | crtc_y = state->dst.y1; |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 978 | crtc_w = drm_rect_width(&state->dst); |
| 979 | crtc_h = drm_rect_height(&state->dst); |
Chandra Konduru | 0a5ae1b | 2015-04-09 16:41:54 -0700 | [diff] [blame] | 980 | src_x = state->src.x1 >> 16; |
| 981 | src_y = state->src.y1 >> 16; |
| 982 | src_w = drm_rect_width(&state->src) >> 16; |
| 983 | src_h = drm_rect_height(&state->src) >> 16; |
Ville Syrjälä | bdd7554 | 2015-03-19 17:57:11 +0200 | [diff] [blame] | 984 | intel_plane->update_plane(plane, crtc, fb, |
Ville Syrjälä | 03c5b25 | 2013-10-01 18:02:11 +0300 | [diff] [blame] | 985 | crtc_x, crtc_y, crtc_w, crtc_h, |
| 986 | src_x, src_y, src_w, src_h); |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 987 | } else { |
Maarten Lankhorst | a8ad0d8 | 2015-04-21 17:12:51 +0300 | [diff] [blame] | 988 | intel_plane->disable_plane(plane, crtc, false); |
Gustavo Padovan | 96d61a7 | 2014-09-05 17:04:47 -0300 | [diff] [blame] | 989 | } |
Ville Syrjälä | 03c5b25 | 2013-10-01 18:02:11 +0300 | [diff] [blame] | 990 | } |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 991 | } |
| 992 | |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 993 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
| 994 | struct drm_file *file_priv) |
| 995 | { |
| 996 | struct drm_intel_sprite_colorkey *set = data; |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 997 | struct drm_plane *plane; |
| 998 | struct intel_plane *intel_plane; |
| 999 | int ret = 0; |
| 1000 | |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 1001 | /* Make sure we don't try to enable both src & dest simultaneously */ |
| 1002 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) |
| 1003 | return -EINVAL; |
| 1004 | |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 1005 | if (IS_VALLEYVIEW(dev) && |
| 1006 | set->flags & I915_SET_COLORKEY_DESTINATION) |
| 1007 | return -EINVAL; |
| 1008 | |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1009 | drm_modeset_lock_all(dev); |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 1010 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 1011 | plane = drm_plane_find(dev, set->plane_id); |
Ville Syrjälä | 840a1cf | 2015-03-27 19:59:40 +0200 | [diff] [blame] | 1012 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) { |
Ville Syrjälä | 3f2c205 | 2013-10-17 13:35:03 +0300 | [diff] [blame] | 1013 | ret = -ENOENT; |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 1014 | goto out_unlock; |
| 1015 | } |
| 1016 | |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 1017 | intel_plane = to_intel_plane(plane); |
Chandra Konduru | 6156a45 | 2015-04-27 13:48:39 -0700 | [diff] [blame] | 1018 | |
| 1019 | if (INTEL_INFO(dev)->gen >= 9) { |
| 1020 | /* plane scaling and colorkey are mutually exclusive */ |
| 1021 | if (to_intel_plane_state(plane->state)->scaler_id >= 0) { |
| 1022 | DRM_ERROR("colorkey not allowed with scaler\n"); |
| 1023 | ret = -EINVAL; |
| 1024 | goto out_unlock; |
| 1025 | } |
| 1026 | } |
| 1027 | |
Ville Syrjälä | 47ecbb2 | 2015-03-19 21:18:57 +0200 | [diff] [blame] | 1028 | intel_plane->ckey = *set; |
| 1029 | |
| 1030 | /* |
| 1031 | * The only way this could fail would be due to |
| 1032 | * the current plane state being unsupportable already, |
| 1033 | * and we dont't consider that an error for the |
| 1034 | * colorkey ioctl. So just ignore any error. |
| 1035 | */ |
| 1036 | intel_plane_restore(plane); |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 1037 | |
| 1038 | out_unlock: |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1039 | drm_modeset_unlock_all(dev); |
Jesse Barnes | 8ea3086 | 2012-01-03 08:05:39 -0800 | [diff] [blame] | 1040 | return ret; |
| 1041 | } |
| 1042 | |
Ville Syrjälä | e57465f | 2014-08-05 11:26:53 +0530 | [diff] [blame] | 1043 | int intel_plane_restore(struct drm_plane *plane) |
Jesse Barnes | 5e1bac2 | 2013-03-26 09:25:43 -0700 | [diff] [blame] | 1044 | { |
Ville Syrjälä | 6e721fb | 2015-03-10 13:15:23 +0200 | [diff] [blame] | 1045 | if (!plane->crtc || !plane->state->fb) |
Ville Syrjälä | e57465f | 2014-08-05 11:26:53 +0530 | [diff] [blame] | 1046 | return 0; |
Jesse Barnes | 5e1bac2 | 2013-03-26 09:25:43 -0700 | [diff] [blame] | 1047 | |
Matt Roper | 70a101f | 2015-04-08 18:56:53 -0700 | [diff] [blame] | 1048 | return drm_plane_helper_update(plane, plane->crtc, plane->state->fb, |
| 1049 | plane->state->crtc_x, plane->state->crtc_y, |
| 1050 | plane->state->crtc_w, plane->state->crtc_h, |
| 1051 | plane->state->src_x, plane->state->src_y, |
| 1052 | plane->state->src_w, plane->state->src_h); |
Jesse Barnes | 5e1bac2 | 2013-03-26 09:25:43 -0700 | [diff] [blame] | 1053 | } |
| 1054 | |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1055 | static uint32_t ilk_plane_formats[] = { |
| 1056 | DRM_FORMAT_XRGB8888, |
| 1057 | DRM_FORMAT_YUYV, |
| 1058 | DRM_FORMAT_YVYU, |
| 1059 | DRM_FORMAT_UYVY, |
| 1060 | DRM_FORMAT_VYUY, |
| 1061 | }; |
| 1062 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1063 | static uint32_t snb_plane_formats[] = { |
| 1064 | DRM_FORMAT_XBGR8888, |
| 1065 | DRM_FORMAT_XRGB8888, |
| 1066 | DRM_FORMAT_YUYV, |
| 1067 | DRM_FORMAT_YVYU, |
| 1068 | DRM_FORMAT_UYVY, |
| 1069 | DRM_FORMAT_VYUY, |
| 1070 | }; |
| 1071 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1072 | static uint32_t vlv_plane_formats[] = { |
| 1073 | DRM_FORMAT_RGB565, |
| 1074 | DRM_FORMAT_ABGR8888, |
| 1075 | DRM_FORMAT_ARGB8888, |
| 1076 | DRM_FORMAT_XBGR8888, |
| 1077 | DRM_FORMAT_XRGB8888, |
| 1078 | DRM_FORMAT_XBGR2101010, |
| 1079 | DRM_FORMAT_ABGR2101010, |
| 1080 | DRM_FORMAT_YUYV, |
| 1081 | DRM_FORMAT_YVYU, |
| 1082 | DRM_FORMAT_UYVY, |
| 1083 | DRM_FORMAT_VYUY, |
| 1084 | }; |
| 1085 | |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 1086 | static uint32_t skl_plane_formats[] = { |
| 1087 | DRM_FORMAT_RGB565, |
| 1088 | DRM_FORMAT_ABGR8888, |
| 1089 | DRM_FORMAT_ARGB8888, |
| 1090 | DRM_FORMAT_XBGR8888, |
| 1091 | DRM_FORMAT_XRGB8888, |
| 1092 | DRM_FORMAT_YUYV, |
| 1093 | DRM_FORMAT_YVYU, |
| 1094 | DRM_FORMAT_UYVY, |
| 1095 | DRM_FORMAT_VYUY, |
| 1096 | }; |
| 1097 | |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1098 | int |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1099 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1100 | { |
| 1101 | struct intel_plane *intel_plane; |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 1102 | struct intel_plane_state *state; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1103 | unsigned long possible_crtcs; |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1104 | const uint32_t *plane_formats; |
| 1105 | int num_plane_formats; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1106 | int ret; |
| 1107 | |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1108 | if (INTEL_INFO(dev)->gen < 5) |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1109 | return -ENODEV; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1110 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 1111 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1112 | if (!intel_plane) |
| 1113 | return -ENOMEM; |
| 1114 | |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 1115 | state = intel_create_plane_state(&intel_plane->base); |
| 1116 | if (!state) { |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 1117 | kfree(intel_plane); |
| 1118 | return -ENOMEM; |
| 1119 | } |
Matt Roper | 8e7d688 | 2015-01-21 16:35:41 -0800 | [diff] [blame] | 1120 | intel_plane->base.state = &state->base; |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 1121 | |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1122 | switch (INTEL_INFO(dev)->gen) { |
| 1123 | case 5: |
| 1124 | case 6: |
Damien Lespiau | 2d354c3 | 2012-10-22 18:19:27 +0100 | [diff] [blame] | 1125 | intel_plane->can_scale = true; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1126 | intel_plane->max_downscale = 16; |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1127 | intel_plane->update_plane = ilk_update_plane; |
| 1128 | intel_plane->disable_plane = ilk_disable_plane; |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1129 | |
| 1130 | if (IS_GEN6(dev)) { |
| 1131 | plane_formats = snb_plane_formats; |
| 1132 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
| 1133 | } else { |
| 1134 | plane_formats = ilk_plane_formats; |
| 1135 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); |
| 1136 | } |
| 1137 | break; |
| 1138 | |
| 1139 | case 7: |
Ben Widawsky | 4e0bbc3 | 2013-11-02 21:07:07 -0700 | [diff] [blame] | 1140 | case 8: |
Damien Lespiau | d49f709 | 2013-04-25 15:15:00 +0100 | [diff] [blame] | 1141 | if (IS_IVYBRIDGE(dev)) { |
Damien Lespiau | 2d354c3 | 2012-10-22 18:19:27 +0100 | [diff] [blame] | 1142 | intel_plane->can_scale = true; |
Damien Lespiau | d49f709 | 2013-04-25 15:15:00 +0100 | [diff] [blame] | 1143 | intel_plane->max_downscale = 2; |
| 1144 | } else { |
| 1145 | intel_plane->can_scale = false; |
| 1146 | intel_plane->max_downscale = 1; |
| 1147 | } |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1148 | |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1149 | if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1150 | intel_plane->update_plane = vlv_update_plane; |
| 1151 | intel_plane->disable_plane = vlv_disable_plane; |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1152 | |
| 1153 | plane_formats = vlv_plane_formats; |
| 1154 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); |
| 1155 | } else { |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1156 | intel_plane->update_plane = ivb_update_plane; |
| 1157 | intel_plane->disable_plane = ivb_disable_plane; |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1158 | |
| 1159 | plane_formats = snb_plane_formats; |
| 1160 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); |
| 1161 | } |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1162 | break; |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 1163 | case 9: |
Chandra Konduru | c331879 | 2015-04-15 15:15:02 -0700 | [diff] [blame] | 1164 | intel_plane->can_scale = true; |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 1165 | intel_plane->update_plane = skl_update_plane; |
| 1166 | intel_plane->disable_plane = skl_disable_plane; |
Chandra Konduru | 549e2bf | 2015-04-07 15:28:38 -0700 | [diff] [blame] | 1167 | state->scaler_id = -1; |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1168 | |
Damien Lespiau | dc2a41b | 2013-12-04 00:49:41 +0000 | [diff] [blame] | 1169 | plane_formats = skl_plane_formats; |
| 1170 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); |
| 1171 | break; |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1172 | default: |
Jesper Juhl | a8b0bba | 2012-06-27 00:55:37 +0200 | [diff] [blame] | 1173 | kfree(intel_plane); |
Chris Wilson | d1686ae | 2012-04-10 11:41:49 +0100 | [diff] [blame] | 1174 | return -ENODEV; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1175 | } |
| 1176 | |
| 1177 | intel_plane->pipe = pipe; |
Jesse Barnes | 7f1f385 | 2013-04-02 11:22:20 -0700 | [diff] [blame] | 1178 | intel_plane->plane = plane; |
Matt Roper | c59cb17 | 2014-12-01 15:40:16 -0800 | [diff] [blame] | 1179 | intel_plane->check_plane = intel_check_sprite_plane; |
| 1180 | intel_plane->commit_plane = intel_commit_sprite_plane; |
Chandra Konduru | 08e221f | 2015-04-07 15:28:37 -0700 | [diff] [blame] | 1181 | intel_plane->ckey.flags = I915_SET_COLORKEY_NONE; |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1182 | possible_crtcs = (1 << pipe); |
Derek Foreman | 8fe8a3f | 2014-09-03 10:38:20 -0300 | [diff] [blame] | 1183 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, |
Matt Roper | 65a3fea | 2015-01-21 16:35:42 -0800 | [diff] [blame] | 1184 | &intel_plane_funcs, |
Derek Foreman | 8fe8a3f | 2014-09-03 10:38:20 -0300 | [diff] [blame] | 1185 | plane_formats, num_plane_formats, |
| 1186 | DRM_PLANE_TYPE_OVERLAY); |
Ville Syrjälä | 7ed6eee | 2014-08-05 11:26:55 +0530 | [diff] [blame] | 1187 | if (ret) { |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1188 | kfree(intel_plane); |
Ville Syrjälä | 7ed6eee | 2014-08-05 11:26:55 +0530 | [diff] [blame] | 1189 | goto out; |
| 1190 | } |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1191 | |
Sonika Jindal | 3b7a511 | 2015-04-10 14:37:29 +0530 | [diff] [blame] | 1192 | intel_create_rotation_property(dev, intel_plane); |
Ville Syrjälä | 7ed6eee | 2014-08-05 11:26:55 +0530 | [diff] [blame] | 1193 | |
Matt Roper | ea2c67b | 2014-12-23 10:41:52 -0800 | [diff] [blame] | 1194 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
| 1195 | |
Ville Syrjälä | 7ed6eee | 2014-08-05 11:26:55 +0530 | [diff] [blame] | 1196 | out: |
Jesse Barnes | b840d907f | 2011-12-13 13:19:38 -0800 | [diff] [blame] | 1197 | return ret; |
| 1198 | } |