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Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
Ben Hutchings0a6f40c2011-02-25 00:01:34 +00004 * Copyright 2005-2011 Solarflare Communications Inc.
Ben Hutchings8ceee662008-04-27 12:55:59 +01005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11/* Common definitions for all Efx net driver code */
12
13#ifndef EFX_NET_DRIVER_H
14#define EFX_NET_DRIVER_H
15
Ben Hutchings8ceee662008-04-27 12:55:59 +010016#include <linux/netdevice.h>
17#include <linux/etherdevice.h>
18#include <linux/ethtool.h>
19#include <linux/if_vlan.h>
Steve Hodgson90d683a2010-06-01 11:19:39 +000020#include <linux/timer.h>
Ben Hutchings68e7f452009-04-29 08:05:08 +000021#include <linux/mdio.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010022#include <linux/list.h>
23#include <linux/pci.h>
24#include <linux/device.h>
25#include <linux/highmem.h>
26#include <linux/workqueue.h>
David S. Miller10ed61c2010-09-21 16:11:06 -070027#include <linux/vmalloc.h>
Ben Hutchings37b5a602008-05-30 22:27:04 +010028#include <linux/i2c.h>
Ben Hutchings8ceee662008-04-27 12:55:59 +010029
30#include "enum.h"
31#include "bitfield.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010032
Ben Hutchings8ceee662008-04-27 12:55:59 +010033/**************************************************************************
34 *
35 * Build definitions
36 *
37 **************************************************************************/
Ben Hutchingsc5d5f5f2010-06-23 11:30:26 +000038
Ben Hutchings6d84b982011-02-25 00:04:42 +000039#define EFX_DRIVER_VERSION "3.1"
Ben Hutchings8ceee662008-04-27 12:55:59 +010040
Ben Hutchings5f3f9d62011-11-04 22:29:14 +000041#ifdef DEBUG
Ben Hutchings8ceee662008-04-27 12:55:59 +010042#define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
43#define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
44#else
45#define EFX_BUG_ON_PARANOID(x) do {} while (0)
46#define EFX_WARN_ON_PARANOID(x) do {} while (0)
47#endif
48
Ben Hutchings8ceee662008-04-27 12:55:59 +010049/**************************************************************************
50 *
51 * Efx data structures
52 *
53 **************************************************************************/
54
55#define EFX_MAX_CHANNELS 32
Ben Hutchings8ceee662008-04-27 12:55:59 +010056#define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
57
Ben Hutchingsa4900ac2010-04-28 09:30:43 +000058/* Checksum generation is a per-queue option in hardware, so each
59 * queue visible to the networking core is backed by two hardware TX
60 * queues. */
Ben Hutchings94b274b2011-01-10 21:18:20 +000061#define EFX_MAX_TX_TC 2
62#define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
63#define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
64#define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
65#define EFX_TXQ_TYPES 4
66#define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
Ben Hutchings60ac1062008-09-01 12:44:59 +010067
Ben Hutchings8ceee662008-04-27 12:55:59 +010068/**
69 * struct efx_special_buffer - An Efx special buffer
70 * @addr: CPU base address of the buffer
71 * @dma_addr: DMA base address of the buffer
72 * @len: Buffer length, in bytes
73 * @index: Buffer index within controller;s buffer table
74 * @entries: Number of buffer table entries
75 *
76 * Special buffers are used for the event queues and the TX and RX
77 * descriptor queues for each channel. They are *not* used for the
78 * actual transmit and receive buffers.
Ben Hutchings8ceee662008-04-27 12:55:59 +010079 */
80struct efx_special_buffer {
81 void *addr;
82 dma_addr_t dma_addr;
83 unsigned int len;
84 int index;
85 int entries;
86};
87
Ben Hutchings127e6e12009-11-25 16:09:55 +000088enum efx_flush_state {
89 FLUSH_NONE,
90 FLUSH_PENDING,
91 FLUSH_FAILED,
92 FLUSH_DONE,
93};
94
Ben Hutchings8ceee662008-04-27 12:55:59 +010095/**
96 * struct efx_tx_buffer - An Efx TX buffer
97 * @skb: The associated socket buffer.
98 * Set only on the final fragment of a packet; %NULL for all other
99 * fragments. When this fragment completes, then we can free this
100 * skb.
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100101 * @tsoh: The associated TSO header structure, or %NULL if this
102 * buffer is not a TSO header.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100103 * @dma_addr: DMA address of the fragment.
104 * @len: Length of this fragment.
105 * This field is zero when the queue slot is empty.
106 * @continuation: True if this fragment is not the end of a packet.
107 * @unmap_single: True if pci_unmap_single should be used.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100108 * @unmap_len: Length of this fragment to unmap
109 */
110struct efx_tx_buffer {
111 const struct sk_buff *skb;
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100112 struct efx_tso_header *tsoh;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100113 dma_addr_t dma_addr;
114 unsigned short len;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100115 bool continuation;
116 bool unmap_single;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100117 unsigned short unmap_len;
118};
119
120/**
121 * struct efx_tx_queue - An Efx TX queue
122 *
123 * This is a ring buffer of TX fragments.
124 * Since the TX completion path always executes on the same
125 * CPU and the xmit path can operate on different CPUs,
126 * performance is increased by ensuring that the completion
127 * path and the xmit path operate on different cache lines.
128 * This is particularly important if the xmit path is always
129 * executing on one CPU which is different from the completion
130 * path. There is also a cache line for members which are
131 * read but not written on the fast path.
132 *
133 * @efx: The associated Efx NIC
134 * @queue: DMA queue number
Ben Hutchings8ceee662008-04-27 12:55:59 +0100135 * @channel: The associated channel
Ben Hutchingsc04bfc62010-12-10 01:24:16 +0000136 * @core_txq: The networking core TX queue structure
Ben Hutchings8ceee662008-04-27 12:55:59 +0100137 * @buffer: The software buffer ring
138 * @txd: The hardware descriptor ring
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000139 * @ptr_mask: The size of the ring minus 1.
Ben Hutchings94b274b2011-01-10 21:18:20 +0000140 * @initialised: Has hardware queue been initialised?
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100141 * @flushed: Used when handling queue flushing
Ben Hutchings8ceee662008-04-27 12:55:59 +0100142 * @read_count: Current read pointer.
143 * This is the number of buffers that have been removed from both rings.
Ben Hutchingscd385572010-11-15 23:53:11 +0000144 * @old_write_count: The value of @write_count when last checked.
145 * This is here for performance reasons. The xmit path will
146 * only get the up-to-date value of @write_count if this
147 * variable indicates that the queue is empty. This is to
148 * avoid cache-line ping-pong between the xmit path and the
149 * completion path.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100150 * @insert_count: Current insert pointer
151 * This is the number of buffers that have been added to the
152 * software ring.
153 * @write_count: Current write pointer
154 * This is the number of buffers that have been added to the
155 * hardware ring.
156 * @old_read_count: The value of read_count when last checked.
157 * This is here for performance reasons. The xmit path will
158 * only get the up-to-date value of read_count if this
159 * variable indicates that the queue is full. This is to
160 * avoid cache-line ping-pong between the xmit path and the
161 * completion path.
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100162 * @tso_headers_free: A list of TSO headers allocated for this TX queue
163 * that are not in use, and so available for new TSO sends. The list
164 * is protected by the TX queue lock.
165 * @tso_bursts: Number of times TSO xmit invoked by kernel
166 * @tso_long_headers: Number of packets with headers too long for standard
167 * blocks
168 * @tso_packets: Number of packets via the TSO xmit path
Ben Hutchingscd385572010-11-15 23:53:11 +0000169 * @pushes: Number of times the TX push feature has been used
170 * @empty_read_count: If the completion path has seen the queue as empty
171 * and the transmission path has not yet checked this, the value of
172 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100173 */
174struct efx_tx_queue {
175 /* Members which don't change on the fast path */
176 struct efx_nic *efx ____cacheline_aligned_in_smp;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000177 unsigned queue;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100178 struct efx_channel *channel;
Ben Hutchingsc04bfc62010-12-10 01:24:16 +0000179 struct netdev_queue *core_txq;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100180 struct efx_tx_buffer *buffer;
181 struct efx_special_buffer txd;
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000182 unsigned int ptr_mask;
Ben Hutchings94b274b2011-01-10 21:18:20 +0000183 bool initialised;
Ben Hutchings127e6e12009-11-25 16:09:55 +0000184 enum efx_flush_state flushed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100185
186 /* Members used mainly on the completion path */
187 unsigned int read_count ____cacheline_aligned_in_smp;
Ben Hutchingscd385572010-11-15 23:53:11 +0000188 unsigned int old_write_count;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100189
190 /* Members used only on the xmit path */
191 unsigned int insert_count ____cacheline_aligned_in_smp;
192 unsigned int write_count;
193 unsigned int old_read_count;
Ben Hutchingsb9b39b62008-05-07 12:51:12 +0100194 struct efx_tso_header *tso_headers_free;
195 unsigned int tso_bursts;
196 unsigned int tso_long_headers;
197 unsigned int tso_packets;
Ben Hutchingscd385572010-11-15 23:53:11 +0000198 unsigned int pushes;
199
200 /* Members shared between paths and sometimes updated */
201 unsigned int empty_read_count ____cacheline_aligned_in_smp;
202#define EFX_EMPTY_COUNT_VALID 0x80000000
Ben Hutchings8ceee662008-04-27 12:55:59 +0100203};
204
205/**
206 * struct efx_rx_buffer - An Efx RX data buffer
207 * @dma_addr: DMA base address of the buffer
Ben Hutchingsdb339562011-08-26 18:05:11 +0100208 * @skb: The associated socket buffer. Valid iff !(@flags & %EFX_RX_BUF_PAGE).
209 * Will be %NULL if the buffer slot is currently free.
210 * @page: The associated page buffer. Valif iff @flags & %EFX_RX_BUF_PAGE.
211 * Will be %NULL if the buffer slot is currently free.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100212 * @len: Buffer length, in bytes.
Ben Hutchingsdb339562011-08-26 18:05:11 +0100213 * @flags: Flags for buffer and packet state.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100214 */
215struct efx_rx_buffer {
216 dma_addr_t dma_addr;
Steve Hodgson8ba53662011-02-24 23:36:01 +0000217 union {
218 struct sk_buff *skb;
219 struct page *page;
220 } u;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100221 unsigned int len;
Ben Hutchingsdb339562011-08-26 18:05:11 +0100222 u16 flags;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100223};
Ben Hutchingsdb339562011-08-26 18:05:11 +0100224#define EFX_RX_BUF_PAGE 0x0001
225#define EFX_RX_PKT_CSUMMED 0x0002
226#define EFX_RX_PKT_DISCARD 0x0004
Ben Hutchings8ceee662008-04-27 12:55:59 +0100227
228/**
Steve Hodgson62b330b2010-06-01 11:20:53 +0000229 * struct efx_rx_page_state - Page-based rx buffer state
230 *
231 * Inserted at the start of every page allocated for receive buffers.
232 * Used to facilitate sharing dma mappings between recycled rx buffers
233 * and those passed up to the kernel.
234 *
235 * @refcnt: Number of struct efx_rx_buffer's referencing this page.
236 * When refcnt falls to zero, the page is unmapped for dma
237 * @dma_addr: The dma address of this page.
238 */
239struct efx_rx_page_state {
240 unsigned refcnt;
241 dma_addr_t dma_addr;
242
243 unsigned int __pad[0] ____cacheline_aligned;
244};
245
246/**
Ben Hutchings8ceee662008-04-27 12:55:59 +0100247 * struct efx_rx_queue - An Efx RX queue
248 * @efx: The associated Efx NIC
Ben Hutchings8ceee662008-04-27 12:55:59 +0100249 * @buffer: The software buffer ring
250 * @rxd: The hardware descriptor ring
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000251 * @ptr_mask: The size of the ring minus 1.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100252 * @added_count: Number of buffers added to the receive queue.
253 * @notified_count: Number of buffers given to NIC (<= @added_count).
254 * @removed_count: Number of buffers removed from the receive queue.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100255 * @max_fill: RX descriptor maximum fill level (<= ring size)
256 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
257 * (<= @max_fill)
258 * @fast_fill_limit: The level to which a fast fill will fill
259 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
260 * @min_fill: RX descriptor minimum non-zero fill level.
261 * This records the minimum fill level observed when a ring
262 * refill was triggered.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100263 * @alloc_page_count: RX allocation strategy counter.
264 * @alloc_skb_count: RX allocation strategy counter.
Steve Hodgson90d683a2010-06-01 11:19:39 +0000265 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
Ben Hutchings6bc5d3a2008-09-01 12:49:37 +0100266 * @flushed: Use when handling queue flushing
Ben Hutchings8ceee662008-04-27 12:55:59 +0100267 */
268struct efx_rx_queue {
269 struct efx_nic *efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100270 struct efx_rx_buffer *buffer;
271 struct efx_special_buffer rxd;
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000272 unsigned int ptr_mask;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100273
274 int added_count;
275 int notified_count;
276 int removed_count;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100277 unsigned int max_fill;
278 unsigned int fast_fill_trigger;
279 unsigned int fast_fill_limit;
280 unsigned int min_fill;
281 unsigned int min_overfill;
282 unsigned int alloc_page_count;
283 unsigned int alloc_skb_count;
Steve Hodgson90d683a2010-06-01 11:19:39 +0000284 struct timer_list slow_fill;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100285 unsigned int slow_fill_count;
286
Ben Hutchings127e6e12009-11-25 16:09:55 +0000287 enum efx_flush_state flushed;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100288};
289
290/**
291 * struct efx_buffer - An Efx general-purpose buffer
292 * @addr: host base address of the buffer
293 * @dma_addr: DMA base address of the buffer
294 * @len: Buffer length, in bytes
295 *
Ben Hutchings754c6532010-02-03 09:31:57 +0000296 * The NIC uses these buffers for its interrupt status registers and
Ben Hutchings8ceee662008-04-27 12:55:59 +0100297 * MAC stats dumps.
298 */
299struct efx_buffer {
300 void *addr;
301 dma_addr_t dma_addr;
302 unsigned int len;
303};
304
305
Ben Hutchings8ceee662008-04-27 12:55:59 +0100306enum efx_rx_alloc_method {
307 RX_ALLOC_METHOD_AUTO = 0,
308 RX_ALLOC_METHOD_SKB = 1,
309 RX_ALLOC_METHOD_PAGE = 2,
310};
311
312/**
313 * struct efx_channel - An Efx channel
314 *
315 * A channel comprises an event queue, at least one TX queue, at least
316 * one RX queue, and an associated tasklet for processing the event
317 * queue.
318 *
319 * @efx: Associated Efx NIC
Ben Hutchings8ceee662008-04-27 12:55:59 +0100320 * @channel: Channel instance number
Ben Hutchings8ceee662008-04-27 12:55:59 +0100321 * @enabled: Channel enabled indicator
322 * @irq: IRQ number (MSI and MSI-X only)
Ben Hutchings0d86ebd2009-10-23 08:32:13 +0000323 * @irq_moderation: IRQ moderation value (in hardware ticks)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100324 * @napi_dev: Net device used with NAPI
325 * @napi_str: NAPI control structure
Ben Hutchings8ceee662008-04-27 12:55:59 +0100326 * @work_pending: Is work pending via NAPI?
327 * @eventq: Event queue buffer
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000328 * @eventq_mask: Event queue pointer mask
Ben Hutchings8ceee662008-04-27 12:55:59 +0100329 * @eventq_read_ptr: Event queue read pointer
330 * @last_eventq_read_ptr: Last event queue read pointer value.
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000331 * @last_irq_cpu: Last CPU to handle interrupt for this channel
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000332 * @irq_count: Number of IRQs since last adaptive moderation decision
333 * @irq_mod_score: IRQ moderation score
Ben Hutchings8ceee662008-04-27 12:55:59 +0100334 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
335 * and diagnostic counters
336 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
337 * descriptors
Ben Hutchings8ceee662008-04-27 12:55:59 +0100338 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
Ben Hutchings8ceee662008-04-27 12:55:59 +0100339 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
340 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
Ben Hutchingsc1ac4032009-11-28 05:36:29 +0000341 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
Ben Hutchings8ceee662008-04-27 12:55:59 +0100342 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
343 * @n_rx_overlength: Count of RX_OVERLENGTH errors
344 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
Ben Hutchings8313aca2010-09-10 06:41:57 +0000345 * @rx_queue: RX queue for this channel
Ben Hutchings8313aca2010-09-10 06:41:57 +0000346 * @tx_queue: TX queues for this channel
Ben Hutchings8ceee662008-04-27 12:55:59 +0100347 */
348struct efx_channel {
349 struct efx_nic *efx;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100350 int channel;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100351 bool enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100352 int irq;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100353 unsigned int irq_moderation;
354 struct net_device *napi_dev;
355 struct napi_struct napi_str;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100356 bool work_pending;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100357 struct efx_special_buffer eventq;
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000358 unsigned int eventq_mask;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100359 unsigned int eventq_read_ptr;
360 unsigned int last_eventq_read_ptr;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100361
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000362 int last_irq_cpu;
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000363 unsigned int irq_count;
364 unsigned int irq_mod_score;
Ben Hutchings64d8ad62011-01-05 00:50:41 +0000365#ifdef CONFIG_RFS_ACCEL
366 unsigned int rfs_filters_added;
367#endif
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000368
Ben Hutchings8ceee662008-04-27 12:55:59 +0100369 int rx_alloc_level;
370 int rx_alloc_push_pages;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100371
372 unsigned n_rx_tobe_disc;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100373 unsigned n_rx_ip_hdr_chksum_err;
374 unsigned n_rx_tcp_udp_chksum_err;
Ben Hutchingsc1ac4032009-11-28 05:36:29 +0000375 unsigned n_rx_mcast_mismatch;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100376 unsigned n_rx_frm_trunc;
377 unsigned n_rx_overlength;
378 unsigned n_skbuff_leaks;
379
380 /* Used to pipeline received packets in order to optimise memory
381 * access with prefetches.
382 */
383 struct efx_rx_buffer *rx_pkt;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100384
Ben Hutchings8313aca2010-09-10 06:41:57 +0000385 struct efx_rx_queue rx_queue;
Ben Hutchings94b274b2011-01-10 21:18:20 +0000386 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100387};
388
Ben Hutchings398468e2009-11-23 16:03:45 +0000389enum efx_led_mode {
390 EFX_LED_OFF = 0,
391 EFX_LED_ON = 1,
392 EFX_LED_DEFAULT = 2
393};
394
Ben Hutchingsc4593022009-11-23 16:08:17 +0000395#define STRING_TABLE_LOOKUP(val, member) \
396 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
397
Ben Hutchings18e83e42012-01-05 19:05:20 +0000398extern const char *const efx_loopback_mode_names[];
Ben Hutchingsc4593022009-11-23 16:08:17 +0000399extern const unsigned int efx_loopback_mode_max;
400#define LOOPBACK_MODE(efx) \
401 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
402
Ben Hutchings18e83e42012-01-05 19:05:20 +0000403extern const char *const efx_reset_type_names[];
Ben Hutchingsc4593022009-11-23 16:08:17 +0000404extern const unsigned int efx_reset_type_max;
405#define RESET_TYPE(type) \
406 STRING_TABLE_LOOKUP(type, efx_reset_type)
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100407
Ben Hutchings8ceee662008-04-27 12:55:59 +0100408enum efx_int_mode {
409 /* Be careful if altering to correct macro below */
410 EFX_INT_MODE_MSIX = 0,
411 EFX_INT_MODE_MSI = 1,
412 EFX_INT_MODE_LEGACY = 2,
413 EFX_INT_MODE_MAX /* Insert any new items before this */
414};
415#define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
416
Ben Hutchings8ceee662008-04-27 12:55:59 +0100417enum nic_state {
418 STATE_INIT = 0,
419 STATE_RUNNING = 1,
420 STATE_FINI = 2,
Ben Hutchings3c787082008-09-01 12:49:08 +0100421 STATE_DISABLED = 3,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100422 STATE_MAX,
423};
424
425/*
426 * Alignment of page-allocated RX buffers
427 *
428 * Controls the number of bytes inserted at the start of an RX buffer.
429 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
430 * of the skb->head for hardware DMA].
431 */
Ben Hutchings13e9ab12008-09-01 12:50:28 +0100432#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Ben Hutchings8ceee662008-04-27 12:55:59 +0100433#define EFX_PAGE_IP_ALIGN 0
434#else
435#define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
436#endif
437
438/*
439 * Alignment of the skb->head which wraps a page-allocated RX buffer
440 *
441 * The skb allocated to wrap an rx_buffer can have this alignment. Since
442 * the data is memcpy'd from the rx_buf, it does not need to be equal to
443 * EFX_PAGE_IP_ALIGN.
444 */
445#define EFX_PAGE_SKB_ALIGN 2
446
447/* Forward declaration */
448struct efx_nic;
449
450/* Pseudo bit-mask flow control field */
David S. Millerb56269462011-05-17 17:53:22 -0400451#define EFX_FC_RX FLOW_CTRL_RX
452#define EFX_FC_TX FLOW_CTRL_TX
453#define EFX_FC_AUTO 4
Ben Hutchings8ceee662008-04-27 12:55:59 +0100454
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800455/**
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000456 * struct efx_link_state - Current state of the link
457 * @up: Link is up
458 * @fd: Link is full-duplex
459 * @fc: Actual flow control flags
460 * @speed: Link speed (Mbps)
461 */
462struct efx_link_state {
463 bool up;
464 bool fd;
David S. Millerb56269462011-05-17 17:53:22 -0400465 u8 fc;
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000466 unsigned int speed;
467};
468
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000469static inline bool efx_link_state_equal(const struct efx_link_state *left,
470 const struct efx_link_state *right)
471{
472 return left->up == right->up && left->fd == right->fd &&
473 left->fc == right->fc && left->speed == right->speed;
474}
475
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000476/**
Ben Hutchings8ceee662008-04-27 12:55:59 +0100477 * struct efx_phy_operations - Efx PHY operations table
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000478 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
479 * efx->loopback_modes.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100480 * @init: Initialise PHY
481 * @fini: Shut down PHY
482 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000483 * @poll: Update @link_state and report whether it changed.
484 * Serialised by the mac_lock.
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800485 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
486 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000487 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800488 * (only needed where AN bit is set in mmds)
Ben Hutchings4f16c072010-02-03 09:30:50 +0000489 * @test_alive: Test that PHY is 'alive' (online)
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000490 * @test_name: Get the name of a PHY-specific test/result
Ben Hutchings4f16c072010-02-03 09:30:50 +0000491 * @run_tests: Run tests and record results as appropriate (offline).
Ben Hutchings17967212008-12-26 13:47:25 -0800492 * Flags are the ethtool tests flags.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100493 */
494struct efx_phy_operations {
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000495 int (*probe) (struct efx_nic *efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100496 int (*init) (struct efx_nic *efx);
497 void (*fini) (struct efx_nic *efx);
Steve Hodgsonff3b00a2009-12-23 13:46:36 +0000498 void (*remove) (struct efx_nic *efx);
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000499 int (*reconfigure) (struct efx_nic *efx);
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000500 bool (*poll) (struct efx_nic *efx);
Ben Hutchings177dfcd2008-12-12 21:50:08 -0800501 void (*get_settings) (struct efx_nic *efx,
502 struct ethtool_cmd *ecmd);
503 int (*set_settings) (struct efx_nic *efx,
504 struct ethtool_cmd *ecmd);
Ben Hutchingsaf4ad9b2009-01-29 17:59:37 +0000505 void (*set_npage_adv) (struct efx_nic *efx, u32);
Ben Hutchings4f16c072010-02-03 09:30:50 +0000506 int (*test_alive) (struct efx_nic *efx);
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000507 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
Ben Hutchings17967212008-12-26 13:47:25 -0800508 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100509};
510
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100511/**
512 * @enum efx_phy_mode - PHY operating mode flags
513 * @PHY_MODE_NORMAL: on and should pass traffic
514 * @PHY_MODE_TX_DISABLED: on with TX disabled
Ben Hutchings3e133c42008-11-04 20:34:56 +0000515 * @PHY_MODE_LOW_POWER: set to low power through MDIO
516 * @PHY_MODE_OFF: switched off through external control
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100517 * @PHY_MODE_SPECIAL: on but will not pass traffic
518 */
519enum efx_phy_mode {
520 PHY_MODE_NORMAL = 0,
521 PHY_MODE_TX_DISABLED = 1,
Ben Hutchings3e133c42008-11-04 20:34:56 +0000522 PHY_MODE_LOW_POWER = 2,
523 PHY_MODE_OFF = 4,
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100524 PHY_MODE_SPECIAL = 8,
525};
526
527static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
528{
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100529 return !!(mode & ~PHY_MODE_TX_DISABLED);
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100530}
531
Ben Hutchings8ceee662008-04-27 12:55:59 +0100532/*
533 * Efx extended statistics
534 *
535 * Not all statistics are provided by all supported MACs. The purpose
536 * is this structure is to contain the raw statistics provided by each
537 * MAC.
538 */
539struct efx_mac_stats {
540 u64 tx_bytes;
541 u64 tx_good_bytes;
542 u64 tx_bad_bytes;
Ben Hutchingsf9c76252011-10-12 17:20:25 +0100543 u64 tx_packets;
544 u64 tx_bad;
545 u64 tx_pause;
546 u64 tx_control;
547 u64 tx_unicast;
548 u64 tx_multicast;
549 u64 tx_broadcast;
550 u64 tx_lt64;
551 u64 tx_64;
552 u64 tx_65_to_127;
553 u64 tx_128_to_255;
554 u64 tx_256_to_511;
555 u64 tx_512_to_1023;
556 u64 tx_1024_to_15xx;
557 u64 tx_15xx_to_jumbo;
558 u64 tx_gtjumbo;
559 u64 tx_collision;
560 u64 tx_single_collision;
561 u64 tx_multiple_collision;
562 u64 tx_excessive_collision;
563 u64 tx_deferred;
564 u64 tx_late_collision;
565 u64 tx_excessive_deferred;
566 u64 tx_non_tcpudp;
567 u64 tx_mac_src_error;
568 u64 tx_ip_src_error;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100569 u64 rx_bytes;
570 u64 rx_good_bytes;
571 u64 rx_bad_bytes;
Ben Hutchingsf9c76252011-10-12 17:20:25 +0100572 u64 rx_packets;
573 u64 rx_good;
574 u64 rx_bad;
575 u64 rx_pause;
576 u64 rx_control;
577 u64 rx_unicast;
578 u64 rx_multicast;
579 u64 rx_broadcast;
580 u64 rx_lt64;
581 u64 rx_64;
582 u64 rx_65_to_127;
583 u64 rx_128_to_255;
584 u64 rx_256_to_511;
585 u64 rx_512_to_1023;
586 u64 rx_1024_to_15xx;
587 u64 rx_15xx_to_jumbo;
588 u64 rx_gtjumbo;
589 u64 rx_bad_lt64;
590 u64 rx_bad_64_to_15xx;
591 u64 rx_bad_15xx_to_jumbo;
592 u64 rx_bad_gtjumbo;
593 u64 rx_overflow;
594 u64 rx_missed;
595 u64 rx_false_carrier;
596 u64 rx_symbol_error;
597 u64 rx_align_error;
598 u64 rx_length_error;
599 u64 rx_internal_error;
600 u64 rx_good_lt64;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100601};
602
603/* Number of bits used in a multicast filter hash address */
604#define EFX_MCAST_HASH_BITS 8
605
606/* Number of (single-bit) entries in a multicast filter hash */
607#define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
608
609/* An Efx multicast filter hash */
610union efx_multicast_hash {
611 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
612 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
613};
614
Ben Hutchings64eebcf2010-09-20 08:43:07 +0000615struct efx_filter_state;
616
Ben Hutchings8ceee662008-04-27 12:55:59 +0100617/**
618 * struct efx_nic - an Efx NIC
619 * @name: Device name (net device name or bus id before net device registered)
620 * @pci_dev: The PCI device
621 * @type: Controller type attributes
622 * @legacy_irq: IRQ number
Ben Hutchings94dec6a2010-12-07 19:24:45 +0000623 * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)?
Ben Hutchings8d9853d2008-07-18 19:01:20 +0100624 * @workqueue: Workqueue for port reconfigures and the HW monitor.
625 * Work items do not hold and must not acquire RTNL.
Ben Hutchings6977dc62008-12-26 13:44:39 -0800626 * @workqueue_name: Name of workqueue
Ben Hutchings8ceee662008-04-27 12:55:59 +0100627 * @reset_work: Scheduled reset workitem
Ben Hutchings8ceee662008-04-27 12:55:59 +0100628 * @membase_phys: Memory BAR value as physical address
629 * @membase: Memory BAR value
Ben Hutchings8ceee662008-04-27 12:55:59 +0100630 * @interrupt_mode: Interrupt mode
Ben Hutchingscc180b62011-12-08 19:51:47 +0000631 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000632 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
633 * @irq_rx_moderation: IRQ moderation time for RX event queues
Ben Hutchings62776d02010-06-23 11:30:07 +0000634 * @msg_enable: Log message enable flags
Ben Hutchings8ceee662008-04-27 12:55:59 +0100635 * @state: Device state flag. Serialised by the rtnl_lock.
Ben Hutchingsa7d529a2011-06-24 20:46:31 +0100636 * @reset_pending: Bitmask for pending resets
Ben Hutchings8ceee662008-04-27 12:55:59 +0100637 * @tx_queue: TX DMA queues
638 * @rx_queue: RX DMA queues
639 * @channel: Channels
Ben Hutchings46426102010-09-10 06:42:33 +0000640 * @channel_name: Names for channels and their IRQs
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000641 * @rxq_entries: Size of receive queues requested by user.
642 * @txq_entries: Size of transmit queues requested by user.
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000643 * @next_buffer_table: First available buffer table id
Neil Turton28b581a2008-12-12 21:41:06 -0800644 * @n_channels: Number of channels in use
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000645 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
646 * @n_tx_channels: Number of channels used for TX
Ben Hutchings8ceee662008-04-27 12:55:59 +0100647 * @rx_buffer_len: RX buffer length
648 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
Ben Hutchings78d41892010-12-02 13:47:56 +0000649 * @rx_hash_key: Toeplitz hash key for RSS
Ben Hutchings765c9f42010-06-30 05:06:28 +0000650 * @rx_indir_table: Indirection table for RSS
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000651 * @int_error_count: Number of internal errors seen recently
652 * @int_error_expire: Time at which error count will be expired
Ben Hutchings8ceee662008-04-27 12:55:59 +0100653 * @irq_status: Interrupt status buffer
Ben Hutchingsc28884c2010-04-28 09:30:00 +0000654 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000655 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
Ben Hutchings76884832009-11-29 15:10:44 +0000656 * @mtd_list: List of MTDs attached to the NIC
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300657 * @nic_data: Hardware dependent state
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100658 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
Ben Hutchingse4abce82011-05-16 18:51:24 +0100659 * efx_monitor() and efx_reconfigure_port()
Ben Hutchings8ceee662008-04-27 12:55:59 +0100660 * @port_enabled: Port enabled indicator.
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000661 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
662 * efx_mac_work() with kernel interfaces. Safe to read under any
663 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
664 * be held to modify it.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100665 * @port_initialized: Port initialized?
666 * @net_dev: Operating system network device. Consider holding the rtnl lock
Ben Hutchings8ceee662008-04-27 12:55:59 +0100667 * @stats_buffer: DMA buffer for statistics
Ben Hutchings8ceee662008-04-27 12:55:59 +0100668 * @phy_type: PHY type
Ben Hutchings8ceee662008-04-27 12:55:59 +0100669 * @phy_op: PHY interface
670 * @phy_data: PHY private data (including PHY-specific stats)
Ben Hutchings68e7f452009-04-29 08:05:08 +0000671 * @mdio: PHY MDIO interface
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000672 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
Ben Hutchings8c8661e2008-09-01 12:49:02 +0100673 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000674 * @link_advertising: Autonegotiation advertising flags
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000675 * @link_state: Current state of the link
Ben Hutchings8ceee662008-04-27 12:55:59 +0100676 * @n_link_state_changes: Number of times the link has changed state
677 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
678 * @multicast_hash: Multicast hash table
Ben Hutchings04cc8ca2008-12-12 21:50:46 -0800679 * @wanted_fc: Wanted flow control flags
Ben Hutchings8be4f3e2009-11-25 16:12:16 +0000680 * @mac_work: Work item for changing MAC promiscuity and multicast hash
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100681 * @loopback_mode: Loopback status
682 * @loopback_modes: Supported loopback mode bitmask
683 * @loopback_selftest: Offline self-test private state
Ben Hutchingsab28c122010-12-06 22:53:15 +0000684 * @monitor_work: Hardware monitor workitem
685 * @biu_lock: BIU (bus interface unit) lock
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000686 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
687 * field is used by efx_test_interrupts() to verify that an
688 * interrupt has occurred.
Ben Hutchingsab28c122010-12-06 22:53:15 +0000689 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
690 * @mac_stats: MAC statistics. These include all statistics the MACs
691 * can provide. Generic code converts these into a standard
692 * &struct net_device_stats.
693 * @stats_lock: Statistics update lock. Serialises statistics fetches
Ben Hutchings1cb34522011-09-02 23:23:00 +0100694 * and access to @mac_stats.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100695 *
Ben Hutchings754c6532010-02-03 09:31:57 +0000696 * This is stored in the private area of the &struct net_device.
Ben Hutchings8ceee662008-04-27 12:55:59 +0100697 */
698struct efx_nic {
Ben Hutchingsab28c122010-12-06 22:53:15 +0000699 /* The following fields should be written very rarely */
700
Ben Hutchings8ceee662008-04-27 12:55:59 +0100701 char name[IFNAMSIZ];
702 struct pci_dev *pci_dev;
703 const struct efx_nic_type *type;
704 int legacy_irq;
Ben Hutchings94dec6a2010-12-07 19:24:45 +0000705 bool legacy_irq_enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100706 struct workqueue_struct *workqueue;
Ben Hutchings6977dc62008-12-26 13:44:39 -0800707 char workqueue_name[16];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100708 struct work_struct reset_work;
Ben Hutchings086ea352008-05-16 21:17:06 +0100709 resource_size_t membase_phys;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100710 void __iomem *membase;
Ben Hutchingsab28c122010-12-06 22:53:15 +0000711
Ben Hutchings8ceee662008-04-27 12:55:59 +0100712 enum efx_int_mode interrupt_mode;
Ben Hutchingscc180b62011-12-08 19:51:47 +0000713 unsigned int timer_quantum_ns;
Ben Hutchings6fb70fd2009-03-20 13:30:37 +0000714 bool irq_rx_adaptive;
715 unsigned int irq_rx_moderation;
Ben Hutchings62776d02010-06-23 11:30:07 +0000716 u32 msg_enable;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100717
Ben Hutchings8ceee662008-04-27 12:55:59 +0100718 enum nic_state state;
Ben Hutchingsa7d529a2011-06-24 20:46:31 +0100719 unsigned long reset_pending;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100720
Ben Hutchings8313aca2010-09-10 06:41:57 +0000721 struct efx_channel *channel[EFX_MAX_CHANNELS];
Ben Hutchingsefbc2d72010-09-13 04:14:49 +0000722 char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100723
Steve Hodgsonecc910f2010-09-10 06:42:22 +0000724 unsigned rxq_entries;
725 unsigned txq_entries;
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000726 unsigned next_buffer_table;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000727 unsigned n_channels;
728 unsigned n_rx_channels;
Ben Hutchings97653432011-01-12 18:26:56 +0000729 unsigned tx_channel_offset;
Ben Hutchingsa4900ac2010-04-28 09:30:43 +0000730 unsigned n_tx_channels;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100731 unsigned int rx_buffer_len;
732 unsigned int rx_buffer_order;
Ben Hutchings5d3a6fc2010-06-25 07:05:43 +0000733 u8 rx_hash_key[40];
Ben Hutchings765c9f42010-06-30 05:06:28 +0000734 u32 rx_indir_table[128];
Ben Hutchings8ceee662008-04-27 12:55:59 +0100735
Ben Hutchings0484e0d2009-10-23 08:32:04 +0000736 unsigned int_error_count;
737 unsigned long int_error_expire;
738
Ben Hutchings8ceee662008-04-27 12:55:59 +0100739 struct efx_buffer irq_status;
Ben Hutchingsc28884c2010-04-28 09:30:00 +0000740 unsigned irq_zero_count;
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000741 unsigned irq_level;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100742
Ben Hutchings76884832009-11-29 15:10:44 +0000743#ifdef CONFIG_SFC_MTD
744 struct list_head mtd_list;
745#endif
Ben Hutchings4a5b5042008-09-01 12:47:16 +0100746
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000747 void *nic_data;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100748
749 struct mutex mac_lock;
Ben Hutchings766ca0f2008-12-12 21:59:24 -0800750 struct work_struct mac_work;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100751 bool port_enabled;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100752
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100753 bool port_initialized;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100754 struct net_device *net_dev;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100755
Ben Hutchings8ceee662008-04-27 12:55:59 +0100756 struct efx_buffer stats_buffer;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100757
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000758 unsigned int phy_type;
stephen hemminger6c8c2512011-04-14 05:50:12 +0000759 const struct efx_phy_operations *phy_op;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100760 void *phy_data;
Ben Hutchings68e7f452009-04-29 08:05:08 +0000761 struct mdio_if_info mdio;
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000762 unsigned int mdio_bus;
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100763 enum efx_phy_mode phy_mode;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100764
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000765 u32 link_advertising;
Ben Hutchingseb50c0d2009-11-23 16:06:30 +0000766 struct efx_link_state link_state;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100767 unsigned int n_link_state_changes;
768
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100769 bool promiscuous;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100770 union efx_multicast_hash multicast_hash;
David S. Millerb56269462011-05-17 17:53:22 -0400771 u8 wanted_fc;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100772
773 atomic_t rx_reset;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100774 enum efx_loopback_mode loopback_mode;
Ben Hutchingse58f69f2009-11-29 15:08:41 +0000775 u64 loopback_modes;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100776
777 void *loopback_selftest;
Ben Hutchings64eebcf2010-09-20 08:43:07 +0000778
779 struct efx_filter_state *filter_state;
Ben Hutchingsab28c122010-12-06 22:53:15 +0000780
781 /* The following fields may be written more often */
782
783 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
784 spinlock_t biu_lock;
Ben Hutchings1646a6f2012-01-05 20:14:10 +0000785 int last_irq_cpu;
Ben Hutchingsab28c122010-12-06 22:53:15 +0000786 unsigned n_rx_nodesc_drop_cnt;
787 struct efx_mac_stats mac_stats;
788 spinlock_t stats_lock;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100789};
790
Ben Hutchings55668612008-05-16 21:16:10 +0100791static inline int efx_dev_registered(struct efx_nic *efx)
792{
793 return efx->net_dev->reg_state == NETREG_REGISTERED;
794}
795
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000796static inline unsigned int efx_port_num(struct efx_nic *efx)
797{
Ben Hutchings3df95ce2010-06-02 10:39:56 +0000798 return efx->net_dev->dev_id;
Ben Hutchings8880f4e2009-11-29 15:15:41 +0000799}
800
Ben Hutchings8ceee662008-04-27 12:55:59 +0100801/**
802 * struct efx_nic_type - Efx device type definition
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000803 * @probe: Probe the controller
804 * @remove: Free resources allocated by probe()
805 * @init: Initialise the controller
806 * @fini: Shut down the controller
807 * @monitor: Periodic function for polling link state and hardware monitor
Ben Hutchings0e2a9c72011-06-24 20:50:07 +0100808 * @map_reset_reason: Map ethtool reset reason to a reset method
809 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000810 * @reset: Reset the controller hardware and possibly the PHY. This will
811 * be called while the controller is uninitialised.
812 * @probe_port: Probe the MAC and PHY
813 * @remove_port: Free resources allocated by probe_port()
Ben Hutchings40641ed2010-12-02 13:47:45 +0000814 * @handle_global_event: Handle a "global" event (may be %NULL)
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000815 * @prepare_flush: Prepare the hardware for flushing the DMA queues
816 * @update_stats: Update statistics not provided by event handling
817 * @start_stats: Start the regular fetching of statistics
818 * @stop_stats: Stop the regular fetching of statistics
Ben Hutchings06629f02009-11-29 03:43:43 +0000819 * @set_id_led: Set state of identifying LED or revert to automatic function
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000820 * @push_irq_moderation: Apply interrupt moderation value
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000821 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
Ben Hutchings30b81cd2011-09-13 19:47:48 +0100822 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
823 * to the hardware. Serialised by the mac_lock.
Ben Hutchings710b2082011-09-03 00:15:00 +0100824 * @check_mac_fault: Check MAC fault state. True if fault present.
Ben Hutchings89c758f2009-11-29 03:43:07 +0000825 * @get_wol: Get WoL configuration from driver state
826 * @set_wol: Push WoL configuration to the NIC
827 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
Ben Hutchings9bfc4bb2009-11-29 03:43:23 +0000828 * @test_registers: Test read/write functionality of control registers
Ben Hutchings0aa3fba2009-11-29 03:43:33 +0000829 * @test_nvram: Test validity of NVRAM contents
Ben Hutchingsdaeda632009-11-28 05:36:04 +0000830 * @revision: Hardware architecture revision
Ben Hutchings8ceee662008-04-27 12:55:59 +0100831 * @mem_map_size: Memory BAR mapped size
832 * @txd_ptr_tbl_base: TX descriptor ring base address
833 * @rxd_ptr_tbl_base: RX descriptor ring base address
834 * @buf_tbl_base: Buffer table base address
835 * @evq_ptr_tbl_base: Event queue pointer table base address
836 * @evq_rptr_tbl_base: Event queue read-pointer table base address
Ben Hutchings8ceee662008-04-27 12:55:59 +0100837 * @max_dma_mask: Maximum possible DMA mask
Ben Hutchings39c9cf02010-06-23 11:31:28 +0000838 * @rx_buffer_hash_size: Size of hash at start of RX buffer
839 * @rx_buffer_padding: Size of padding at end of RX buffer
Ben Hutchings8ceee662008-04-27 12:55:59 +0100840 * @max_interrupt_mode: Highest capability interrupt mode supported
841 * from &enum efx_init_mode.
842 * @phys_addr_channels: Number of channels with physically addressed
843 * descriptors
Ben Hutchingscc180b62011-12-08 19:51:47 +0000844 * @timer_period_max: Maximum period of interrupt timer (in ticks)
Ben Hutchings0228f5cdb02009-11-28 05:36:12 +0000845 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
846 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
Ben Hutchingsc383b532009-11-29 15:11:02 +0000847 * @offload_features: net_device feature flags for protocol offload
848 * features implemented in hardware
Ben Hutchings8ceee662008-04-27 12:55:59 +0100849 */
850struct efx_nic_type {
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000851 int (*probe)(struct efx_nic *efx);
852 void (*remove)(struct efx_nic *efx);
853 int (*init)(struct efx_nic *efx);
854 void (*fini)(struct efx_nic *efx);
855 void (*monitor)(struct efx_nic *efx);
Ben Hutchings0e2a9c72011-06-24 20:50:07 +0100856 enum reset_type (*map_reset_reason)(enum reset_type reason);
857 int (*map_reset_flags)(u32 *flags);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000858 int (*reset)(struct efx_nic *efx, enum reset_type method);
859 int (*probe_port)(struct efx_nic *efx);
860 void (*remove_port)(struct efx_nic *efx);
Ben Hutchings40641ed2010-12-02 13:47:45 +0000861 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000862 void (*prepare_flush)(struct efx_nic *efx);
863 void (*update_stats)(struct efx_nic *efx);
864 void (*start_stats)(struct efx_nic *efx);
865 void (*stop_stats)(struct efx_nic *efx);
Ben Hutchings06629f02009-11-29 03:43:43 +0000866 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
Ben Hutchingsef2b90e2009-11-29 03:42:31 +0000867 void (*push_irq_moderation)(struct efx_channel *channel);
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000868 int (*reconfigure_port)(struct efx_nic *efx);
Ben Hutchings710b2082011-09-03 00:15:00 +0100869 int (*reconfigure_mac)(struct efx_nic *efx);
870 bool (*check_mac_fault)(struct efx_nic *efx);
Ben Hutchings89c758f2009-11-29 03:43:07 +0000871 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
872 int (*set_wol)(struct efx_nic *efx, u32 type);
873 void (*resume_wol)(struct efx_nic *efx);
Ben Hutchings9bfc4bb2009-11-29 03:43:23 +0000874 int (*test_registers)(struct efx_nic *efx);
Ben Hutchings0aa3fba2009-11-29 03:43:33 +0000875 int (*test_nvram)(struct efx_nic *efx);
Steve Hodgsonb895d732009-11-28 05:35:00 +0000876
Ben Hutchingsdaeda632009-11-28 05:36:04 +0000877 int revision;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100878 unsigned int mem_map_size;
879 unsigned int txd_ptr_tbl_base;
880 unsigned int rxd_ptr_tbl_base;
881 unsigned int buf_tbl_base;
882 unsigned int evq_ptr_tbl_base;
883 unsigned int evq_rptr_tbl_base;
Ben Hutchings9bbd7d92008-05-16 21:18:48 +0100884 u64 max_dma_mask;
Ben Hutchings39c9cf02010-06-23 11:31:28 +0000885 unsigned int rx_buffer_hash_size;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100886 unsigned int rx_buffer_padding;
887 unsigned int max_interrupt_mode;
888 unsigned int phys_addr_channels;
Ben Hutchingscc180b62011-12-08 19:51:47 +0000889 unsigned int timer_period_max;
Ben Hutchings0228f5cdb02009-11-28 05:36:12 +0000890 unsigned int tx_dc_base;
891 unsigned int rx_dc_base;
Michał Mirosławc8f44af2011-11-15 15:29:55 +0000892 netdev_features_t offload_features;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100893};
894
895/**************************************************************************
896 *
897 * Prototypes and inline functions
898 *
899 *************************************************************************/
900
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000901static inline struct efx_channel *
902efx_get_channel(struct efx_nic *efx, unsigned index)
903{
904 EFX_BUG_ON_PARANOID(index >= efx->n_channels);
Ben Hutchings8313aca2010-09-10 06:41:57 +0000905 return efx->channel[index];
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000906}
907
Ben Hutchings8ceee662008-04-27 12:55:59 +0100908/* Iterate over all used channels */
909#define efx_for_each_channel(_channel, _efx) \
Ben Hutchings8313aca2010-09-10 06:41:57 +0000910 for (_channel = (_efx)->channel[0]; \
911 _channel; \
912 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
913 (_efx)->channel[_channel->channel + 1] : NULL)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100914
Ben Hutchings97653432011-01-12 18:26:56 +0000915static inline struct efx_tx_queue *
916efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
917{
918 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels ||
919 type >= EFX_TXQ_TYPES);
920 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
921}
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000922
Ben Hutchings525da902011-02-07 23:04:38 +0000923static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
924{
925 return channel->channel - channel->efx->tx_channel_offset <
926 channel->efx->n_tx_channels;
927}
928
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000929static inline struct efx_tx_queue *
930efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
931{
Ben Hutchings525da902011-02-07 23:04:38 +0000932 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) ||
933 type >= EFX_TXQ_TYPES);
934 return &channel->tx_queue[type];
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000935}
Ben Hutchings8ceee662008-04-27 12:55:59 +0100936
Ben Hutchings94b274b2011-01-10 21:18:20 +0000937static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
938{
939 return !(tx_queue->efx->net_dev->num_tc < 2 &&
940 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
941}
942
Ben Hutchings8ceee662008-04-27 12:55:59 +0100943/* Iterate over all TX queues belonging to a channel */
944#define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
Ben Hutchings525da902011-02-07 23:04:38 +0000945 if (!efx_channel_has_tx_queues(_channel)) \
946 ; \
947 else \
948 for (_tx_queue = (_channel)->tx_queue; \
Ben Hutchings94b274b2011-01-10 21:18:20 +0000949 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
950 efx_tx_queue_used(_tx_queue); \
Ben Hutchings525da902011-02-07 23:04:38 +0000951 _tx_queue++)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100952
Ben Hutchings94b274b2011-01-10 21:18:20 +0000953/* Iterate over all possible TX queues belonging to a channel */
954#define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
955 for (_tx_queue = (_channel)->tx_queue; \
956 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
957 _tx_queue++)
958
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000959static inline struct efx_rx_queue *
960efx_get_rx_queue(struct efx_nic *efx, unsigned index)
961{
962 EFX_BUG_ON_PARANOID(index >= efx->n_rx_channels);
Ben Hutchings8313aca2010-09-10 06:41:57 +0000963 return &efx->channel[index]->rx_queue;
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000964}
965
Ben Hutchings525da902011-02-07 23:04:38 +0000966static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
967{
968 return channel->channel < channel->efx->n_rx_channels;
969}
970
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000971static inline struct efx_rx_queue *
972efx_channel_get_rx_queue(struct efx_channel *channel)
973{
Ben Hutchings525da902011-02-07 23:04:38 +0000974 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel));
975 return &channel->rx_queue;
Ben Hutchingsf7d12cd2010-09-10 06:41:47 +0000976}
977
Ben Hutchings8ceee662008-04-27 12:55:59 +0100978/* Iterate over all RX queues belonging to a channel */
979#define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
Ben Hutchings525da902011-02-07 23:04:38 +0000980 if (!efx_channel_has_rx_queue(_channel)) \
981 ; \
982 else \
983 for (_rx_queue = &(_channel)->rx_queue; \
984 _rx_queue; \
985 _rx_queue = NULL)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100986
Ben Hutchingsba1e8a32010-09-10 06:41:36 +0000987static inline struct efx_channel *
988efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
989{
Ben Hutchings8313aca2010-09-10 06:41:57 +0000990 return container_of(rx_queue, struct efx_channel, rx_queue);
Ben Hutchingsba1e8a32010-09-10 06:41:36 +0000991}
992
993static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
994{
Ben Hutchings8313aca2010-09-10 06:41:57 +0000995 return efx_rx_queue_channel(rx_queue)->channel;
Ben Hutchingsba1e8a32010-09-10 06:41:36 +0000996}
997
Ben Hutchings8ceee662008-04-27 12:55:59 +0100998/* Returns a pointer to the specified receive buffer in the RX
999 * descriptor queue.
1000 */
1001static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1002 unsigned int index)
1003{
Eric Dumazet807540b2010-09-23 05:40:09 +00001004 return &rx_queue->buffer[index];
Ben Hutchings8ceee662008-04-27 12:55:59 +01001005}
1006
1007/* Set bit in a little-endian bitfield */
Ben Hutchings18c2fc02008-09-01 12:43:39 +01001008static inline void set_bit_le(unsigned nr, unsigned char *addr)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001009{
1010 addr[nr / 8] |= (1 << (nr % 8));
1011}
1012
1013/* Clear bit in a little-endian bitfield */
Ben Hutchings18c2fc02008-09-01 12:43:39 +01001014static inline void clear_bit_le(unsigned nr, unsigned char *addr)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001015{
1016 addr[nr / 8] &= ~(1 << (nr % 8));
1017}
1018
1019
1020/**
1021 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1022 *
1023 * This calculates the maximum frame length that will be used for a
1024 * given MTU. The frame length will be equal to the MTU plus a
1025 * constant amount of header space and padding. This is the quantity
1026 * that the net driver will program into the MAC as the maximum frame
1027 * length.
1028 *
Ben Hutchings754c6532010-02-03 09:31:57 +00001029 * The 10G MAC requires 8-byte alignment on the frame
Ben Hutchings8ceee662008-04-27 12:55:59 +01001030 * length, so we round up to the nearest 8.
Ben Hutchingscc117632009-08-26 08:17:59 +00001031 *
1032 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1033 * XGMII cycle). If the frame length reaches the maximum value in the
1034 * same cycle, the XMAC can miss the IPG altogether. We work around
1035 * this by adding a further 16 bytes.
Ben Hutchings8ceee662008-04-27 12:55:59 +01001036 */
1037#define EFX_MAX_FRAME_LEN(mtu) \
Ben Hutchingscc117632009-08-26 08:17:59 +00001038 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
Ben Hutchings8ceee662008-04-27 12:55:59 +01001039
1040
1041#endif /* EFX_NET_DRIVER_H */