Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2000 Deep Blue Solutions Ltd |
| 3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) |
| 4 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/serial_8250.h> |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 21 | #include <linux/gpio.h> |
| 22 | #include <linux/i2c.h> |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 23 | #include <linux/irq.h> |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 24 | #include <linux/irqdomain.h> |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 25 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 26 | #include <asm/mach-types.h> |
| 27 | #include <asm/mach/arch.h> |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 28 | #include <asm/mach/time.h> |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 29 | #include <asm/memory.h> |
| 30 | #include <asm/mach/map.h> |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 31 | |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 32 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 |
| 33 | #include <linux/mfd/wm8350/audio.h> |
| 34 | #include <linux/mfd/wm8350/core.h> |
| 35 | #include <linux/mfd/wm8350/pmic.h> |
| 36 | #endif |
| 37 | |
Shawn Guo | e337247 | 2012-09-13 21:01:00 +0800 | [diff] [blame] | 38 | #include "common.h" |
Uwe Kleine-König | 4a9b8b0 | 2010-06-16 18:03:05 +0200 | [diff] [blame] | 39 | #include "devices-imx31.h" |
Shawn Guo | 50f2de6 | 2012-09-14 14:14:45 +0800 | [diff] [blame] | 40 | #include "hardware.h" |
Shawn Guo | 267dd34 | 2012-09-13 13:26:00 +0800 | [diff] [blame] | 41 | #include "iomux-mx3.h" |
Sascha Hauer | 2eca047 | 2008-10-17 16:10:38 +0200 | [diff] [blame] | 42 | |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 43 | /* Base address of PBC controller */ |
| 44 | #define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT |
| 45 | |
Uwe Kleine-König | ccfa7c2 | 2010-03-08 17:10:54 +0100 | [diff] [blame] | 46 | /* PBC Board interrupt status register */ |
| 47 | #define PBC_INTSTATUS 0x000016 |
| 48 | |
| 49 | /* PBC Board interrupt current status register */ |
| 50 | #define PBC_INTCURR_STATUS 0x000018 |
| 51 | |
| 52 | /* PBC Interrupt mask register set address */ |
| 53 | #define PBC_INTMASK_SET 0x00001A |
| 54 | |
| 55 | /* PBC Interrupt mask register clear address */ |
| 56 | #define PBC_INTMASK_CLEAR 0x00001C |
| 57 | |
| 58 | /* External UART A */ |
| 59 | #define PBC_SC16C652_UARTA 0x010000 |
| 60 | |
| 61 | /* External UART B */ |
| 62 | #define PBC_SC16C652_UARTB 0x010010 |
| 63 | |
| 64 | #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) |
| 65 | #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) |
| 66 | #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) |
Uwe Kleine-König | ccfa7c2 | 2010-03-08 17:10:54 +0100 | [diff] [blame] | 67 | |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 68 | #define EXPIO_INT_XUART_INTA 10 |
| 69 | #define EXPIO_INT_XUART_INTB 11 |
Uwe Kleine-König | ccfa7c2 | 2010-03-08 17:10:54 +0100 | [diff] [blame] | 70 | |
| 71 | #define MXC_MAX_EXP_IO_LINES 16 |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 72 | |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 73 | /* CS8900 */ |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 74 | #define EXPIO_INT_ENET_INT 8 |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 75 | #define CS4_CS8900_MMIO_START 0x20000 |
| 76 | |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 77 | static struct irq_domain *domain; |
| 78 | |
Sascha Hauer | 9f43e44 | 2011-01-14 11:22:31 +0100 | [diff] [blame] | 79 | /* |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 80 | * The serial port definition structure. |
| 81 | */ |
| 82 | static struct plat_serial8250_port serial_platform_data[] = { |
| 83 | { |
| 84 | .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), |
Uwe Kleine-König | f568dd7 | 2009-12-09 11:57:21 +0100 | [diff] [blame] | 85 | .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA), |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 86 | .uartclk = 14745600, |
| 87 | .regshift = 0, |
| 88 | .iotype = UPIO_MEM, |
| 89 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, |
| 90 | }, { |
| 91 | .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), |
Uwe Kleine-König | f568dd7 | 2009-12-09 11:57:21 +0100 | [diff] [blame] | 92 | .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB), |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 93 | .uartclk = 14745600, |
| 94 | .regshift = 0, |
| 95 | .iotype = UPIO_MEM, |
| 96 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, |
| 97 | }, |
| 98 | {}, |
| 99 | }; |
| 100 | |
| 101 | static struct platform_device serial_device = { |
| 102 | .name = "serial8250", |
| 103 | .id = 0, |
| 104 | .dev = { |
| 105 | .platform_data = serial_platform_data, |
| 106 | }, |
| 107 | }; |
| 108 | |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 109 | static struct resource mx31ads_cs8900_resources[] __initdata = { |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 110 | DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K), |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 111 | DEFINE_RES_IRQ(-1), |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 112 | }; |
| 113 | |
| 114 | static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = { |
| 115 | .name = "cs89x0", |
| 116 | .id = 0, |
| 117 | .res = mx31ads_cs8900_resources, |
| 118 | .num_res = ARRAY_SIZE(mx31ads_cs8900_resources), |
| 119 | }; |
| 120 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 121 | static int __init mxc_init_extuart(void) |
| 122 | { |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 123 | serial_platform_data[0].irq = irq_find_mapping(domain, |
| 124 | EXPIO_INT_XUART_INTA); |
| 125 | serial_platform_data[1].irq = irq_find_mapping(domain, |
| 126 | EXPIO_INT_XUART_INTB); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 127 | return platform_device_register(&serial_device); |
| 128 | } |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 129 | |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 130 | static void __init mxc_init_ext_ethernet(void) |
| 131 | { |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 132 | mx31ads_cs8900_resources[1].start = |
| 133 | irq_find_mapping(domain, EXPIO_INT_ENET_INT); |
| 134 | mx31ads_cs8900_resources[1].end = |
| 135 | irq_find_mapping(domain, EXPIO_INT_ENET_INT); |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 136 | platform_device_register_full( |
| 137 | (struct platform_device_info *)&mx31ads_cs8900_devinfo); |
| 138 | } |
| 139 | |
Uwe Kleine-König | 16cf5c4 | 2010-06-23 11:46:16 +0200 | [diff] [blame] | 140 | static const struct imxuart_platform_data uart_pdata __initconst = { |
Gilles Chanteperdrix | 0741794 | 2008-09-09 10:19:41 +0200 | [diff] [blame] | 141 | .flags = IMXUART_HAVE_RTSCTS, |
| 142 | }; |
| 143 | |
Mark Brown | 9070e7a | 2009-04-13 13:02:36 +0100 | [diff] [blame] | 144 | static unsigned int uart_pins[] = { |
Valentin Longchamp | 945c10b | 2009-01-28 15:13:52 +0100 | [diff] [blame] | 145 | MX31_PIN_CTS1__CTS1, |
| 146 | MX31_PIN_RTS1__RTS1, |
| 147 | MX31_PIN_TXD1__TXD1, |
| 148 | MX31_PIN_RXD1__RXD1 |
| 149 | }; |
| 150 | |
Gilles Chanteperdrix | 0741794 | 2008-09-09 10:19:41 +0200 | [diff] [blame] | 151 | static inline void mxc_init_imx_uart(void) |
| 152 | { |
Valentin Longchamp | 945c10b | 2009-01-28 15:13:52 +0100 | [diff] [blame] | 153 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); |
Uwe Kleine-König | 16cf5c4 | 2010-06-23 11:46:16 +0200 | [diff] [blame] | 154 | imx31_add_imx_uart0(&uart_pdata); |
Gilles Chanteperdrix | 0741794 | 2008-09-09 10:19:41 +0200 | [diff] [blame] | 155 | } |
Gilles Chanteperdrix | 0741794 | 2008-09-09 10:19:41 +0200 | [diff] [blame] | 156 | |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 157 | static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc) |
| 158 | { |
| 159 | u32 imr_val; |
| 160 | u32 int_valid; |
| 161 | u32 expio_irq; |
| 162 | |
| 163 | imr_val = __raw_readw(PBC_INTMASK_SET_REG); |
| 164 | int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val; |
| 165 | |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 166 | expio_irq = 0; |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 167 | for (; int_valid != 0; int_valid >>= 1, expio_irq++) { |
| 168 | if ((int_valid & 1) == 0) |
| 169 | continue; |
| 170 | |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 171 | generic_handle_irq(irq_find_mapping(domain, expio_irq)); |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 172 | } |
| 173 | } |
| 174 | |
| 175 | /* |
| 176 | * Disable an expio pin's interrupt by setting the bit in the imr. |
Uwe Kleine-König | 4e43d9f | 2011-02-11 10:21:09 +0100 | [diff] [blame] | 177 | * @param d an expio virtual irq description |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 178 | */ |
Lennert Buytenhek | e981a30 | 2010-11-29 10:37:55 +0100 | [diff] [blame] | 179 | static void expio_mask_irq(struct irq_data *d) |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 180 | { |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 181 | u32 expio = d->hwirq; |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 182 | /* mask the interrupt */ |
| 183 | __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG); |
| 184 | __raw_readw(PBC_INTMASK_CLEAR_REG); |
| 185 | } |
| 186 | |
| 187 | /* |
| 188 | * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. |
Uwe Kleine-König | 4e43d9f | 2011-02-11 10:21:09 +0100 | [diff] [blame] | 189 | * @param d an expio virtual irq description |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 190 | */ |
Lennert Buytenhek | e981a30 | 2010-11-29 10:37:55 +0100 | [diff] [blame] | 191 | static void expio_ack_irq(struct irq_data *d) |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 192 | { |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 193 | u32 expio = d->hwirq; |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 194 | /* clear the interrupt status */ |
| 195 | __raw_writew(1 << expio, PBC_INTSTATUS_REG); |
| 196 | } |
| 197 | |
| 198 | /* |
| 199 | * Enable a expio pin's interrupt by clearing the bit in the imr. |
Uwe Kleine-König | 4e43d9f | 2011-02-11 10:21:09 +0100 | [diff] [blame] | 200 | * @param d an expio virtual irq description |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 201 | */ |
Lennert Buytenhek | e981a30 | 2010-11-29 10:37:55 +0100 | [diff] [blame] | 202 | static void expio_unmask_irq(struct irq_data *d) |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 203 | { |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 204 | u32 expio = d->hwirq; |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 205 | /* unmask the interrupt */ |
| 206 | __raw_writew(1 << expio, PBC_INTMASK_SET_REG); |
| 207 | } |
| 208 | |
| 209 | static struct irq_chip expio_irq_chip = { |
Mark Brown | bd02acd | 2010-01-05 16:05:15 +0000 | [diff] [blame] | 210 | .name = "EXPIO(CPLD)", |
Lennert Buytenhek | e981a30 | 2010-11-29 10:37:55 +0100 | [diff] [blame] | 211 | .irq_ack = expio_ack_irq, |
| 212 | .irq_mask = expio_mask_irq, |
| 213 | .irq_unmask = expio_unmask_irq, |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 214 | }; |
| 215 | |
| 216 | static void __init mx31ads_init_expio(void) |
| 217 | { |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 218 | int irq_base; |
Shawn Guo | ed17534 | 2011-12-02 20:00:33 +0800 | [diff] [blame] | 219 | int i, irq; |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 220 | |
| 221 | printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n"); |
| 222 | |
| 223 | /* |
| 224 | * Configure INT line as GPIO input |
| 225 | */ |
Sascha Hauer | 4f163eb | 2009-05-06 12:55:50 +0200 | [diff] [blame] | 226 | mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 227 | |
| 228 | /* disable the interrupt and clear the status */ |
| 229 | __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); |
| 230 | __raw_writew(0xFFFF, PBC_INTSTATUS_REG); |
Shawn Guo | 130d8bd | 2012-06-13 17:07:25 +0800 | [diff] [blame] | 231 | |
| 232 | irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id()); |
| 233 | WARN_ON(irq_base < 0); |
| 234 | |
| 235 | domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0, |
| 236 | &irq_domain_simple_ops, NULL); |
| 237 | WARN_ON(!domain); |
| 238 | |
| 239 | for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { |
Thomas Gleixner | f38c02f | 2011-03-24 13:35:09 +0100 | [diff] [blame] | 240 | irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 241 | set_irq_flags(i, IRQF_VALID); |
| 242 | } |
Shawn Guo | ed17534 | 2011-12-02 20:00:33 +0800 | [diff] [blame] | 243 | irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4)); |
| 244 | irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); |
| 245 | irq_set_chained_handler(irq, mx31ads_expio_irq_handler); |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 246 | } |
| 247 | |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 248 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 |
| 249 | /* This section defines setup for the Wolfson Microelectronics |
| 250 | * 1133-EV1 PMU/audio board. When other PMU boards are supported the |
| 251 | * regulator definitions may be shared with them, but for now they can |
| 252 | * only be used with this board so would generate warnings about |
| 253 | * unused statics and some of the configuration is specific to this |
| 254 | * module. |
| 255 | */ |
| 256 | |
| 257 | /* CPU */ |
| 258 | static struct regulator_consumer_supply sw1a_consumers[] = { |
| 259 | { |
| 260 | .supply = "cpu_vcc", |
| 261 | } |
| 262 | }; |
| 263 | |
| 264 | static struct regulator_init_data sw1a_data = { |
| 265 | .constraints = { |
| 266 | .name = "SW1A", |
| 267 | .min_uV = 1275000, |
| 268 | .max_uV = 1600000, |
| 269 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
| 270 | REGULATOR_CHANGE_MODE, |
| 271 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
| 272 | REGULATOR_MODE_FAST, |
| 273 | .state_mem = { |
| 274 | .uV = 1400000, |
| 275 | .mode = REGULATOR_MODE_NORMAL, |
| 276 | .enabled = 1, |
| 277 | }, |
| 278 | .initial_state = PM_SUSPEND_MEM, |
| 279 | .always_on = 1, |
| 280 | .boot_on = 1, |
| 281 | }, |
| 282 | .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers), |
| 283 | .consumer_supplies = sw1a_consumers, |
| 284 | }; |
| 285 | |
| 286 | /* System IO - High */ |
| 287 | static struct regulator_init_data viohi_data = { |
| 288 | .constraints = { |
| 289 | .name = "VIOHO", |
| 290 | .min_uV = 2800000, |
| 291 | .max_uV = 2800000, |
| 292 | .state_mem = { |
| 293 | .uV = 2800000, |
| 294 | .mode = REGULATOR_MODE_NORMAL, |
| 295 | .enabled = 1, |
| 296 | }, |
| 297 | .initial_state = PM_SUSPEND_MEM, |
| 298 | .always_on = 1, |
| 299 | .boot_on = 1, |
| 300 | }, |
| 301 | }; |
| 302 | |
| 303 | /* System IO - Low */ |
| 304 | static struct regulator_init_data violo_data = { |
| 305 | .constraints = { |
| 306 | .name = "VIOLO", |
| 307 | .min_uV = 1800000, |
| 308 | .max_uV = 1800000, |
| 309 | .state_mem = { |
| 310 | .uV = 1800000, |
| 311 | .mode = REGULATOR_MODE_NORMAL, |
| 312 | .enabled = 1, |
| 313 | }, |
| 314 | .initial_state = PM_SUSPEND_MEM, |
| 315 | .always_on = 1, |
| 316 | .boot_on = 1, |
| 317 | }, |
| 318 | }; |
| 319 | |
| 320 | /* DDR RAM */ |
| 321 | static struct regulator_init_data sw2a_data = { |
| 322 | .constraints = { |
| 323 | .name = "SW2A", |
| 324 | .min_uV = 1800000, |
| 325 | .max_uV = 1800000, |
| 326 | .valid_modes_mask = REGULATOR_MODE_NORMAL, |
| 327 | .state_mem = { |
| 328 | .uV = 1800000, |
| 329 | .mode = REGULATOR_MODE_NORMAL, |
| 330 | .enabled = 1, |
| 331 | }, |
| 332 | .state_disk = { |
| 333 | .mode = REGULATOR_MODE_NORMAL, |
| 334 | .enabled = 0, |
| 335 | }, |
| 336 | .always_on = 1, |
| 337 | .boot_on = 1, |
| 338 | .initial_state = PM_SUSPEND_MEM, |
| 339 | }, |
| 340 | }; |
| 341 | |
| 342 | static struct regulator_init_data ldo1_data = { |
| 343 | .constraints = { |
| 344 | .name = "VCAM/VMMC1/VMMC2", |
| 345 | .min_uV = 2800000, |
| 346 | .max_uV = 2800000, |
| 347 | .valid_modes_mask = REGULATOR_MODE_NORMAL, |
Mark Brown | becc670 | 2010-01-04 18:24:50 +0000 | [diff] [blame] | 348 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 349 | .apply_uV = 1, |
| 350 | }, |
| 351 | }; |
| 352 | |
| 353 | static struct regulator_consumer_supply ldo2_consumers[] = { |
Mark Brown | edc34a9 | 2010-01-04 18:24:49 +0000 | [diff] [blame] | 354 | { .supply = "AVDD", .dev_name = "1-001a" }, |
| 355 | { .supply = "HPVDD", .dev_name = "1-001a" }, |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 356 | }; |
| 357 | |
| 358 | /* CODEC and SIM */ |
| 359 | static struct regulator_init_data ldo2_data = { |
| 360 | .constraints = { |
| 361 | .name = "VESIM/VSIM/AVDD", |
| 362 | .min_uV = 3300000, |
| 363 | .max_uV = 3300000, |
| 364 | .valid_modes_mask = REGULATOR_MODE_NORMAL, |
Mark Brown | becc670 | 2010-01-04 18:24:50 +0000 | [diff] [blame] | 365 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 366 | .apply_uV = 1, |
| 367 | }, |
| 368 | .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), |
| 369 | .consumer_supplies = ldo2_consumers, |
| 370 | }; |
| 371 | |
| 372 | /* General */ |
| 373 | static struct regulator_init_data vdig_data = { |
| 374 | .constraints = { |
| 375 | .name = "VDIG", |
| 376 | .min_uV = 1500000, |
| 377 | .max_uV = 1500000, |
| 378 | .valid_modes_mask = REGULATOR_MODE_NORMAL, |
| 379 | .apply_uV = 1, |
| 380 | .always_on = 1, |
| 381 | .boot_on = 1, |
| 382 | }, |
| 383 | }; |
| 384 | |
| 385 | /* Tranceivers */ |
| 386 | static struct regulator_init_data ldo4_data = { |
| 387 | .constraints = { |
| 388 | .name = "VRF1/CVDD_2.775", |
| 389 | .min_uV = 2500000, |
| 390 | .max_uV = 2500000, |
| 391 | .valid_modes_mask = REGULATOR_MODE_NORMAL, |
| 392 | .apply_uV = 1, |
| 393 | .always_on = 1, |
| 394 | .boot_on = 1, |
| 395 | }, |
| 396 | }; |
| 397 | |
| 398 | static struct wm8350_led_platform_data wm8350_led_data = { |
| 399 | .name = "wm8350:white", |
| 400 | .default_trigger = "heartbeat", |
| 401 | .max_uA = 27899, |
| 402 | }; |
| 403 | |
| 404 | static struct wm8350_audio_platform_data imx32ads_wm8350_setup = { |
| 405 | .vmid_discharge_msecs = 1000, |
| 406 | .drain_msecs = 30, |
| 407 | .cap_discharge_msecs = 700, |
| 408 | .vmid_charge_msecs = 700, |
| 409 | .vmid_s_curve = WM8350_S_CURVE_SLOW, |
| 410 | .dis_out4 = WM8350_DISCHARGE_SLOW, |
| 411 | .dis_out3 = WM8350_DISCHARGE_SLOW, |
| 412 | .dis_out2 = WM8350_DISCHARGE_SLOW, |
| 413 | .dis_out1 = WM8350_DISCHARGE_SLOW, |
| 414 | .vroi_out4 = WM8350_TIE_OFF_500R, |
| 415 | .vroi_out3 = WM8350_TIE_OFF_500R, |
| 416 | .vroi_out2 = WM8350_TIE_OFF_500R, |
| 417 | .vroi_out1 = WM8350_TIE_OFF_500R, |
| 418 | .vroi_enable = 0, |
| 419 | .codec_current_on = WM8350_CODEC_ISEL_1_0, |
| 420 | .codec_current_standby = WM8350_CODEC_ISEL_0_5, |
| 421 | .codec_current_charge = WM8350_CODEC_ISEL_1_5, |
| 422 | }; |
| 423 | |
| 424 | static int mx31_wm8350_init(struct wm8350 *wm8350) |
| 425 | { |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 426 | wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, |
| 427 | WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, |
| 428 | WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, |
| 429 | WM8350_GPIO_DEBOUNCE_ON); |
| 430 | |
| 431 | wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN, |
| 432 | WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH, |
| 433 | WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, |
| 434 | WM8350_GPIO_DEBOUNCE_ON); |
| 435 | |
| 436 | wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN, |
| 437 | WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH, |
| 438 | WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, |
| 439 | WM8350_GPIO_DEBOUNCE_OFF); |
| 440 | |
| 441 | wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN, |
| 442 | WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH, |
| 443 | WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, |
| 444 | WM8350_GPIO_DEBOUNCE_OFF); |
| 445 | |
| 446 | wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT, |
| 447 | WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH, |
| 448 | WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, |
| 449 | WM8350_GPIO_DEBOUNCE_OFF); |
| 450 | |
| 451 | wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT, |
| 452 | WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, |
| 453 | WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, |
| 454 | WM8350_GPIO_DEBOUNCE_OFF); |
| 455 | |
| 456 | wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT, |
| 457 | WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, |
| 458 | WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, |
| 459 | WM8350_GPIO_DEBOUNCE_OFF); |
| 460 | |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 461 | wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); |
| 462 | wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); |
| 463 | wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); |
| 464 | wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data); |
| 465 | wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data); |
| 466 | wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data); |
| 467 | wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data); |
| 468 | wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data); |
| 469 | |
| 470 | /* LEDs */ |
| 471 | wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1, |
| 472 | WM8350_DC5_ERRACT_SHUTDOWN_CONV); |
| 473 | wm8350_isink_set_flash(wm8350, WM8350_ISINK_A, |
| 474 | WM8350_ISINK_FLASH_DISABLE, |
| 475 | WM8350_ISINK_FLASH_TRIG_BIT, |
| 476 | WM8350_ISINK_FLASH_DUR_32MS, |
| 477 | WM8350_ISINK_FLASH_ON_INSTANT, |
| 478 | WM8350_ISINK_FLASH_OFF_INSTANT, |
| 479 | WM8350_ISINK_FLASH_MODE_EN); |
| 480 | wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5, |
| 481 | WM8350_ISINK_MODE_BOOST, |
| 482 | WM8350_ISINK_ILIM_NORMAL, |
| 483 | WM8350_DC5_RMP_20V, |
| 484 | WM8350_DC5_FBSRC_ISINKA); |
| 485 | wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A, |
| 486 | &wm8350_led_data); |
| 487 | |
| 488 | wm8350->codec.platform_data = &imx32ads_wm8350_setup; |
| 489 | |
Mark Brown | 0ac402f | 2009-04-13 13:05:28 +0100 | [diff] [blame] | 490 | regulator_has_full_constraints(); |
| 491 | |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 492 | return 0; |
| 493 | } |
| 494 | |
| 495 | static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { |
| 496 | .init = mx31_wm8350_init, |
| 497 | }; |
| 498 | #endif |
| 499 | |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 500 | static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { |
| 501 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 |
| 502 | { |
| 503 | I2C_BOARD_INFO("wm8350", 0x1a), |
| 504 | .platform_data = &mx31_wm8350_pdata, |
Shawn Guo | ed17534 | 2011-12-02 20:00:33 +0800 | [diff] [blame] | 505 | /* irq number is run-time assigned */ |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 506 | }, |
| 507 | #endif |
| 508 | }; |
| 509 | |
Fabio Estevam | ea7aed6 | 2011-06-14 15:42:49 -0300 | [diff] [blame] | 510 | static void __init mxc_init_i2c(void) |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 511 | { |
Shawn Guo | ed17534 | 2011-12-02 20:00:33 +0800 | [diff] [blame] | 512 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 |
| 513 | mx31ads_i2c1_devices[0].irq = |
| 514 | gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); |
| 515 | #endif |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 516 | i2c_register_board_info(1, mx31ads_i2c1_devices, |
| 517 | ARRAY_SIZE(mx31ads_i2c1_devices)); |
| 518 | |
| 519 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); |
| 520 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); |
| 521 | |
Uwe Kleine-König | 4a9b8b0 | 2010-06-16 18:03:05 +0200 | [diff] [blame] | 522 | imx31_add_imx_i2c1(NULL); |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 523 | } |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 524 | |
Mark Brown | cd6eb98 | 2010-02-23 11:05:11 +0000 | [diff] [blame] | 525 | static unsigned int ssi_pins[] = { |
| 526 | MX31_PIN_SFS5__SFS5, |
| 527 | MX31_PIN_SCK5__SCK5, |
| 528 | MX31_PIN_SRXD5__SRXD5, |
| 529 | MX31_PIN_STXD5__STXD5, |
| 530 | }; |
| 531 | |
Fabio Estevam | ea7aed6 | 2011-06-14 15:42:49 -0300 | [diff] [blame] | 532 | static void __init mxc_init_audio(void) |
Mark Brown | cd6eb98 | 2010-02-23 11:05:11 +0000 | [diff] [blame] | 533 | { |
Uwe Kleine-König | 4697bb9 | 2010-08-25 17:37:45 +0200 | [diff] [blame] | 534 | imx31_add_imx_ssi(0, NULL); |
Mark Brown | cd6eb98 | 2010-02-23 11:05:11 +0000 | [diff] [blame] | 535 | mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); |
| 536 | } |
| 537 | |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 538 | /* |
| 539 | * Static mappings, starting from the CS4 start address up to the start address |
| 540 | * of the CS8900. |
| 541 | */ |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 542 | static struct map_desc mx31ads_io_desc[] __initdata = { |
| 543 | { |
Arnd Bergmann | f25d696 | 2012-09-14 20:14:01 +0000 | [diff] [blame] | 544 | .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, |
Uwe Kleine-König | f568dd7 | 2009-12-09 11:57:21 +0100 | [diff] [blame] | 545 | .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 546 | .length = CS4_CS8900_MMIO_START, |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 547 | .type = MT_DEVICE |
| 548 | }, |
| 549 | }; |
| 550 | |
Mark Brown | 8b785b9 | 2009-01-15 16:14:29 +0000 | [diff] [blame] | 551 | static void __init mx31ads_map_io(void) |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 552 | { |
Sascha Hauer | cd4a05f | 2009-04-02 22:32:10 +0200 | [diff] [blame] | 553 | mx31_map_io(); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 554 | iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); |
| 555 | } |
| 556 | |
Mark Brown | 8b785b9 | 2009-01-15 16:14:29 +0000 | [diff] [blame] | 557 | static void __init mx31ads_init_irq(void) |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 558 | { |
Sascha Hauer | c5aa0ad | 2009-05-25 17:36:19 +0200 | [diff] [blame] | 559 | mx31_init_irq(); |
Gilles Chanteperdrix | d7568f7 | 2008-09-09 10:19:42 +0200 | [diff] [blame] | 560 | mx31ads_init_expio(); |
| 561 | } |
| 562 | |
Uwe Kleine-König | e134fb2 | 2011-02-11 10:23:19 +0100 | [diff] [blame] | 563 | static void __init mx31ads_init(void) |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 564 | { |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 565 | imx31_soc_init(); |
| 566 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 567 | mxc_init_extuart(); |
Gilles Chanteperdrix | 0741794 | 2008-09-09 10:19:41 +0200 | [diff] [blame] | 568 | mxc_init_imx_uart(); |
Mark Brown | fe7316b | 2009-01-15 16:14:30 +0000 | [diff] [blame] | 569 | mxc_init_i2c(); |
Mark Brown | cd6eb98 | 2010-02-23 11:05:11 +0000 | [diff] [blame] | 570 | mxc_init_audio(); |
Jaccon Bastiaansen | 64a3851 | 2012-01-26 21:47:27 +0100 | [diff] [blame] | 571 | mxc_init_ext_ethernet(); |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 572 | } |
| 573 | |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 574 | static void __init mx31ads_timer_init(void) |
| 575 | { |
Sascha Hauer | 30c730f | 2009-02-16 14:36:49 +0100 | [diff] [blame] | 576 | mx31_clocks_init(26000000); |
Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame] | 577 | } |
| 578 | |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 579 | MACHINE_START(MX31ADS, "Freescale MX31ADS") |
| 580 | /* Maintainer: Freescale Semiconductor, Inc. */ |
Nicolas Pitre | dc8f190 | 2011-07-05 22:38:12 -0400 | [diff] [blame] | 581 | .atag_offset = 0x100, |
Uwe Kleine-König | 97976e2 | 2011-02-07 16:35:20 +0100 | [diff] [blame] | 582 | .map_io = mx31ads_map_io, |
| 583 | .init_early = imx31_init_early, |
| 584 | .init_irq = mx31ads_init_irq, |
Sascha Hauer | ffa2ea3 | 2011-09-20 14:31:24 +0200 | [diff] [blame] | 585 | .handle_irq = imx31_handle_irq, |
Stephen Warren | 6bb27d7 | 2012-11-08 12:40:59 -0700 | [diff] [blame] | 586 | .init_time = mx31ads_timer_init, |
Uwe Kleine-König | e134fb2 | 2011-02-11 10:23:19 +0100 | [diff] [blame] | 587 | .init_machine = mx31ads_init, |
Russell King | 65ea788 | 2011-11-06 17:12:08 +0000 | [diff] [blame] | 588 | .restart = mxc_restart, |
Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 589 | MACHINE_END |