blob: d2ea8b460364cf3681f778a0a9cdd4dca521f7d6 [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001#include "drmP.h"
2#include "drm_mode.h"
Ben Skeggs77145f12012-07-31 16:16:21 +10003#include "nouveau_drm.h"
Ben Skeggs6ee73862009-12-11 19:24:15 +10004#include "nouveau_reg.h"
Ben Skeggs6ee73862009-12-11 19:24:15 +10005#include "nouveau_crtc.h"
6#include "nouveau_hw.h"
7
8static void
9nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
10{
11 nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true);
12}
13
14static void
15nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
16{
17 nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false);
18}
19
20static void
21nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
22{
Maarten Maathuisb334f2b2010-05-09 14:49:52 +020023 nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y;
Ben Skeggs6ee73862009-12-11 19:24:15 +100024 NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index,
25 NV_PRAMDAC_CU_START_POS,
26 XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) |
27 XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X));
28}
29
30static void
31crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
32{
33 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
34 crtcstate->CRTC[index]);
35}
36
37static void
38nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
39{
40 struct drm_device *dev = nv_crtc->base.dev;
Ben Skeggs77145f12012-07-31 16:16:21 +100041 struct nouveau_drm *drm = nouveau_drm(dev);
Ben Skeggs017e6e22012-07-18 10:00:50 +100042 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
Ben Skeggs6ee73862009-12-11 19:24:15 +100043 struct drm_crtc *crtc = &nv_crtc->base;
44
45 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
46 MASK(NV_CIO_CRE_HCUR_ASI) |
47 XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR);
48 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
49 XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR);
50 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
51 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
52 MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24;
54
55 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
56 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
57 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
Ben Skeggs77145f12012-07-31 16:16:21 +100058 if (nv_device(drm->device)->card_type == NV_40)
Ben Skeggs6ee73862009-12-11 19:24:15 +100059 nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
60}
61
62int
63nv04_cursor_init(struct nouveau_crtc *crtc)
64{
65 crtc->cursor.set_offset = nv04_cursor_set_offset;
66 crtc->cursor.set_pos = nv04_cursor_set_pos;
67 crtc->cursor.hide = nv04_cursor_hide;
68 crtc->cursor.show = nv04_cursor_show;
69 return 0;
70}
71