blob: 4c64627c6bb5db745a3efff6d64eef9d8416e331 [file] [log] [blame]
Gregory Fong3b0213d2015-05-28 19:14:05 -07001/*
2 * Copyright (C) 2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/bitops.h>
15#include <linux/gpio/driver.h>
16#include <linux/of_device.h>
17#include <linux/of_irq.h>
18#include <linux/module.h>
19#include <linux/basic_mmio_gpio.h>
Gregory Fong19a7b692015-07-31 18:17:43 -070020#include <linux/irqdomain.h>
21#include <linux/irqchip/chained_irq.h>
22#include <linux/interrupt.h>
Gregory Fong3afa1292015-07-31 18:17:44 -070023#include <linux/reboot.h>
Gregory Fong3b0213d2015-05-28 19:14:05 -070024
25#define GIO_BANK_SIZE 0x20
26#define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00)
27#define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04)
28#define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08)
29#define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c)
30#define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10)
31#define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14)
32#define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18)
33#define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c)
34
35struct brcmstb_gpio_bank {
36 struct list_head node;
37 int id;
38 struct bgpio_chip bgc;
39 struct brcmstb_gpio_priv *parent_priv;
40 u32 width;
Gregory Fong19a7b692015-07-31 18:17:43 -070041 struct irq_chip irq_chip;
Gregory Fong3b0213d2015-05-28 19:14:05 -070042};
43
44struct brcmstb_gpio_priv {
45 struct list_head bank_list;
46 void __iomem *reg_base;
Gregory Fong3b0213d2015-05-28 19:14:05 -070047 struct platform_device *pdev;
Gregory Fong19a7b692015-07-31 18:17:43 -070048 int parent_irq;
Gregory Fong3b0213d2015-05-28 19:14:05 -070049 int gpio_base;
Gregory Fong19a7b692015-07-31 18:17:43 -070050 bool can_wake;
51 int parent_wake_irq;
Gregory Fong3afa1292015-07-31 18:17:44 -070052 struct notifier_block reboot_notifier;
Gregory Fong3b0213d2015-05-28 19:14:05 -070053};
54
55#define MAX_GPIO_PER_BANK 32
56#define GPIO_BANK(gpio) ((gpio) >> 5)
57/* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
58#define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
59
60static inline struct brcmstb_gpio_bank *
61brcmstb_gpio_gc_to_bank(struct gpio_chip *gc)
62{
63 struct bgpio_chip *bgc = to_bgpio_chip(gc);
64 return container_of(bgc, struct brcmstb_gpio_bank, bgc);
65}
66
67static inline struct brcmstb_gpio_priv *
68brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
69{
70 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
71 return bank->parent_priv;
72}
73
Gregory Fong19a7b692015-07-31 18:17:43 -070074static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
75 unsigned int offset, bool enable)
76{
77 struct bgpio_chip *bgc = &bank->bgc;
78 struct brcmstb_gpio_priv *priv = bank->parent_priv;
79 u32 mask = bgc->pin2mask(bgc, offset);
80 u32 imask;
81 unsigned long flags;
82
83 spin_lock_irqsave(&bgc->lock, flags);
84 imask = bgc->read_reg(priv->reg_base + GIO_MASK(bank->id));
85 if (enable)
86 imask |= mask;
87 else
88 imask &= ~mask;
89 bgc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
90 spin_unlock_irqrestore(&bgc->lock, flags);
91}
92
93/* -------------------- IRQ chip functions -------------------- */
94
95static void brcmstb_gpio_irq_mask(struct irq_data *d)
96{
97 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
98 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
99
100 brcmstb_gpio_set_imask(bank, d->hwirq, false);
101}
102
103static void brcmstb_gpio_irq_unmask(struct irq_data *d)
104{
105 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
106 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
107
108 brcmstb_gpio_set_imask(bank, d->hwirq, true);
109}
110
111static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
112{
113 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
114 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
115 struct brcmstb_gpio_priv *priv = bank->parent_priv;
116 u32 mask = BIT(d->hwirq);
117 u32 edge_insensitive, iedge_insensitive;
118 u32 edge_config, iedge_config;
119 u32 level, ilevel;
120 unsigned long flags;
121
122 switch (type) {
123 case IRQ_TYPE_LEVEL_LOW:
124 level = 0;
125 edge_config = 0;
126 edge_insensitive = 0;
127 break;
128 case IRQ_TYPE_LEVEL_HIGH:
129 level = mask;
130 edge_config = 0;
131 edge_insensitive = 0;
132 break;
133 case IRQ_TYPE_EDGE_FALLING:
134 level = 0;
135 edge_config = 0;
136 edge_insensitive = 0;
137 break;
138 case IRQ_TYPE_EDGE_RISING:
139 level = 0;
140 edge_config = mask;
141 edge_insensitive = 0;
142 break;
143 case IRQ_TYPE_EDGE_BOTH:
144 level = 0;
145 edge_config = 0; /* don't care, but want known value */
146 edge_insensitive = mask;
147 break;
148 default:
149 return -EINVAL;
150 }
151
152 spin_lock_irqsave(&bank->bgc.lock, flags);
153
154 iedge_config = bank->bgc.read_reg(priv->reg_base +
155 GIO_EC(bank->id)) & ~mask;
156 iedge_insensitive = bank->bgc.read_reg(priv->reg_base +
157 GIO_EI(bank->id)) & ~mask;
158 ilevel = bank->bgc.read_reg(priv->reg_base +
159 GIO_LEVEL(bank->id)) & ~mask;
160
161 bank->bgc.write_reg(priv->reg_base + GIO_EC(bank->id),
162 iedge_config | edge_config);
163 bank->bgc.write_reg(priv->reg_base + GIO_EI(bank->id),
164 iedge_insensitive | edge_insensitive);
165 bank->bgc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
166 ilevel | level);
167
168 spin_unlock_irqrestore(&bank->bgc.lock, flags);
169 return 0;
170}
171
Gregory Fong3afa1292015-07-31 18:17:44 -0700172static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
173 unsigned int enable)
Gregory Fong19a7b692015-07-31 18:17:43 -0700174{
Gregory Fong19a7b692015-07-31 18:17:43 -0700175 int ret = 0;
176
177 /*
178 * Only enable wake IRQ once for however many hwirqs can wake
179 * since they all use the same wake IRQ. Mask will be set
180 * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
181 */
182 if (enable)
183 ret = enable_irq_wake(priv->parent_wake_irq);
184 else
185 ret = disable_irq_wake(priv->parent_wake_irq);
186 if (ret)
187 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
188 enable ? "enable" : "disable");
189 return ret;
190}
191
Gregory Fong3afa1292015-07-31 18:17:44 -0700192static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
193{
194 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
195 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
196
197 return brcmstb_gpio_priv_set_wake(priv, enable);
198}
199
Gregory Fong19a7b692015-07-31 18:17:43 -0700200static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
201{
202 struct brcmstb_gpio_priv *priv = data;
203
204 if (!priv || irq != priv->parent_wake_irq)
205 return IRQ_NONE;
206 pm_wakeup_event(&priv->pdev->dev, 0);
207 return IRQ_HANDLED;
208}
209
210static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
211{
212 struct brcmstb_gpio_priv *priv = bank->parent_priv;
213 struct irq_domain *irq_domain = bank->bgc.gc.irqdomain;
214 void __iomem *reg_base = priv->reg_base;
215 unsigned long status;
216 unsigned long flags;
217
218 spin_lock_irqsave(&bank->bgc.lock, flags);
219 while ((status = bank->bgc.read_reg(reg_base + GIO_STAT(bank->id)) &
220 bank->bgc.read_reg(reg_base + GIO_MASK(bank->id)))) {
221 int bit;
222
223 for_each_set_bit(bit, &status, 32) {
224 u32 stat = bank->bgc.read_reg(reg_base +
225 GIO_STAT(bank->id));
226 if (bit >= bank->width)
227 dev_warn(&priv->pdev->dev,
228 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
229 bank->id, bit);
230 bank->bgc.write_reg(reg_base + GIO_STAT(bank->id),
231 stat | BIT(bit));
232 generic_handle_irq(irq_find_mapping(irq_domain, bit));
233 }
234 }
235 spin_unlock_irqrestore(&bank->bgc.lock, flags);
236}
237
238/* Each UPG GIO block has one IRQ for all banks */
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200239static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
Gregory Fong19a7b692015-07-31 18:17:43 -0700240{
241 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
242 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
243 struct irq_chip *chip = irq_desc_get_chip(desc);
244 struct list_head *pos;
245
246 /* Interrupts weren't properly cleared during probe */
247 BUG_ON(!priv || !chip);
248
249 chained_irq_enter(chip, desc);
250 list_for_each(pos, &priv->bank_list) {
251 struct brcmstb_gpio_bank *bank =
252 list_entry(pos, struct brcmstb_gpio_bank, node);
253 brcmstb_gpio_irq_bank_handler(bank);
254 }
255 chained_irq_exit(chip, desc);
256}
257
Gregory Fong3afa1292015-07-31 18:17:44 -0700258static int brcmstb_gpio_reboot(struct notifier_block *nb,
259 unsigned long action, void *data)
260{
261 struct brcmstb_gpio_priv *priv =
262 container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
263
264 /* Enable GPIO for S5 cold boot */
265 if (action == SYS_POWER_OFF)
266 brcmstb_gpio_priv_set_wake(priv, 1);
267
268 return NOTIFY_DONE;
269}
270
Gregory Fong3b0213d2015-05-28 19:14:05 -0700271/* Make sure that the number of banks matches up between properties */
272static int brcmstb_gpio_sanity_check_banks(struct device *dev,
273 struct device_node *np, struct resource *res)
274{
275 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
276 int num_banks =
277 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
278
279 if (res_num_banks != num_banks) {
280 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
281 res_num_banks, num_banks);
282 return -EINVAL;
283 } else {
284 return 0;
285 }
286}
287
288static int brcmstb_gpio_remove(struct platform_device *pdev)
289{
290 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
291 struct list_head *pos;
292 struct brcmstb_gpio_bank *bank;
293 int ret = 0;
294
Gregory Fong22526072015-06-17 18:00:40 -0700295 if (!priv) {
296 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
297 return -EFAULT;
298 }
299
300 /*
301 * You can lose return values below, but we report all errors, and it's
302 * more important to actually perform all of the steps.
303 */
Gregory Fong3b0213d2015-05-28 19:14:05 -0700304 list_for_each(pos, &priv->bank_list) {
305 bank = list_entry(pos, struct brcmstb_gpio_bank, node);
306 ret = bgpio_remove(&bank->bgc);
307 if (ret)
Gregory Fong19a7b692015-07-31 18:17:43 -0700308 dev_err(&pdev->dev, "gpiochip_remove fail in cleanup\n");
Gregory Fong3b0213d2015-05-28 19:14:05 -0700309 }
Gregory Fong3afa1292015-07-31 18:17:44 -0700310 if (priv->reboot_notifier.notifier_call) {
311 ret = unregister_reboot_notifier(&priv->reboot_notifier);
312 if (ret)
313 dev_err(&pdev->dev,
314 "failed to unregister reboot notifier\n");
315 }
Gregory Fong3b0213d2015-05-28 19:14:05 -0700316 return ret;
317}
318
319static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
320 const struct of_phandle_args *gpiospec, u32 *flags)
321{
322 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
323 struct brcmstb_gpio_bank *bank = brcmstb_gpio_gc_to_bank(gc);
324 int offset;
325
326 if (gc->of_gpio_n_cells != 2) {
327 WARN_ON(1);
328 return -EINVAL;
329 }
330
331 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
332 return -EINVAL;
333
334 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
Gregory Fong19a7b692015-07-31 18:17:43 -0700335 if (offset >= gc->ngpio || offset < 0)
Gregory Fong3b0213d2015-05-28 19:14:05 -0700336 return -EINVAL;
337
338 if (unlikely(offset >= bank->width)) {
339 dev_warn_ratelimited(&priv->pdev->dev,
340 "Received request for invalid GPIO offset %d\n",
341 gpiospec->args[0]);
342 }
343
344 if (flags)
345 *flags = gpiospec->args[1];
346
347 return offset;
348}
349
Gregory Fong19a7b692015-07-31 18:17:43 -0700350/* Before calling, must have bank->parent_irq set and gpiochip registered */
351static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
352 struct brcmstb_gpio_bank *bank)
353{
354 struct brcmstb_gpio_priv *priv = bank->parent_priv;
355 struct device *dev = &pdev->dev;
356 struct device_node *np = dev->of_node;
357
358 bank->irq_chip.name = dev_name(dev);
359 bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
360 bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
361 bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
362
363 /* Ensures that all non-wakeup IRQs are disabled at suspend */
364 bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
365
366 if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
367 of_property_read_bool(np, "wakeup-source")) {
368 priv->parent_wake_irq = platform_get_irq(pdev, 1);
369 if (priv->parent_wake_irq < 0) {
370 dev_warn(dev,
371 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
372 } else {
Gregory Fong3afa1292015-07-31 18:17:44 -0700373 int err;
374
375 /*
376 * Set wakeup capability before requesting wakeup
377 * interrupt, so we can process boot-time "wakeups"
378 * (e.g., from S5 cold boot)
379 */
380 device_set_wakeup_capable(dev, true);
381 device_wakeup_enable(dev);
382 err = devm_request_irq(dev, priv->parent_wake_irq,
Gregory Fong19a7b692015-07-31 18:17:43 -0700383 brcmstb_gpio_wake_irq_handler, 0,
384 "brcmstb-gpio-wake", priv);
385
386 if (err < 0) {
387 dev_err(dev, "Couldn't request wake IRQ");
388 return err;
389 }
390
Gregory Fong3afa1292015-07-31 18:17:44 -0700391 priv->reboot_notifier.notifier_call =
392 brcmstb_gpio_reboot;
393 register_reboot_notifier(&priv->reboot_notifier);
Gregory Fong19a7b692015-07-31 18:17:43 -0700394 priv->can_wake = true;
395 }
396 }
397
398 if (priv->can_wake)
399 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
400
401 gpiochip_irqchip_add(&bank->bgc.gc, &bank->irq_chip, 0,
402 handle_simple_irq, IRQ_TYPE_NONE);
403 gpiochip_set_chained_irqchip(&bank->bgc.gc, &bank->irq_chip,
404 priv->parent_irq, brcmstb_gpio_irq_handler);
405
406 return 0;
407}
408
Gregory Fong3b0213d2015-05-28 19:14:05 -0700409static int brcmstb_gpio_probe(struct platform_device *pdev)
410{
411 struct device *dev = &pdev->dev;
412 struct device_node *np = dev->of_node;
413 void __iomem *reg_base;
414 struct brcmstb_gpio_priv *priv;
415 struct resource *res;
416 struct property *prop;
417 const __be32 *p;
418 u32 bank_width;
Gregory Fong19a7b692015-07-31 18:17:43 -0700419 int num_banks = 0;
Gregory Fong3b0213d2015-05-28 19:14:05 -0700420 int err;
421 static int gpio_base;
422
423 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
424 if (!priv)
425 return -ENOMEM;
Gregory Fong22526072015-06-17 18:00:40 -0700426 platform_set_drvdata(pdev, priv);
427 INIT_LIST_HEAD(&priv->bank_list);
Gregory Fong3b0213d2015-05-28 19:14:05 -0700428
429 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
430 reg_base = devm_ioremap_resource(dev, res);
431 if (IS_ERR(reg_base))
432 return PTR_ERR(reg_base);
433
434 priv->gpio_base = gpio_base;
435 priv->reg_base = reg_base;
436 priv->pdev = pdev;
437
Gregory Fong19a7b692015-07-31 18:17:43 -0700438 if (of_property_read_bool(np, "interrupt-controller")) {
439 priv->parent_irq = platform_get_irq(pdev, 0);
440 if (priv->parent_irq <= 0) {
441 dev_err(dev, "Couldn't get IRQ");
442 return -ENOENT;
443 }
444 } else {
445 priv->parent_irq = -ENOENT;
446 }
447
Gregory Fong3b0213d2015-05-28 19:14:05 -0700448 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
449 return -EINVAL;
450
451 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
452 bank_width) {
453 struct brcmstb_gpio_bank *bank;
454 struct bgpio_chip *bgc;
455 struct gpio_chip *gc;
456
457 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
458 if (!bank) {
459 err = -ENOMEM;
460 goto fail;
461 }
462
463 bank->parent_priv = priv;
Gregory Fong19a7b692015-07-31 18:17:43 -0700464 bank->id = num_banks;
Gregory Fong3b0213d2015-05-28 19:14:05 -0700465 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
466 dev_err(dev, "Invalid bank width %d\n", bank_width);
467 goto fail;
468 } else {
469 bank->width = bank_width;
470 }
471
472 /*
473 * Regs are 4 bytes wide, have data reg, no set/clear regs,
474 * and direction bits have 0 = output and 1 = input
475 */
476 bgc = &bank->bgc;
477 err = bgpio_init(bgc, dev, 4,
478 reg_base + GIO_DATA(bank->id),
479 NULL, NULL, NULL,
480 reg_base + GIO_IODIR(bank->id), 0);
481 if (err) {
482 dev_err(dev, "bgpio_init() failed\n");
483 goto fail;
484 }
485
486 gc = &bgc->gc;
487 gc->of_node = np;
488 gc->owner = THIS_MODULE;
489 gc->label = np->full_name;
490 gc->base = gpio_base;
491 gc->of_gpio_n_cells = 2;
492 gc->of_xlate = brcmstb_gpio_of_xlate;
493 /* not all ngpio lines are valid, will use bank width later */
494 gc->ngpio = MAX_GPIO_PER_BANK;
495
Gregory Fong3afa1292015-07-31 18:17:44 -0700496 /*
497 * Mask all interrupts by default, since wakeup interrupts may
498 * be retained from S5 cold boot
499 */
500 bank->bgc.write_reg(reg_base + GIO_MASK(bank->id), 0);
501
Gregory Fong3b0213d2015-05-28 19:14:05 -0700502 err = gpiochip_add(gc);
503 if (err) {
504 dev_err(dev, "Could not add gpiochip for bank %d\n",
505 bank->id);
506 goto fail;
507 }
508 gpio_base += gc->ngpio;
Gregory Fong19a7b692015-07-31 18:17:43 -0700509
510 if (priv->parent_irq > 0) {
511 err = brcmstb_gpio_irq_setup(pdev, bank);
512 if (err)
513 goto fail;
514 }
515
Gregory Fong3b0213d2015-05-28 19:14:05 -0700516 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
517 gc->base, gc->ngpio, bank->width);
518
519 /* Everything looks good, so add bank to list */
520 list_add(&bank->node, &priv->bank_list);
521
Gregory Fong19a7b692015-07-31 18:17:43 -0700522 num_banks++;
Gregory Fong3b0213d2015-05-28 19:14:05 -0700523 }
524
525 dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
Gregory Fong19a7b692015-07-31 18:17:43 -0700526 num_banks, priv->gpio_base, gpio_base - 1);
Gregory Fong3b0213d2015-05-28 19:14:05 -0700527
Gregory Fong3b0213d2015-05-28 19:14:05 -0700528 return 0;
529
530fail:
531 (void) brcmstb_gpio_remove(pdev);
532 return err;
533}
534
535static const struct of_device_id brcmstb_gpio_of_match[] = {
536 { .compatible = "brcm,brcmstb-gpio" },
537 {},
538};
539
540MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
541
542static struct platform_driver brcmstb_gpio_driver = {
543 .driver = {
544 .name = "brcmstb-gpio",
545 .of_match_table = brcmstb_gpio_of_match,
546 },
547 .probe = brcmstb_gpio_probe,
548 .remove = brcmstb_gpio_remove,
549};
550module_platform_driver(brcmstb_gpio_driver);
551
552MODULE_AUTHOR("Gregory Fong");
553MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
554MODULE_LICENSE("GPL v2");